JP2804044B2 - Disk unit - Google Patents

Description

The present invention relates to a magnetic disk device having a built-in microprocessor, a magnetic disk device having a built-in magnetic disk controller, and an automatic positioning of a window of a phase synchronization circuit in an optical disk device. The present invention relates to an adjustment method for adjusting to an optimal position.

[Conventional technology]

In a system such as a magnetic disk device, a phase synchronization circuit used for generating and demodulating a recording signal generally has a block configuration shown in FIG. PLL (Phase
A look-up loop) circuit 58, a delay element 55 with tap, a data discriminating circuit 56 composed of a latch and the like, and a decoder 57 also perform demodulation.

Further, the PLL circuit 58 includes a phase comparator 51, a charge pump 5
2. It comprises a loop filter 53 and a voltage controlled oscillator 54. To reproduce and demodulate the recorded signal, use the playback signal RAWR
D is input to the PLL circuit 58. The phase comparator 51 outputs the reproduction signal RAWR
The phase of D and the clock (VCOCLK) of the VCO 54 output are compared, and an INC pulse or DEC pulse with a time width proportional to the phase difference is output.

The charge pump 52 outputs a current or a voltage in response to the INC pulse and the DEC pulse. The loop filter 53 is
The output of the charge pump 52 is integrated and smoothed, and the VCO 54 changes the frequency of the output clock in proportion to the integrated and smoothed voltage.

As described above, the PLL circuit 58 operates to make the phase of the output clock of the VCO 54 coincide with the phase of the reproduced signal RAWRD. Next, the operations of the tapped delay line 55 and the data discrimination circuit 56 will be described with reference to a time chart shown in FIG. First playback signal RAWRD
It is assumed that the phase of VCOCLK, which is the output of the VCO 54, and the phase of VCOCLK, which are completely matched by the PLL circuit 58, are obtained. The tapped delay line 55 delays the reproduction signal RAWRD by a half cycle time of VCOCLK. Thus, the setup time of the output of the delay line 55 with respect to VCOCLK in the data discrimination circuit 56 constituted by the latch is VOCL
It is a half cycle of K and has an optimal phase relationship.

Generally, in a disk device, a peak shift phenomenon occurs in a reproduction signal RAWRD due to magnetization interference due to magnetization reversal of a medium. The range in which this peak shift can be tolerated is called a window margin and is a major factor in determining the performance of the disk drive. In order to maximize the window margin, high accuracy is required for the setup time of the input data of the data discrimination circuit 56. As mentioned earlier, the playback signals RAWRD and VCO
If the phase of the CLK completely matches and the tapped delay line 55 delays exactly by the half cycle time of VCOCLK, the window margin is maximized. However, as shown in FIG. In many cases, the phase difference between the reproduced signal RAWRD and VCOCLK does not become zero in a stable synchronization state due to the performance of the above.

This phase shift further changes due to temperature fluctuation. In this case, the window margin is not maximized even if the tapped delay line 55 delays exactly by a half cycle time of VCOCLK. Conventionally, leave this window margin loss or
The delay amount of the tapped delay line was manually adjusted. However, if the adjustment causes a cost increase and the phase shift in the synchronized state described above fluctuates due to the temperature, or if the delay amount of the tapped delay line 55 fluctuates due to the temperature, the loss of the window margin is adjusted. I can't do it.

In order to solve this problem, Japanese Patent Application Laid-Open No. Sho 59-161813 discloses a method of providing a delay amount adjusting circuit, inputting data delayed by a known amount to a phase synchronization circuit, and determining whether or not an error has occurred. Measure the amount of phase shift between
The process of adjusting the phase shift amount to an appropriate value has been performed at regular intervals. In addition, if the host starts the operation of accessing the disk during the adjustment process, the adjustment process is interrupted, and the adjustment process is re-executed when the host access is completed.

[Problems to be solved by the invention]

The above-mentioned prior art requires data delayed by a known amount, so that a high accuracy is required for the tapped delay line, and temperature drift and aging of the tapped delay line are not considered. There was a problem with the point.

In the related art, since the controller in the phase synchronization circuit determines whether or not to perform the adjustment processing, the disk access operation may overlap with the adjustment processing from the host or the disk controller. In that case, the adjustment processing is interrupted. And the interruption can occur at any time and is therefore poorly coordinated,
The phase synchronization circuit operates by disk access from the host or the disk controller.

SUMMARY OF THE INVENTION It is an object of the present invention to provide an automatic phase adjustment method capable of always adjusting a phase shift so as to maximize a window margin without being affected by variations in delay amount accuracy of a delay line, temperature drift and aging.

[Means for solving the problem]

In order to achieve the above object, a disk drive according to the present invention includes a PLL that generates a clock pulse synchronized with an input pulse waveform signal, and a window adjustment that performs phase adjustment between the pulse waveform signal and the clock pulse using control data. A phase synchronization circuit including means for receiving the phase-adjusted pulse waveform signal and the clock pulse and discriminating the data using a window based on the clock pulse; and the discrimination means discriminates. Window abnormality detecting means for determining whether an error has occurred in the data;
Means for setting a plurality of second data for setting various window timings as the control data, and indicating whether an error has occurred in data discriminated using each of the plurality of second data. Means for acquiring data from the window abnormality detecting means, means for calculating first data using the acquired data, and means for setting the first data as the control data.

[Action]

The window adjustment circuit adds one of the delay amounts according to the regulation of the arithmetic progression selected by a command from the microprocessor to the input data.

In the normal mode, the optimum delay amount obtained as a result of the adjustment is added to the input data.

The window abnormality detection circuit monitors the reproduced data signal and detects that an error has occurred outside the window.

When detecting that there is no disk access command from the host or the disk controller, the microprocessor starts window adjustment processing, and the window adjustment circuit and the window abnormality detection circuit use the maximum delay amount among the delay amounts that can be reproduced and demodulated. And the information for selecting the minimum delay amount are detected. Thereafter, the microprocessor calculates the information in the form of internal differentiation using the two pieces of information, calculates information for selecting an optimal delay amount, and designates the information to the window adjustment circuit. Through these processes, the required delay amount is selected in a relative internal differentiation manner, and therefore does not particularly depend on the accuracy and temperature of the delay element.

Further, the above adjustment processing is performed at a time other than when the host or the disk controller accesses the disk under the management of the microprocessor in the disk device. Therefore, when the host or the disk controller accesses the disk, the window of the phase synchronization circuit is Is kept in optimal condition.

Further, before performing the window adjustment processing, the microprocessor sends the information waiting for the disk access operation to the host or the disk controller, and then performs the adjustment processing, or performs the window adjustment processing by the disk access from the host or the disk controller. , The window of the phase-locked loop can be maintained in an optimal state.

〔Example〕

The overall configuration of a disk drive embodying the present invention will be described with reference to FIGS.

In the case of FIG. 2, the disk device incorporates a disk controller (hereinafter referred to as HDC), a disk disk 19 for recording data, a head 20 for converting data on the disk disk into an electric signal, and an output of the head 20. Read / write AMP14 or read / write AMP14
Waveform shaping 13, which shapes the output of the
The phase synchronization circuit 12 of the present invention, which discriminates the data from the output of the phase shifter and converts it into NRZ data (NRZRD) or conversely encodes the input NRZ data (NRZWD) into a recording code, directly converts the data from the output of the phase circuit. HD that converts parallel data to extract parallel data or conversely converts parallel data from the host to serial data in a format unique to the disk
C10, a host interface 11 for controlling the interface between the disk drive and the host 21, and the head 20
An actuator 16 and a control circuit 15 for positioning the disk on a target track, a spindle motor 18 and a control circuit 17 for rotating the disk 20 at a constant speed, and a microprocessor 9 for controlling all of these electronic circuits. You. Here, the microprocessor 9 controls all electronic circuits. However, a microprocessor may be added for actuator control and spindle motor control.

In the disk system 23, the window adjustment processing of the phase synchronization circuit 12 is performed by the microprocessor 9.
However, when the added microprocessor can directly or indirectly detect a disk access command from the host or the disk controller, the execution can be performed by the added microprocessor.

Next, FIG. 3 shows the overall configuration of a disk device without a built-in disk controller.
The microprocessor 9 performs window adjustment processing of the phase synchronization circuit 12.

Next, a microprocessor 9 for performing interface control with a host or a disk controller and a phase synchronization circuit
The window adjustment with 12 will be described with reference to FIG.

The phase synchronization circuit 12, which is a main circuit of the present invention, includes a PLL1, a delay element having a delay amount according to a plurality of arithmetic progression rules, and a window configured to select and output one of the plurality of delay amounts. An adjustment circuit 3, a data discrimination circuit for discriminating data from an output clock of the PLL 1 and an output of the window adjustment circuit 3, a window abnormality detection circuit 5 for detecting a window abnormality of the window adjustment circuit 3 from an output of the data discrimination circuit 4,
And a decoder 6 for decoding the reproduction signal into NRZ data (NRZRD), and NRZ data (NRZRD) from the disk controller.
WD) to a recording code, a reference clock for encoding the encoder, and a reference signal generation circuit 7 for generating a test signal (TEST SIG) to be input to the PLL 1 and the window adjustment circuit 3 in the window adjustment mode. In accordance with the adjustment mode and the normal mode, data input to the PLL 1 and the window adjustment circuit 3 are read from the disk.
Output test signal from RAWRD or reference signal formation 7 (TEST SI
G).

When detecting that there is no disk access command from the host or the disk controller, the microprocessor 9 outputs a command to the terminal of the switching circuit 2 to connect the terminal and negates the reset of the window abnormality detection circuit 5. Then, the phase synchronization circuit 12 is set to the adjustment mode. The microprocessor 9 starts the operation after waiting for the phase synchronization of the PLL 1 to be completed. The TEST SIG is delayed by a delay element in the window adjustment circuit, and the amount of the delay is determined by a set value N to a selector in the window adjustment circuit of the microprocessor 9. The plurality of delay amount (delay _{amount) N = t c + N ×} t 2 t c: is determined by the adjustment delay amount: constant delay amount N: value determined rely on the set value of the selector (integer) t _d .

Assuming that N = No before the adjustment, the microprocessor changes the set value to N = No-1, No-2,..., No-m as shown in FIG.
Monitor the output of When the window abnormality detection circuit 5 detects an abnormality at N = No-m, the microprocessor 9 records the value of (No-m). Next, in the opposite direction, the microprocessor 9 changes the set value to N = No + 1, No + 2,... N = No + n, and when the window abnormality detection circuit 5 detects an abnormality when N = No + n, the same as described above. The microprocessor 9 stores the value of No + n at that time. Thereafter, the microprocessor 9 performs an operation of T = {(No-m) + (No + n)} / 2 using the values (No-m) and (No + n) detected by the above processing, and obtains the result by this operation. The value T is set in the selector of the window adjustment circuit 3. If T is not an integer, then T
Let T be the nearest integer of.

As described above, since the window adjustment processing has been completed, the microprocessor 9 issues a designation to the switching circuit 2 and outputs the designation to the switch 2.
To reset the window abnormality detection circuit 5, and set the mode from the adjustment mode to the normal mode.

However, the microprocessor 9 sets the phase synchronization circuit to N = No−1, No
-2 ... or N = No + 1, No + 2 ... and it is not necessary to set all the setting values in the window.
And (No + n) can also be detected.

Here, in this embodiment, the test signal TESTSIG is a 4T pattern (10001000...), And in that case, the window abnormality detection circuit 5 detects the difference between the 5-bit shift register and the two signals as shown in FIG. And two flip-flops that latch the result.

When the phase of the output of the window adjustment circuit 3 deviates from the window of the data discrimination circuit 4, the output of the data discrimination circuit becomes a 4T pattern (1000) as shown in FIG.
From 1000…) to 3T (100100…).

An abnormality is detected by detecting the change with a flip-flop.

Above is a test pattern of 4T for detecting window anomalies
Is an example of the configuration of the window abnormality detection circuit in the case of, but when the test signal TEST SIG is a 3T pattern (100100 ...), 5
All that is required is to change the bit shift register to 4 bits. Further, the test signal does not cause any problem except for the 3T pattern and the 4T pattern. In that case, the bit number of the shift register in the window abnormality detection circuit 5 may be changed.

Here, the microprocessor 9 performs the window adjustment process when there is no disk access command from the host or the disk control. However, if the microprocessor 9 performs a window access process from the host or the disk controller during the window adjustment process. At times, ESDI (En
In a disk device having a hance small device interface, the microprocessor 9 may perform processing such as negating the READY signal or setting NRZRD data to a fixed level before performing window adjustment processing.

In a disk device with a built-in disk controller such as SCSI (Small Computer System Interface), the microprocessor 9 outputs the status of the disk access weight, or sends a disk access command from the host or the disk controller during window adjustment processing. It may be temporarily stored, and after the window adjustment processing is completed, the stored disk access command from the host or the disk controller may be executed.

〔The invention's effect〕

According to the present invention, by using a simple window adjustment circuit including a low-cost delay element that does not require the absolute accuracy of the delay amount and a simple window abnormality detection circuit, the window of the phase synchronization circuit can be accurately discarded by the microprocessor. Since automatic adjustment can be performed at any time other than access, a high-performance device can be realized, which has a great effect on cost reduction of the device.

Also, since the delay element can be realized by a semiconductor delay,
A phase synchronization circuit incorporating a window adjustment circuit and a window abnormality detection circuit can be integrated on a single chip.

In this case, the cost can be reduced by using the LSI, and the area occupied by the substrate of the phase synchronization circuit of the disk device can be greatly reduced.

[Brief description of the drawings]

FIG. 1 is a circuit diagram of a phase locked loop according to an embodiment of the present invention.
FIG. 3 is a circuit diagram showing the overall configuration of an embodiment of the disk drive of the present invention, FIG. 3 is a circuit diagram showing the overall configuration of another embodiment of the disk drive of the present invention, and FIG. 4 is a timing chart showing window adjustment timing. FIG. 5, FIG. 5 is a circuit diagram showing the configuration of the window abnormality detection circuit, FIG. 6 is a timing diagram showing the operation timing of the window abnormality detection circuit, FIG. 7 is a circuit diagram showing the configuration of the conventional phase locked loop circuit. FIG. 8 is a timing chart showing the operation timing of the conventional phase locked loop circuit. 1 PLL (Phased Locked Loop) 2… Switching circuit 3… Window adjustment circuit 4… Data discrimination circuit 5… Window abnormality detection circuit 6… Decoder 7… Reference signal generation 8… Encoder , 9 Microprocessor 10 Disk controller (HDC) 11 Host interface 12 Phase synchronization circuit 13 Waveform shaping 14 Read / write AMP 15 Actuator control 16 Actuator 17 ... Spindle motor control 18 ... Spindle motor, 19 ... Disk disk 20 ... Head, 21 ... Host 22 ... Host or disk controller 23 ... Disk device with built-in disk controller 24 ... Disk device, 55 ... Tap Attached delay line 56 Data discriminator circuit 57 Decoder 58 Conventional PLL circuit

──────────────────────────────────────────────────続 き Continuing on the front page (72) Inventor Kenichi Hase 292 Yoshida-cho, Totsuka-ku, Yokohama-shi, Kanagawa Prefecture Inside Microelectronics Device Development Laboratory, Hitachi, Ltd. Address Hitachi, Ltd. Takasaki Factory (56) References JP-A-61-287347 (JP, A) JP-A-60-50755 (JP, A) JP-A-52-55618 (JP, A) JP 58-182117 (JP, A) JP-A-63-10824 (JP, A) JP-A-59-45615 (JP, A) JP-A-63-107231 (JP, A) JP-A-59-113517 (JP, A) A) (58) Field surveyed (Int. Cl. ⁶ , DB name) G11B 20/10-20/14 H03L 7/00

Claims (10)

(57) [Claims] 1. A disk device for discriminating data from a read signal read from a disk-shaped recording medium, comprising: a PLL for generating a clock pulse synchronized with an input pulse waveform signal; Window adjusting means for adjusting the phase of a signal and the clock pulse, and discriminating means for discriminating the data using a window based on the clock pulse in which the pulse waveform signal and the clock pulse whose phase has been adjusted are input. A window synchronization detecting means for determining whether or not an error has occurred in the data discriminated by the discriminating means; and setting a plurality of second data for setting various window timings as the control data. Means for determining whether an error has occurred in data discriminated using each of the plurality of second data items A means for acquiring data indicating the above from the window abnormality detecting means, means for calculating first data using the acquired data, and means for setting the first data as the control data. A disk device comprising a processor and. 2. The disk device according to claim 1, wherein the control data is a phase amount representing time. 3. The disk drive according to claim 1, wherein said window adjusting means includes delay means for delaying said pulse waveform signal in accordance with a delay amount indicated by said control data. 4. The disk device according to claim 1, wherein said microprocessor sets a plurality of said second data as control data, and said microprocessor is capable of setting based on said acquired data. A disk device comprising: means for storing a maximum delay amount and a minimum delay amount; and means for calculating the first data from the allowable maximum delay amount and the minimum delay amount. 5. The disk device according to claim 1, wherein said microprocessor sets a plurality of said second data when said disk device is not performing a read operation, and sets an error. A disk device configured to acquire data indicating whether or not the error has occurred and calculate and set the first data. 6. A disk device for discriminating data from a read signal read from a disk-shaped recording medium, comprising: a PLL for generating a clock pulse synchronized with an input pulse waveform signal; Window adjusting means for adjusting the phase of a signal and the clock pulse; discriminating means for receiving the phase-adjusted pulse waveform signal and the clock pulse and discriminating the data using a window based on the clock pulse; A window abnormality detecting means for determining whether an error has occurred in the data to be distinguished by the discriminating means; a means for setting a plurality of second data for setting various window timings as the control data; Data indicating whether an error has occurred in the data discriminated using each of the second data, A microprocessor having means for acquiring from the window abnormality detecting means, means for calculating first data using the acquired data, and means for setting the first data as the control data. Disk device. 7. The disk device according to claim 6, wherein said control data is a phase amount representing time. 8. The disk drive according to claim 6, wherein said window adjustment means includes delay means for delaying said pulse waveform signal in accordance with a delay amount indicated by said control data. 9. The disk drive according to claim 6, wherein the microprocessor sets a plurality of the second data as control data, and the microprocessor is capable of setting based on the acquired data. A disk device comprising: means for storing a maximum delay amount and a minimum delay amount; and means for calculating the first data from the allowable maximum delay amount and the minimum delay amount. 10. The disk device according to claim 6, wherein said microprocessor sets a plurality of said second data when said disk device is not performing a read operation, and sets an error. A disk device configured to acquire data indicating whether or not an error has occurred and calculate and set the first data.