JP2804194B2 - Transmission data transceiver - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a transmission data transmission / reception apparatus applied to, for example, a digital protection relay used for protection of a transmission line of a power system.

[0002]

2. Description of the Related Art In a digital protection relay device using a microcomputer, system information is transmitted by PCM (Pu).
The introduction of carrier relays is being promoted in which transmission and reception are performed between electric substations in the form of one-code modulation (lse code modulation).

[0003] In this type of comparative protection relay device, in particular, after sampling instantaneous values of system information at two points of a transmission line of a power system at a fixed cycle and performing A / D conversion, for example, a microwave line or the like is used. The transmission line is mutually transmitted to the partner device using a communication line, and the system failure of the transmission line is monitored by comparing the value of the own device with the received value.

The above-mentioned comparative protective relay has recently been applied to a relatively low voltage class (154 K volts or less) of a power system, and conventionally applied to a relatively high voltage class (154 K volts or more). Unlike the point-to-point transmission system configuration, a transmission system in which two or more points and eight points are connected in a loop is employed. For this reason, the transmitted data is cascaded through the communication line between the points and the protection relay device.

[0005] On the communication line, a stuff-type multiplex conversion device that generally collects information other than the protection relay device is installed, and performs multiplexing / demultiplexing operations.

[0006] In the multiplexing-side input section of the multiplex conversion device, a memory is provided for synchronizing asynchronous signals, and data is input and output without delay. Also, the separation side output unit is provided with a memory for converting a non-synchronous asynchronous signal from which stuff bits have been removed into a signal which is smoothed and averaged by a phase control circuit (PLO).

On the multiplexing side, no signal is lost because the frequency of the synchronous signal is higher than the frequency of the asynchronous signal. In addition, the phase comparator of the write clock and the read clock for the memory and the characteristics of its PLO are very important issues.

The protection relay has a circuit having almost the same function as the multiplexing-side input section / separation output section of the stuff multiplex conversion. This circuit inputs the transmission data, stores it in the memory, compares the phase with the read clock to suppress the frequency of the write clock to the memory, and uses the loop filter to transmit with the smoothed read clock. It has a function to output data.

FIG. 2 shows, for example, a document “PLL application circuit”.
A conventional stuff synchronous receiver (corresponding to a demultiplexed output unit of a stuff multiplex converter) shown in (Sogo Denshi Publisher)
FIG. In the figure, 1 is a write clock, 2 is a memory, 3 is a read clock, 4 is a phase comparator for comparing the phases of the write clock 1 and read clock 3, and 5 is a loop filter for smoothing the output signal of the phase comparator 4. , 6 are voltage-controlled oscillators (VCOs) whose transmission frequency is variable based on the signal smoothed by the loop filter.

In this configuration, when the phase comparator 4 determines that there is no phase difference between the write clock 1 and the read clock 3, the voltage controlled oscillator 6 generates a frequency synchronized with the write clock 1, and Clock 3
Are also synchronized, so that the data written in the memory is read without being missed. At this time, since the result determined by the phase comparator 4 passes through the loop filter 5, for example, in the case of a low-pass filter, a response delay time occurs according to the filter characteristic. Therefore, when the frequency of the write clock 1 fluctuates, the read clock 3 follows and synchronizes without any delay time.
Loop filter 5 must be a primary loop filter.

When the phase comparator 4 determines that there is a phase difference between the write clock 1 and the read clock 3,
A logic signal corresponding to the phase difference is generated. This logic signal is generated by the low-pass filter characteristic of the loop filter 5
The signal is converted into a smoothed signal, and a voltage difference corresponding to the phase difference is generated. The oscillation frequency of the output of the voltage-controlled oscillator 6 is shifted according to the voltage difference, and the phase of the read clock 3 is shifted so that the phase difference is eliminated.

[0012]

In the demultiplexing circuit of the multiplex converter, the loop filter generally has the following formula (1).
A second-order low-pass filter having a cutoff frequency of 0 Hz is employed. When the frequency of the write clock 1 fluctuates, the read clock 3 follows with a time delay according to the filter characteristics. At this time, if the data cannot be followed, the write clock 1 and the read clock 3 are out of synchronization, and data read from the memory 2 is lost or duplicated. This corresponds to the initial state, for example, when the control power is applied and the write clock 1 and the read clock 3
This is particularly noticeable during the period until the phase difference disappears.

Therefore, the device for receiving the output from the demultiplexing circuit of the multiplex conversion device judges that the fault is not on the communication line but the fault on the communication line even though the fault is not on the communication line. There is a problem that time is wasted unnecessarily.

SUMMARY OF THE INVENTION The present invention has been made to solve this problem, and an abnormality in an upstream device such as a loss of synchronization between a write clock and a read clock for a memory storing an input signal is caused by a transmission failure occurring on a communication line. It is an object of the present invention to provide a transmission data transmission / reception device that can prevent erroneous determination that the transmission data is transmitted, and can improve reliability compared to the related art.

[0015]

According to the present invention, there is provided a memory for holding an input signal received through a transmission line, a write clock for writing the input signal to the memory, A read clock for reading the input signal, a phase comparator for comparing the phases of the write clock and the read clock, a loop filter for smoothing the output of the phase comparator, and an oscillation frequency according to the smoothed signal A transmission / reception device comprising a voltage-controlled oscillator for changing the phase difference between the write clock and the read clock; and a phase determiner for determining whether a phase difference between the write clock and the read clock is within an allowable value. replacer to be transmitted to the upper Symbol transmission path a signal read out from the memory if it is outside by substituting other signals The provided, has a structure the other signal to be decrypted in accordance with predetermined arrangements.

According to the second aspect of the present invention, the predetermined rule for the another signal is out of synchronization between the two clocks and is not interpreted as a transmission failure on the communication line.

[0017]

According to the present invention, when the write clock is out of synchronization with the read clock, another signal is sent out instead of the signal read from the memory, and this signal is not a transmission failure. Can be prevented from being erroneously determined as a transmission failure on the communication line on the side receiving this.

[0018]

An embodiment of the present invention will be described below with reference to the drawings.

In FIG. 1, reference numeral 7 denotes a phase determiner,
The phase comparison between the write clock 1 and the read clock 3 is performed, and when the phase difference between the two exceeds a predetermined value, the determination result is sent to the replacement unit 8. The replacement unit 8 replaces the signal output from the memory 2 with a preset signal based on the determination result. Other configurations are the same as those in FIG.

In this configuration, when the phase difference between the write clock 1 and the read clock 3 is equal to or smaller than a predetermined value, the phase determiner 7 outputs a determination result "GOOD". Upon receiving this determination result, the replacement unit 8 passes the signal from the memory 2 as it is.

Write clock 1 and read clock 3
Is greater than or equal to the predetermined value, the phase determiner 7 outputs a determination result “NG”. The replacement unit 8 receiving this determination result keeps the determination result “NG” being input while the replacement unit 8 continues to input.
Instead of a signal input from the memory 2, for example, logic "1"
Is output. The device that receives this signal has a rule in advance that if a logical “1” is received for a certain period of time or longer, it is not determined that a transmission failure has occurred on the communication line, and the device does not detect the transmission failure. When the phase difference between the write clock 1 and the read clock 3 returns within a predetermined value, the phase determiner 7 outputs a determination result “GOOD”. No replacement operation is performed.

Therefore, in this embodiment, when the write clock 1 and the read clock 3 are out of synchronization, the signal read from the memory 2 is transmitted instead of another signal,
Since it is a promise that this other signal is not a transmission failure as described above, on the receiving side, it is necessary to avoid erroneous determination of loss of synchronization between the two clocks as a transmission failure on the communication line. Can be.

In the above embodiment, when the determination result of the phase determination unit 7 is "NG", the replacement unit 8 forcibly replaces the output signal from the memory 2 with the logic "1". Is an agreement with the receiving side, so that logic "0" may be output continuously, or logic "1" and logic "0" may be alternately repeated.

Further, in the above embodiment, when the judgment result of the phase judging device 7 is “NG”, the replacing device 8
Is forcibly replaced with a logic "1" or the like for a certain period of time, and continues to be replaced even if the determination result of the phase determiner 7 returns to "GOOD". After continuously determining “GOOD”, the replacement unit 8 may be configured not to perform the replacement operation on the output signal.

In this embodiment, the frequency of the input signal can also be monitored.

[0026]

As described above, according to the present invention, when the write clock is out of synchronization with the read clock, a signal is transmitted assuming that there is no transmission failure until the synchronization is restored. It is possible to avoid erroneous determination of a disconnection as a transmission failure and wasteful time pursuing the failure, and reliability can be improved as compared with the related art.

[Brief description of the drawings]

FIG. 1 is a lock diagram showing an embodiment of the present invention.

FIG. 2 is a block diagram of a conventional staff synchronization receiving circuit.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Write clock 2 Memory 3 Read clock 4 Phase comparator 5 Loop filter 6 Voltage controlled oscillator 7 Phase judging device 8 Substitution device

Claims (2)

(57) [Claims] 1. A memory for holding an input signal received through a transmission line, a write clock for writing the input signal to the memory, a read clock for reading the input signal from the memory, the write clock and the read In a transmission data transmitting / receiving apparatus comprising: a phase comparator for comparing the phases of clocks; a loop filter for smoothing the output of the phase comparator; and a voltage-controlled oscillator for changing an oscillation frequency according to the smoothed signal. A phase determiner for determining whether a phase difference between the write clock and the read clock is within an allowable value, and a signal read from the memory when the phase determination result is out of the allowable value. and a replacement unit to be transmitted to the upper Symbol transmission path substitutions to the signal, the further signal is interpreted in accordance with predetermined arrangements A transmission data transmission / reception device, characterized in that: 2. The transmission data transmitting / receiving apparatus according to claim 1, wherein the predetermined rule for another signal is out of synchronization between the two clocks and is not interpreted as a transmission failure on the communication line.