JP2806026B2 - Memory test circuit - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a memory test circuit for testing a plurality of memories built in an LSI.

2. Description of the Related Art Conventionally, when testing a memory such as a ROM built in an LSI, data stored in the ROM is sequentially read out of the LSI, and the read data and an expected output value prepared in advance are read out. Are sequentially compared to detect a match / mismatch between the two, and based on the detection result, it is determined whether the memory is a good or a bad memory.

On the other hand, in recent years, the integration and multi-functionality of LSIs have been advanced, and the number of cases in which 5 to 6 ROMs are built in one LSI has increased. In this case, according to the conventional memory test method, reading the read data from all the ROMs at once to the outside of the LSI is
Since it is not possible due to the limitation of the number of external terminals, that is, the chip size, the built-in ROMs are tested one by one in order.

[Problems to be Solved by the Invention] However, in such a conventional memory test method, a plurality of ROMs built in an LSI are tested one by one in order. This increases the test time.

Also, for LSIs in which data in the built-in ROM is not read out externally in normal operation, the above-described test method requires an external terminal for data reading of at least about 4 to 16 bits. In addition, there is also a problem that the package size is increased and the cost is increased.

The present invention has been made to solve such a conventional problem, and can complete a memory test in a short time regardless of the number of memories built in an LSI. It is an object of the present invention to provide a memory test circuit capable of greatly reducing the number of external terminals required for the test.

[Means for Solving the Problems] A memory test circuit according to the present invention is a memory test circuit built in a semiconductor integrated circuit including a plurality of memories together with the memories, wherein each of the memories is serially supplied simultaneously from the outside. A plurality of expected value holding means each comprising a shift register for holding an expected output value of the memory and outputting the data as parallel data; an expected output value of each memory held by the expected value holding means and data read from each memory; And a plurality of comparing means for detecting coincidence / mismatch of the two by simultaneously and in parallel with each other, and detecting that the output of these comparing means includes a result of mismatch detection and outputting a test result signal to the outside. Test result output means.

According to the present invention, when the expected output value of each memory is given from the outside to the plurality of expected value holding means at the same time, the expected value holding means holds the same, and the plurality of comparing means further stores the expected value. And the read data from a plurality of memories are compared simultaneously and in parallel to detect a match / mismatch between them, so that a memory test for a plurality of built-in memories can be performed simultaneously, and the test time can be reduced. Shortening can be achieved.

Further, according to the present invention, only the test result signal indicating whether or not the comparison result from the plurality of comparison means includes a mismatch detection result is taken out to the outside and is determined. There is no need to take out the read data directly to the outside. Therefore, an external terminal for reading data is not required, and the number of external terminals can be significantly reduced.

Hereinafter, embodiments of the present invention will be described with reference to the accompanying drawings.

FIG. 1 is a block diagram showing an LSI according to an embodiment of the present invention.

The LSI 1 has two ROMs 11 and 12 built therein. RO
M11 is, 4 bits of the address from the address bus AB A ₀ ~A
Specifying ₃ by outputs a 4-bit data D ₁₀ to D _13, and a capacity of 2 ⁴ = 16 words. Also, ROM1
2 is a 5-bit address A _{0 to} A ₄ from the address bus AB
And it outputs the 5-bit data D ₂₀ to D ₂₄ with the specified, and a capacity of 2 ⁵ = 32 words.

The LSI 1 also has external input terminals 13 and 14 for serially inputting expected output values E ₁ and E ₂ of the ROMs 11 and 12 at the time of testing. Output expectation value E ₁ inputted from the external input terminal 13, a shift register of serial-in / parallel-out is the expected value holding means (hereinafter, abbreviated as S / P.) Are inputted to the 15 serial input terminal SIN of I have. S / P15 is the output expectation value E ₁ sequentially shifted in accordance with the master clock phi _M, parallel data E ₁₀ 4-bit,
And outputs the _{E 11, E 12, E 13} . Further, the expected output value E ₂ input from the external input terminal 14 is the S / P 16
Is input to the serial input terminal SIN. S / P16 is the output expectation value E ₂ sequentially shifted in accordance with the master clock phi _M, of 5-bit parallel data _{E 20, E 21, E 22} , E 23, E 24
Is output. These S / Ps 15 and 16 hold the parallel data by a test signal TEST.

FIG. 2 is a diagram showing a more detailed configuration example of the S / P 15. That is, the S / P 15 is composed of four 1-bit latch circuits 41, 42, 43, and 44 of the same configuration connected in cascade, and each of the latch circuits 41 to 44 receives the output data from the preceding stage and the own stage by the test signal TEST. To select one of the output data
And D gate 51 and OR gate 53, is constituted by the data selected is outputted from the OR gate 53 and D-type flip-flop 54 for holding in accordance with the master clock phi _M. With such a configuration, shift-in of data when the test signal TEST is “1” is prohibited, and the expected output value can be held.

On the other hand, the output of ROM11,12 is supplied to each data bus DB _1, DB _2, is adapted to be latched in synchronism with the clock phi _A respectively latch circuits 17 and 18.

A read data D ₁₀ to D ₁₃ which is latched in the latch circuit 17,
The output expectation value data E ₁₀ to E ₁₃ given from the S / P15,
Exclusive OR gates (hereinafter, abbreviated as EX-OR) 21, 22, 23, and 24 as comparison means are used for comparison. The outputs of these EX-OR gates 21 to 24 are
Has been entered. The output of OR gate 25 is connected to AND gate 26
Is supplied to one of the input terminals. The other input terminal of the ADN gate 26, the signal obtained by inverting the address signal A ₄ by the inverter 27 is given.

In addition, the read data D _{20 to} D latched by the latch circuit 18 are
₂₄ and output expected value data E _{20 to} E ₂₄ given from S / P 16
Are compared by EX-OR gates 31, 32, 33, 34 and 35 which are comparison means. The outputs of these EX-ORs 31 to 35 are input to the OR gate 36.

The output of the AND gate 26 and the output of the OR gate 36 are
These signals indicate the match / mismatch between the read data 11 and 12 and the output expected value thereof, and these signals are input to the OR gate 37 which is the test result output means. Then, P / F (PASS / FAIL) indicating the test result, which is the output of the OR gate 37
The signal is output to the outside of the LSI 1 via the external output terminal 38.

Next, the operation of the LSI 1 of this embodiment configured as described above will be described.

FIG. 3 is a timing chart showing the operation of the LSI 1.

When the master clock φ output expectation value in synchronism with the _M E _1, E ₂ is serially input as shown in FIG. 3, the output expectation value E _1, E ₂ are sequentially respectively S / P15,16 Shift in. Here, the output expectation value E ₁ is 4-bit, because the output expectation value E ₂ is 5-bit data, in order to match the input timing of the two, the output expectation value E ₂ is 1 than the output expectation value E ₁ It will be input ahead by bits.

On the other hand, ROM11,12, the is given clock φ address A in the cycle shown in _{A 0} to A _4, read data D ₁₀ from ROM11,12
~D _13, D ₂₀ ~D ₂₄ is latched by the latch circuits 17 and 18.

When the expected output values E ₁ and E ₂ are all set in S / P15 and 16,
At the timing when the test signal TEST becomes “1”, the output expected values E ₁ and E ₂ are held in the S / Ps 15 and 16, and the read data D _{10 to} D ₁₃ and D _{20 to} D ₂₄ from the ROMs 11 and 12 are read. Is compared to As a result,
In the case of a non-defective product, the expected output value matches the read data, so that the P / F signal goes low. If even one bit does not match between the two, the P / F signal is
Since the high level is set, the non-defective product and the defective product can be determined.

In this embodiment, it has different capacity ROM11,12, when tested from address 0 in this order, testing ROM11 when the address signal A ₄ is set to "1" is finished first. Accordingly, the address signal A ₄ inverter 27
And the signal is supplied as one input of the AND gate 26, so that the EX-OR gate 2 after the test of the ROM 11 is completed.
The undefined outputs 1 to 24 are masked by the AND gate 26. Thus, it is possible to prevent the output of the comparing means after the test of the ROM 11 from affecting the test result of the ROM 12.

[Effects of the Invention] As described above, according to the present invention, the comparison means built in the LSI together with the memory compares the read data from the plurality of memories and the expected output value simultaneously and in parallel. A memory test for the built-in memory can be performed simultaneously. For this reason, the time required for the memory test can be significantly reduced as compared with the related art.

Further, according to the present invention, since only the test result signal is taken out to the outside, it is not necessary to take out the read data of the memory directly to the outside. For this reason, an external terminal for reading data is not required, and the number of external terminals can be significantly reduced as compared with the related art.

[Brief description of the drawings]

FIG. 1 is a block diagram of an LSI incorporating a memory test circuit according to an embodiment of the present invention, FIG. 2 is a detailed block diagram of a serial-in / parallel-out shift register in the memory test circuit, and FIG. FIG. 4 is a timing chart showing an operation of the circuit. 1; LSI, 11, 12; ROM, 13, 14; external input terminal, 15, 16; real-in / parallel-out shift register, 17, 18; latch circuit, 21 to 24, 31 to 35; EX-OR gate , 25, 36, 37, 53; OR gate, 26, 51, 52; AND gate, 38; external output terminal, 41-44;
1-bit latch circuit, 54; D-type flip-flop

Claims (1)

(57) [Claims] 1. A memory test circuit built in a semiconductor integrated circuit having a plurality of memories together with said memories, wherein said memory test circuits respectively hold expected output values of said memories serially supplied simultaneously from outside and store the parallel data as parallel data. A plurality of expected value holding means comprising a shift register for outputting, and an output expected value of each of the memories held in the expected value holding means and data read from each of the memories are compared simultaneously and in parallel to find a match between the two. / A plurality of comparing means for detecting a mismatch, and a test result output means for detecting that the output of the comparing means includes a mismatch detection result and outputting a test result signal to the outside. Memory test circuit.