JP2806028B2 - Method for manufacturing MOS type semiconductor device - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention suppresses short-channel effects and device characteristics deterioration caused by hot electrons which become apparent when miniaturizing a MOS type semiconductor device by using independent device structural elements. High density MOS for high reliability
The present invention relates to a method for manufacturing a semiconductor device.

2. Description of the Related Art In super-integrated circuit devices, so-called VLSI, MOS type integrated circuit devices have become increasingly important due to the demand for low power consumption and high integration. However, with the miniaturization, the degradation of the sub-threshold characteristics leads to a leakage current during standby. The so-called short channel effect and the deterioration of the hot elktron induced device characteristics caused by the high electric field near the drain become a serious problem for the miniaturization. Is coming.

Therefore, various structures and manufacturing processes have been proposed to solve this problem. Hereinafter, two points of (I) suppression of short channel effect and (II) suppression of hot electron degradation will be described.

For example, IEE, 1982 IEE
DM (IEEE.1982 IEDM) Technical Digest p.718
FIG. 3 shows a structure proposed by S. Ogura et al.

In the figure, 31 is a low-concentration substrate (p-type), 32 is a high-concentration p-type impurity layer, 33 is a p-type impurity layer for controlling a threshold voltage,
34 is a high concentration source / drain layer, 35 is a low concentration source / drain layer, 36 is a gate insulating film, 37 is a gate electrode, and 38 is an aluminum wiring.

In this structure, a low-concentration source / drain layer 35 and a high-concentration p-type impurity layer 32 are formed in a self-aligned manner by double ion implantation using the gate electrode 37 as a mask.
A high-concentration source / drain layer 34 is formed in a self-aligned manner using the mask 37 and the sidewall oxide film 38 as a mask.

The low-concentration source / drain layer 35 relieves a high electric field near the drain, improves hot electron degradation resistance, and suppresses the extension of potential from the drain layer by the high-concentration p-type impurity layer 32. The short channel effect that increases the parasitic capacitance between the substrates is suppressed.

1988 VLSI Symposium Technical Digest p. 73-
Figure 74 shows the structure proposed by CSOh et al.
It is shown in (c).

In the figure, 41 is a low concentration substrate (p-type), 42 is 0.1-
A source / drain layer comprising a shallow region having a depth of 0.15 μm and a deep region having a depth of 0.15-0.2 μm; 43, a gate insulating film; 44, a gate electrode; 45, an L-shaped side wall oxide film; 46
Is a sidewall nitride film, and 47 is a p-type impurity layer for controlling a threshold voltage. In this structure, the side wall nitride film 46 allows the L-
A side wall oxide film 45 is formed (FIG. 4B), and after removing the side wall nitride film 46, the gate electrode 44 and the L-shaped side wall oxide pattern 45 are used as a mask to perform 0.1 ion implantation. A source / drain 42 composed of a shallow region having a depth of −0.15 μm and a deep region having a depth of 0.15 to 0.2 μm is formed (FIG. 3C), and the shallow source / drain layer has a short channel effect. Contribute to suppression.

 As described above, two major proposals have been made.

However, these structures are still not sufficient. The structure shown in FIG. 3 has the following serious problems. High concentration p-type impurity layer 32 and low concentration source / drain layers
Since the layer 35 is formed in a self-aligned manner using the gate electrode 37 as a mask, the high-concentration p-type impurity layer 32 has a structure formed so as to surround the high-concentration source / drain layer 34 and the low-concentration source / drain layer 35. Has become. Although this is effective for suppressing the short-channel effect, the high-concentration p-type impurity layer is also formed on the side surface of the low-concentration source / drain layer 35. Resistance is significantly reduced.

The structure shown in FIG. 4C has the following problems. Since the source / drain layers are formed using the L-shaped side wall oxide film pattern 45 as a mask, the structure has a source / drain layer 42 having a shallow region of 0.1-0.15 μm. For this reason, the effect of suppressing the short channel effect can be expected to some extent, but the improvement in the resistance to hot elktron degradation cannot be expected to a great extent. The reasons are as follows: (1) The concentration value of the impurity layer in the shallow region of the source / drain layer 42 is reduced by only about 1.0E19 / cm ³ , and the hot electron deterioration resistance is not significantly improved.

(2) Since the source / drain layer 42 is formed using the gate electrode 44 and the L-shaped side wall oxide film pattern 45 as a mask, the overlap between the gate electrode 44 and the source / drain layer 42 is very small. In addition, the hot electron degradation resistance is not significantly improved.

(3) Since there is no high-concentration layer of the same conductivity type as the substrate other than the p-type impurity layer 47 for controlling the threshold voltage, the short channel effect becomes more pronounced as the device is miniaturized.

In other words, the conventional structure does not exhibit characteristics satisfying both the suppression of the short channel effect and the improvement of the hot electron degradation resistance in miniaturization. Therefore, the present invention has been made in view of such problems of the conventional structure, and is a manufacturing method of a MOS type semiconductor device using a new process.

Means for Solving the Problems According to the present invention, after a gate electrode is formed on a semiconductor substrate of a first conductivity type via a gate insulating film, a second source / drain of a second conductivity type is formed using the gate electrode as a mask. Forming a layer, depositing an L-shaped first insulating film covering both sides of the gate electrode and the surface of the semiconductor substrate on both sides of the gate electrode, and forming a second insulating film on the first insulating film; Depositing a film, and etching the second insulating film to form two insulating film patterns in a self-aligned manner so as to cover side surfaces of the L-shaped first insulating film; A first insulating film covering a side surface of the gate electrode and a second insulating film;
Forming a first source / drain layer using the insulating film pattern as a mask, and etching and removing the second insulating film pattern. Then, the gate electrode and the side surfaces of the gate electrode and the surface covering the semiconductor substrate surface are removed. -Shaped first
The first conductive type impurity is introduced using the insulating film as a mask,
Immediately below the second source / drain layer and on the side of the first source / drain layer, the second second source / drain layer
Forming a high-concentration layer having a maximum concentration value at a position deeper than the drain layer and shallower than the lower part of the first source / drain layer.

A step of forming a gate electrode on a semiconductor substrate of the first conductivity type via a gate insulating film, and then forming a second source / drain layer of the second conductivity type using the gate electrode as a mask; An L-shaped first insulating film covering the side surface of the gate electrode and the surface of the semiconductor substrate is deposited on both sides of the gate electrode, and the L-shaped first insulating film covering the side surface of the gate electrode and the side surface of the gate electrode and the surface of the semiconductor substrate is deposited. Forming a high-concentration layer by introducing an impurity of a first conductivity type using the first insulating film as a mask; and depositing a second insulating film on the first insulating film; After the second insulating film pattern is formed in a self-aligning manner so as to cover the side surface of the L-shaped first insulating film, the first insulating film covering the gate electrode and the side surface of the gate electrode is formed. Membrane and said second insulation Forming a first source / drain layer using a pattern as a mask, wherein the high-concentration layer is provided immediately below a second source / drain layer and on a side portion of the first source / drain layer. A method of manufacturing a MOS type semiconductor device having a maximum concentration value at a position deeper than the second source / drain layer and shallower than the lower part of the first source / drain layer.

According to the method of manufacturing a MOS semiconductor device of the present invention, a first source / drain layer of a second conductivity type is formed on a semiconductor substrate of a first conductivity type so as to overlap a gate electrode. In the source / drain layer structure in which the second source / drain layer is formed outside the first source / drain layer and deeper than the first source / drain layer, the first conductive type high-concentration layer is 1 at the side of the source / drain layer,
Since it is formed at a position directly below the second source / drain layer,
A low-concentration first conductivity type impurity layer for controlling a threshold voltage can be formed on a side portion of the second source / drain layer. Therefore, the high concentration layer of the first conductivity type for suppressing the short channel effect does not cause a reduction in hot electron degradation resistance, and the short channel effect is suppressed to facilitate miniaturization.

In addition, the manufacturing method of the present invention makes it possible to achieve highly reliable high density. That is, a low concentration and shallow source / drain layer is formed by using the gate electrode as a mask,
A high-concentration impurity layer of the same conductivity type as the substrate is formed using the insulating layer as a mask, and a high-concentration deep source / drain layer is formed using the gate electrode, the first insulating layer, and the second insulating layer as a mask. A high-concentration impurity layer of the same conductivity type as the substrate can be determined without causing a high electric field near the drain.

Embodiment Hereinafter, an embodiment of the present invention will be described with reference to FIG. 1 and FIG.

In FIG. 1, 1 is a low-concentration substrate (p-type), 2 is a high-concentration p-type impurity layer, 3 is a p-type impurity layer for controlling threshold voltage, 4 is a high-concentration source / drain layer, and 5 is a low-concentration source / drain layer. A source / drain layer having a shallow concentration, 6 is a gate insulating film, 7 is a gate electrode, and 8 is an aluminum wiring.

FIG. 1 is characterized by a high concentration p-type impurity layer 2.
Is formed only directly under the low concentration and shallow source / drain layer 5, and on the side of the low concentration and shallow source / drain layer,
That is, the p-type impurity layer 3 for controlling the threshold voltage is formed.

Therefore, a high electric field is not generated at the side end of the low concentration and shallow source / drain layer 5, and the resistance to hot electron degradation can be significantly improved. Further, since the concentration value of the high-concentration p-type impurity layer 2 can be increased without lowering the hot electron degradation resistance, the short channel effect can be significantly suppressed. That is, such a structure makes it possible to remarkably suppress the short channel effect while improving the resistance to hot electron degradation for the first time.

Next, with reference to FIGS. 2 (a) to 2 (d), the point of an example of the manufacturing method will be described.

First, as shown in FIG. 2A, a low-concentration substrate (p ⁻ type) having a threshold voltage controlling p-type impurity layer 3 on its surface
1, a gate insulating film 6 and a gate electrode 7 are selectively formed. Thereafter, using the gate electrode 7 as a mask, arsenic is ion-implanted at an acceleration voltage of 40 KeV and a dose of 4.0E13 / cm 2 to form the source / drain layers 5. At this time, the source / drain layer 5 can be formed at a low concentration and shallow, and the low concentration and shallow source / drain layer 5 completely overlaps the gate electrode 7.

Next, as shown in FIG. 2B, an oxide film 9a and a nitride film 10a are deposited on the entire surface of the substrate by a CVD method. Here, the oxide film thickness is set to about 50 nm, and the nitride film thickness is set to about 250 nm.

Thereafter, as shown in FIG. 2C, dry etching is performed to form a nitride film pattern 10b in a self-aligned manner so as to cover the side surface of the oxide film 9b. At this time, the oxide film 9b on the substrate is reduced to about 30 nm. Thereafter, the gate electrode 7
Using the oxide film 9a and the nitride film pattern 10b covering the side surfaces of the gate electrode 7 as a mask, arsenic is ion-implanted at an acceleration voltage of 80 KeV and a dose of 6.0E15 / cm ² to form a source / drain layer 4.
To form At this time, the source / drain layer 4 can be formed deeply at a high concentration and furthermore, since ions are implanted at a distance of 0.3 μm from the end of the gate electrode, the source / drain layer 4 is deeply doped at a high concentration.
The drain layer 4 does not cover the low concentration and shallow source / drain layer 5.

Next, as shown in FIG. 2D, the nitride film pattern 10b is formed.
Is treated with hydrofluoric acid HF for about 200 seconds and then etched away with hot phosphoric acid H ₃ PO ₄ . At this time, the oxide film 9c on the substrate becomes 10
Decrease to about nm. After this step, boron is ion-implanted at an acceleration voltage of 80 KeV and a dose of 3.2E12 / cm ² by using the gate electrode 7 and the oxide film pattern 9c covering the side surfaces of the gate electrode 7 as a mask to form a high-concentration p-type impurity layer. 2 can be formed. Further, due to the oxide film pattern 9c covering the side surface of the gate electrode 7, the high concentration p-type impurity layer 2 does not cover the side surface of the low concentration and shallow source / drain layer 5.

Thereafter, aluminum wiring 8 is formed by a normal process to
Obtain an S-type semiconductor device.

In this embodiment, after a gate electrode 7 is formed on a semiconductor substrate of a first conductivity type via a gate insulating film 6, a second source / drain of a second conductivity type is formed using the gate electrode 7 as a mask. A step of forming a layer 5, a step of depositing a first insulating film 9a over the entire surface of the semiconductor substrate, and a step of depositing a second insulating film 10a over the entire surface of the first insulating film 9a.
After performing dry etching of the second insulating film 10a to form a second insulating film pattern 10b in a self-aligned manner so as to cover the side surface of the first insulating film 9a,
And a first insulating film covering a side surface of the gate electrode and a second insulating film.
Forming the first source / drain layer 4 using the second insulating film pattern as a mask;
forming a high concentration layer 2 by introducing impurities of the first conductivity type using the gate electrode 7 and the first insulating film 9c covering the side surfaces of the gate electrode as a mask after the b is removed by etching. A method of manufacturing a MOS type semiconductor device has been described. After a gate electrode is formed on a semiconductor substrate of a first conductivity type via a gate insulating film, a second source of a second conductivity type is formed using the gate electrode as a mask. Forming a high-concentration layer by depositing an insulating film over the entire surface of the semiconductor substrate and introducing a first conductivity type impurity using the gate electrode and the insulating film covering the side surfaces of the gate electrode as a mask. A forming step, an insulating film is deposited again on the entire surface of the semiconductor substrate, and an insulating film pattern is formed in a self-aligned manner so as to cover side surfaces of the gate electrode by performing dry etching of the insulating film. Insulating film pattern covering the side surfaces of the serial gate electrodes and the gate electrode may be used a method of manufacturing a MOS type semiconductor device having a step of forming a first source / drain layer as a mask.

As is clear from the above description, according to the method for manufacturing a MOS semiconductor device of the present invention, a high-concentration impurity layer of the same conductivity type as that of a substrate can be formed directly under a low-concentration shallow source / drain layer. Thus, a high electric field is not generated by the high concentration impurity layer of the same conductivity type as the substrate on the side surfaces of the shallow source / drain layers. For this reason, the concentration value of the high-concentration impurity layer of the same conductivity type as the substrate can be sufficiently increased without lowering the hot electron degradation resistance, and the short channel effect can be significantly suppressed. An easy-to-use MOS semiconductor device can be obtained.

Further, the manufacturing method of the present invention enables highly reliable high-density recording. That is, a low-concentration and shallow source / drain layer is formed using the gate electrode as a mask, a high-concentration impurity layer having the same conductivity type as the substrate is formed using the gate electrode and the first insulating layer as a mask, and the gate electrode, the first insulating layer and the second Since the high concentration and deep source / drain layers are formed using the second insulating layer as a mask, a high concentration impurity layer having the same conductivity type as the substrate can be determined without causing a high electric field near the drain.

Therefore, the MOS type semiconductor device of the present invention has a high resistance to hot electron degradation required for VLSI, and is indispensable for a highly integrated technology in which a short channel effect is remarkably suppressed. Extremely large.

[Brief description of the drawings]

FIG. 1 is a structural sectional view of a MOS type semiconductor device according to one embodiment of the present invention, FIG. 2 is a schematic sectional view of a manufacturing process of the device,
FIG. 3 is a structural sectional view of a conventional MOS type semiconductor device, and FIG. 4 is a structural sectional view of another conventional MOS type semiconductor device and a schematic sectional view of a manufacturing process. DESCRIPTION OF SYMBOLS 1 ... Low concentration board | substrate (p ^- type), 2 ... High concentration p-type impurity layer, 3 ... P-type impurity layer for threshold voltage control, 4 ... High concentration source / drain layer, 5 ... Low Source with low concentration /
Drain layer, 6 gate insulating film, 7 gate electrode,
8 ... Aluminum wiring.

Continuation of front page (56) References JP-A-63-37663 (JP, A) JP-A-63-293979 (JP, A) JP-A-60-64472 (JP, A)

Claims (4)

(57) [Claims] A step of forming a gate electrode on a semiconductor substrate of a first conductivity type via a gate insulating film, and then forming a second source / drain layer of a second conductivity type using the gate electrode as a mask; Depositing an L-shaped first insulating film covering both sides of the gate electrode and the surface of the semiconductor substrate on both sides of the gate electrode, and depositing a second insulating film on the first insulating film; After the second insulating film is etched to form a second insulating film pattern in a self-aligned manner so as to cover the side surface of the L-shaped first insulating film, the gate electrode and the side surface of the gate electrode are formed. Forming a first source / drain layer by using the first insulating film and the second insulating film pattern to be covered as a mask; and etching and removing the second insulating film pattern. Side and Impurities of the first conductivity type are introduced using the L-shaped first insulating film covering the surface of the semiconductor substrate as a mask, and the impurity is introduced immediately below the second source / drain layers and at the side of the first source / drain layers. At a depth deeper than the second source / drain layer,
Forming a high concentration layer having a maximum concentration value at a position shallower than the lower portion of the first source / drain layer.
Of manufacturing a semiconductor device. 2. A step of forming a gate electrode on a semiconductor substrate of a first conductivity type via a gate insulating film, and then forming a second source / drain layer of a second conductivity type using the gate electrode as a mask. Depositing an L-shaped first insulating film covering both sides of the gate electrode and the surface of the semiconductor substrate on both sides of the gate electrode; Forming a high-concentration layer by introducing impurities of the first conductivity type using the first insulating film in a shape as a mask; depositing a second insulating film on the first insulating film;
After the second insulating film pattern is formed in a self-aligned manner so as to cover the side surface of the L-shaped first insulating film, the second insulating film pattern covering the side surface of the gate electrode and the gate electrode is formed. Forming a first source / drain layer using the first insulating film and the second insulating film pattern as a mask, wherein the high-concentration layer is located immediately below a second source / drain layer and the first source / drain layer. The MOS type semiconductor device having a maximum concentration value at a side portion of the source / drain layer at a position deeper than the second second source / drain layer and shallower than a lower portion of the first source / drain layer. Production method. 3. The method of manufacturing a MOS semiconductor device according to claim 1, wherein an impurity layer of the second conductivity type monotonously decreasing from the first source / drain layer end to the gate electrode end is formed. 4. The method for manufacturing a MOS semiconductor device according to claim 1, wherein the first insulating film and the second insulating film are made of different materials.