JP2806436B2 - Arithmetic circuit - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an arithmetic circuit used in a digital data processing system, and is particularly effective for real-time video processing / display and real-time image analysis in a digital video processing system. It relates to an arithmetic circuit.

(Prior art)

2. Description of the Related Art Conventionally, for example, in an image processing system that recognizes an image based on features extracted from an input image, a digital processing system is often used because of the sophistication, reproducibility, quantitativeness, and variety of processing of the processing result. . In this digital processing system, it is necessary to handle an image as a set of pixels, and an enormous amount of calculations are performed on the pixels. For example
In order to measure the particle size distribution for image data of 512 × 512 pixels and 8 bits of RGB per pixel, the processing speed is 20
Even if calculations are performed using a very large computer of the order of MIPS, a processing time of several seconds is required, which is not fast enough to perform the processing in real time. In view of this, there has been a case where the speed of video processing has been increased by using a dedicated IC for image processing. However, the application of this dedicated IC is extremely narrow and cannot be applied to a wide range of video processing.

Conventionally, in order to solve such a problem, a calculation unit holds pixel data in a plurality of units to calculate a parameter necessary for video processing, and a conversion unit performs integration and the like based on a processing result of the calculation unit. Video processing systems that perform processing have been proposed.

An arithmetic circuit that performs density averaging, filter processing, and the like in the arithmetic unit of this video processing system is configured as shown in FIG. That is, when pixel data is input along a scan line, a plurality of pixel data (here, three consecutive pixel data) are held in a holding unit 28 formed by sequentially connecting flip flops 22, 24, and 26. And output simultaneously. The output of the holding unit 28 is connected to a multiplication unit 36. The multiplying unit 36 has the same number of pixel data as the number of pixel data held by the holding unit 28, that is, three multiplying circuits 30, 32, and 34. The pixel data output from the holding unit 28 is input to the three multiplication circuits 30, 32, and 34, and the multiplication circuits 30, 32, and 34 output multiplication results each multiplied by a predetermined value. The output multiplication result is input to the integration unit 38 via the selector 37 as distribution means, and the integration unit 38 calculates parameters necessary for video processing based on the input multiplication result.

[Problems to be solved by the invention]

However, in the conventional arithmetic circuit, since multiplication is performed after a plurality of pieces of continuously input pixel data are held in units, the number of the multiplication circuits is required to be equal to the number of pixel data held in the holding unit. The multiplication circuit generally has a complicated configuration, and there is a problem that the circuit configuration of a conventional arithmetic circuit using many multiplication circuits is also complicated.

The present invention has been made in view of the above-described facts, and has as its object to obtain an arithmetic circuit having a simple circuit configuration without using many multiplication circuits having a complicated configuration.

[Means for solving the problem]

In order to achieve the above object, the invention according to claim 1 provides a single multiplication circuit for multiplying input numerical data by a predetermined value and outputting the multiplied result, and a multiplication result output from the multiplication circuit in a plurality of units. A multiplication result holding unit that holds a plurality of inputs and performs arithmetic processing on each of the input multiplication results to obtain 1
At least one integration unit for integrating the multiplication results, and distributing each of the plurality of multiplication results held in the multiplication result holding unit as it is or to a plurality of outputs and outputting to a plurality of inputs provided in the integration unit Distributing means.

According to a second aspect of the present invention, in the first aspect of the present invention, there is provided a data holding unit for holding input numerical data in a plurality of units, and a plurality of numerical data held in the data holding unit. And selecting means for outputting either of the above to the multiplying circuit.

[Action]

The multiplication circuit multiplies the input numerical data by a predetermined value and outputs the result. The multiplication result holding unit holds the multiplication results output from the multiplication circuit in a plurality of units.

As described above, the input numerical data is multiplied first and the multiplied result is retained, so that only one multiplication circuit is required, the gate efficiency is improved, and the circuit configuration of the arithmetic circuit is simplified. Becomes

According to claim (2), the data holding unit holds the input numerical data in a plurality of units, and the selecting unit outputs one of the plurality of numerical data held in the data holding unit to the multiplication circuit. For this reason, the order of the numerical data input to the multiplication circuit and the number of times the numerical data is input to the multiplication circuit can be selected according to the content of the operation, and various operations can be performed in the operation circuit.

〔Example〕

Hereinafter, an embodiment in which the present invention is applied to a video processing system will be described in detail with reference to the drawings.

In FIG. 3, the video processing system has an input unit 60 to which pixel data is input. The pixel data input to the input unit 60 is sequentially processed by an arithmetic unit 62 and a conversion unit 64.
The calculation section 62 performs calculation processing such as numerical calculation or state calculation, and the conversion section 64 performs post-processing for obtaining a final processed image or feature amount.

As shown in FIG. 4, the pixel data P _{i, j} are generally arranged sequentially along one scan line. In image processing, for example, as shown in FIG. 5, for example, 3 × 3 pixel data P _{(i-1), (j-1)} , P _{(i-1), j} , P
_{(I-1), (j + 1)} , P _{i, (j-1)} , P _{i, j} , P
_{i, (j + 1)} , P _{(i + 1), (j-1)} , P
Various processes are performed on _{(i + 1), j} , P _{(i + 1), (J + 1)} . Note that the size of this processing area is 2 ×
2, or may be set to a larger area. Further, the processing area is defined as a region having a shape other than a square, for example, a center pixel and four pixels adjacent to the upper, lower, left and right sides of the center pixel.
It may be a pixel area. Normally, neighborhood processing for holding such a 3 × 3 or other area is necessary, but in this embodiment, this neighborhood processing unit is omitted.

Next, the calculation unit 62 will be described. The pixel data is input to the calculation unit 62, where parameters necessary for video processing are calculated. For example, the average density of each pixel in the processing area is one of such parameters, and can be obtained by the calculation unit 62.

As shown in FIG. 6, the operation unit 62 includes a state operation unit 92 and a numerical operation unit 94 constituted by the operation circuit of the present invention. In the state calculation unit 92, the number of links, an index of whether or not the pixel is the object of processing, parameters T, F, D, E for obtaining the Euler number, a comparator signal indicating the processing pixel and the state in the vicinity thereof , And others are calculated. On the other hand, in the numerical operation unit 94, density averaging, first derivative, second derivative, filter processing, and other processing are performed. The processing of these arithmetic units 92 and 94 is sped up by pipeline processing.

FIG. 1 shows the configuration of the state operation unit 92 and the numerical operation unit 94.

.., 82 are connected to the inputs of a multiplexer (MUX) 78. The input unit 60 includes a memory for storing the input pixel data. Multiplexer 78
Is connected to a numerical operation unit 94.
, 82, one of the pixel data output from the input unit 60 and the memories 80,..., 82 is selected by the multiplexer 78 and input.

The numerical operation unit 94 includes a data holding unit 10 and a multiplexer.
18, a multiplying unit 72, a multiplication result holding unit 52, and a selector 74
And the integration unit 76 are sequentially connected. A control signal is input to each of the data holding unit 10, the multiplexer 18, the multiplication unit 72, the multiplication result holding unit 52, the selector 74, and the integration unit 76 from a control device (not shown). Is controlled so as to operate at a predetermined timing based on the clock used as the reference timing.

The data holding unit 10 has three flip-flops 12, 14, 16
Are sequentially connected, and the control signals are input to the flip-flops 12, 14, and 16, respectively. As shown in FIG. 4, pixel data P _{i, j} are sequentially input to the first flip-flop 12 along one scan line _, and the pixel data P _{i, j} are held for a predetermined time determined by a control signal, and the second flip-flop 14 and the multiplexer are held.
Output to 18. The second flip-flop 14 holds the pixel data input from the first flip-flop 12 for a predetermined time determined by a control signal and outputs the pixel data to the third flip-flop 16 and the multiplexer 18. The third flip-flop 16 holds the pixel data input from the second flip-flop 14 for a predetermined time determined by a control signal and outputs the pixel data to the multiplexer 18. Therefore, three consecutive pixel data along one scan line are input to the multiplexer 18 at the same time. Multiplexer
Reference numeral 18 outputs the input three pieces of pixel data to the multiplying unit 72 one by one at a predetermined timing synchronized with the control signal.

The multiplier 72 includes a single multiplier 54, a multiplexer 46, and a multiplier register 58. This multiplier register
A predetermined value (hereinafter, referred to as a multiplication value) by which the input pixel data is multiplied
(Called a multiplier). Multiplier register 58
Has the same number of output terminals as the number of stored multipliers, and each of the output terminals is connected to each of the input terminals of the multiplexer 56. A control device (not shown) is connected to the multiplexer 56, and is controlled so as to guide any one of a plurality of multipliers input from an input terminal to an output terminal. A multiplier 54 is connected to the output terminal of the multiplexer 56. The multiplication circuit 54 multiplies the input pixel data by the multiplier input from the multiplexer 56 and outputs the multiplication result to the multiplication result holding unit 52.

The multiplication result holding unit 52 has the same configuration as the data holding unit 10,
The three flip-flops 66, 68, 70 are connected in order, and the flip-flops 12, 14, 16 receive the control signal. The multiplication results output from the multiplication circuit 54 are sequentially input to the first flip-flop 66, and the multiplication results are held for a predetermined time determined by the control signal, and the second flip-flop 68 and the selector 74 are held.
Output to The second flip-flop 68 holds the result of the multiplication input from the first flip-flop 70 for a predetermined time determined by the control signal, and holds the third flip-flop 70.
And output to the selector 74. Third flip flop 70
Holds the multiplication result input from the second flip-flop 68 for a predetermined time determined by the control signal, and
Output to 74. A state operation unit 92 is connected between each of the three flip-flops 66, 68, and 70 of the multiplication result holding unit 52 and the selector 74. Therefore, the result of multiplication of three consecutive pixel data along one scan line is input to the selector 74 and the state calculation unit 92 at the same time.

In the selector 74, each of the multiplication results input to each input terminal is distributed as it is or to a plurality of outputs and guided to an output terminal. The integrating unit 76 integrates the multiplication results derived from the selector 74 while performing addition and subtraction and other operations. The operations in the integration unit 76 are performed in a hierarchical manner, and different operations are performed simultaneously in each hierarchy and are pipelined to the next stage, thereby improving the operation speed of the numerical operation unit 94 as a whole. Let me.

On the other hand, the state calculation unit 92 performs processing such as logical operation and pattern matching on the input pixel data.
The output of the integration unit 76 of the numerical operation unit 94 and the output of the state operation unit 92 are input to the multiplexer 90. An output of the multiplexer 90 is connected to an input of the multiplexer 84, and a plurality of outputs of the multiplexer 84 are respectively connected to buffers 86,.
, 88 are connected to the memories 80, ..., 82. The memories 80,..., 82 store processing result data of the numerical operation unit 94 or the state operation unit 92 with the selector 84 and the buffer 8 respectively.
6,..., 88 are stored. Also, memory 80,
.., 82 are sent to the numerical operation unit 94 and the state operation unit 92 via the multiplexer 78 as necessary, and can be processed again. The processing data stored in 80,..., 82 is input to the conversion unit 64, where final video processing is performed or a feature amount is obtained.

FIG. 7 shows the basic configuration of the conversion circuit 40 that forms a part of the conversion unit 64. The conversion circuit 40 has a high-speed memory 42. In this embodiment, a static RAM is used as the high-speed memory 42. A control device (not shown) is connected to a write enable terminal of the high-speed memory 42, and a write enable signal S for controlling reading and writing of the high-speed memory 42 is input. High-speed memory 42 data output pin
D1 is connected to one of two input terminals of the light operation unit 44. In the present embodiment, an adder is used as the light operation unit 44. The light operation unit 44 outputs an addition result of two data input from each of the two input terminals from an output terminal. The output terminal D2 of the light operation unit 44 is connected to one of the two input terminals of the selector 46. The data D4 is input to the other of the two input terminals of the selector 46. The selector 46 guides one of the data respectively input from the two input terminals to the output terminal of the selector 46. The output terminal of the selector 46 is the data input terminal of the first high-speed memory 42.
Connected to D0.

 Next, the operation of the video processing system according to the present embodiment will be described.

First, a description will be given of a calculation process for obtaining a Sobel operator in the y direction, which is one of the techniques for enhancing the edge of a figure in a digital image and sharpening the figure in the numerical calculation unit 94 to which the calculation circuit of the present invention is applied.

In the 3 × 3 convolution, the Sobel operator multiplies the density value of pixels around the central pixel by a coefficient and adds the result to the central pixel density. Sobe
The coefficient for obtaining the l operator in the y direction is the third
Shown in the figure. That is, the operation by the Sobel operator in the y direction (here, expressed as Δy according to Laplacian) is defined as follows.

Δyf _ij = P _{(i−1), (j−1)} + 2P _{i, (j−1)} +
P _{(i + 1), (j-1)} -P _{(i-1), (j + 1)} -2Pi _{, (j + 1)} -P
_{(I + 1), j + 1)} .

The pixel data stored in the memory of the input unit 60 is sequentially read out along a scan line shown in FIG. In the data holding unit 10, three consecutive
Pixel data P _{(i-1), (j-1)} , P
_{i, (j-1)} , P _{(i + 1), (j-1)} are held and output to the multiplexer 18 simultaneously. The multiplexer 18 outputs the inputted three pieces of pixel data to the multiplying circuit 54 of the multiplying unit 72 one by one at a predetermined timing. Multiplexer
At 56, the multiplier input from the multiplier register 58 is selected in synchronization with the timing at which the pixel data is input to the multiplier 54. Then, the multipliers 1, 2, and 1 are sequentially output to the multiplication circuit 56. In the multiplication circuit 54, the input pixel data P
_{(I-1), (j-1)} is 1, pixel data P
_{i, (j-1)} is 2, pixel data P
_{(I + 1) and (j-1)} are each multiplied by 1 and output to the multiplication result holding unit 52.

The multiplication result holding unit 52 holds the input multiplication result,
Three multiplication results P _{(i-1), (j-1)} , 2P
_{i, (j-1)} , P _{(i + 1), (j-1)} are selected by the selector 74.
Output simultaneously to In this calculation process, the selector 74 outputs the input data to the integration unit 76 as it is.

In the integration unit 76, P _{(i-1), (j-1)} + 2P
_{i, (j-1)} + P _{(i + 1), (j-1)} are calculated,
The operation result is stored in the memory 80 via the multiplexers 90 and 84 and the buffer 86. At this time, the pixel data P
Unlike the normal scan line direction shown in FIG. 4 _{, i and j} are rearranged and arranged in the vertical direction as shown in FIG. That is, the calculation result to be stored at the coordinates (i, j) of the memory 80 is stored at the coordinates (j, i), and as a result, the coordinates (i, j) of the center pixel are The operation result to be stored at the coordinates (i, j-1) adjacent in the direction is the coordinates (i-1, j) adjacent to the center pixel in the left direction.
And the operation result to be stored in the downwardly adjacent coordinates is the coordinate (i +
1, j).

The data holding unit 10 stores the pixel data P
_{(I-1), (j-1)} , P _{i, (j-1)} , P
Multiplication result P of _{(i + 1), (j-1)
(I-1), (j-1)} , 2P _{i, (j-1)} , P
_{When (i + 1) and (j-1)} are held in the multiplication result holding unit 52, the next pixel data P along the scan line
_{(I + 2) and (j−1)} are input, and pixel data P _{i, (j−1)} , P _{(i + 1), (j−1)} , P of three pixels
_{(I + 2) and (j-1)} are output to the multiplexer 18. The multiplexer 18 sequentially outputs these one by one to the multiplier, and the multiplier 72 outputs the multiplier 1,
The multiplication result is multiplied by 2 and 1 and integrated by the integration unit 76 via the multiplication result holding unit 52 and the selector 74. When the reading of the pixel data on one scan line and the calculation are completed, the process proceeds to the reading and calculation of the next scan line, and thereafter, similarly, the pixel data P _{(i-1), (j + 1)} , P _{i, (j + 1) )} , P
_{(I + 1) and (j + 1)} are also multiplied by multipliers _{1, 2, and 1} to obtain a sum, which is stored in the memory 80. Such processing is performed for one screen (512 × 512 pixels).

Next, the data stored in the memory 80 is read out along the scan line, and the data P sequentially input to the multiplier 72 is read.
_{(I−1), j} , P _{i, j} , and P _{(i + 1), j} are multiplied by multipliers _{1, 0, and 1} in a multiplication circuit 54, respectively, and are passed through a multiplication result holding unit 52 and a selector 74 to an integration unit 76. Is obtained, and the Sobe in the y direction in the 3 × 3 convolution is obtained.
The operation Δyf _ij by the l operator Δy is obtained.

This processing result is stored in P _{i, j} of the memory 82, and such processing is performed on all pixel data in one screen.

When the Sobel operator is determined in the x direction, the density of the pixels around the central pixel multiplied by the coefficient shown in FIG. 9 may be used as the density of the central pixel.
However, in this case, when reading out the pixel data stored in the memory of the input unit 60, two line memories holding one scan line are used, or as shown in FIG. It is necessary to scan and read out pixel data, and to input the pixel data to the numerical operation unit 94 in a continuous manner in the vertical direction.

The numerical operation unit 94 can also perform smoothing, differentiation, and other arithmetic processing in the same manner as the processing described above.

Next, calculation of the area in a binary image or a labeled image will be described as image processing that can be performed by the conversion circuit 40. The labeled image to be processed is stored in a memory or the like, and the image value of each pixel is used as an address for the high-speed memory 42.
And the high-speed memory 42 outputs the data stored at the input address (the initial value of the data stored at each address of the high-speed memory 42 is 0). The light operation unit 44 outputs data obtained by adding D3 (set to “1” here) to this data, and stores the data again at the same address of the high-speed memory 42 via the selector 16. By repeating this process until the scan of the processing target image is completed once, the number of pixels of each pixel value in the image is integrated, and the area of each label region is obtained.

Also, the conversion circuit 40 can extract various features by changing the operation contents of the light operation unit 44 to maximum value extraction, minimum value extraction, logical operation and the like.

As described above, in the numerical operation circuit 94 of the present embodiment, the multiplication process is performed by using the single multiplication circuit 54, and the multiplication result is stored in the multiplication result storage unit 52. Processing of pixel data in a fixed neighborhood unit can be realized by a single multiplication circuit 54, thereby improving gate efficiency and simplifying the configuration.

In general, the configuration of the multiplication circuit is complicated, and when designing a circuit including many multiplication circuits, the load on the designer is heavy. In the arithmetic circuit of the present invention, since only one multiplication circuit is required, the load on the designer can be reduced as compared with the case where an arithmetic circuit including many multiplication circuits is designed.

In this embodiment, the output is 1 as an integrated unit of the arithmetic circuit.
Although the system integration unit 76 is shown, an integration system 96 having two output systems as shown in FIG. 2 may be used. In this integration part 96, 2
The input terminals are shared by the two systems, and two different processes, for example, a differential process and a filter process, can be simultaneously performed on input data. Here, if the processing results of the two systems are stored in separate memories or the like,
For example, differential processing and filter processing can be performed in parallel, and the processing speed of the entire video processing system can be improved.

Further, in this embodiment, the multiplier is stored in the multiplier register 58, the multiplier is selected by the multiplexer 56, and the selected multiplier is output to the multiplier 54.However, the multiplier is stored in storage means such as a memory, and the address is designated by the control device or the like. May be selected and output to the multiplication circuit.

Further, in this embodiment, each of the data holding unit 10 and the multiplication result holding unit 52 is configured by sequentially connecting three flip-flops. However, the data holding unit 10 and the multiplication result holding unit 52 are configured by using storage means such as a memory, and are arranged along a scan line. It is also possible to simultaneously output data of three consecutive pixels at a predetermined timing.

Further, in the present embodiment, the data holding unit 10 and the multiplexer 18 are provided before the multiplying unit 72, but these may be omitted.

Further, the arithmetic circuit of the present invention is not limited to the video processing system described in the present embodiment, but is applicable to various digital data processing systems.

〔The invention's effect〕

As described above, in the present invention, a single multiplication circuit is used, and the multiplication result output from the multiplication circuit is held in a plurality of units in the multiplication result holding unit. An excellent effect that an arithmetic circuit having a simple circuit configuration can be obtained without any problem can be obtained.

[Brief description of the drawings]

FIG. 1 is a circuit diagram showing an arithmetic circuit according to the present invention and its peripherals, FIG. 2 is a circuit diagram showing another embodiment of the present invention, and FIG. 3 is a video processing system to which the arithmetic circuit of the present invention can be applied. FIG. 4 is a schematic block diagram showing a basic configuration, FIG. 4 is an explanatory diagram for explaining an array of pixel data, FIG. 5 is a conceptual diagram for explaining a 3 × 3 processing area, and FIG. FIG. 7, FIG. 7 is a circuit diagram showing a basic configuration of the conversion circuit, FIG. 8 is a conceptual diagram showing coefficients for obtaining a Sobel operator in the y direction, and FIG. 9 is a diagram showing coefficients for obtaining a Sobel operator in the x direction. FIG. 10 is an explanatory diagram for explaining vertical scanning, and FIG. 11 is a circuit diagram showing a conventional arithmetic circuit. 10 Data holding unit, 52 Multiplication result holding unit, 54 Multiplication circuit, 60 Input unit, 62 Operation unit, 64 Conversion unit, 72 Multiplication unit, 74 Selector, 76: Integration unit, 94: Numerical operation unit

Claims (2)

(57) [Claims] 1. A single multiplication circuit for multiplying one input numerical data by one predetermined value and outputting the multiplied result, and holding a plurality of multiplication results output from the multiplication circuit in time series A multiplication result holding unit, at least one integration unit having a plurality of inputs, performing an operation process on each of the input multiplication results and integrating them into one, and a plurality of multiplication results held by the multiplication result holding unit And a distribution unit for distributing each of them as it is or to a plurality of outputs, and outputting to a plurality of inputs provided in the integration unit. 2. A data holding unit for holding inputted numerical data in a plurality of units, and a selecting means for outputting any one of the plurality of numerical data held by the data holding unit to the multiplying circuit. The arithmetic circuit according to claim 1, wherein: