JP2806744B2 - Semiconductor integrated circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit having a complementary insulated gate field effect transistor (CMOSFET) structure, and more particularly to a semiconductor integrated circuit having a data bus connected to a tri-state buffer.

[0002]

2. Description of the Related Art A conventional semiconductor integrated circuit of this type is described, for example, in Japanese Patent Application Laid-Open No. 63-131614.
Referring to FIG. 5, which shows a circuit diagram of a semiconductor integrated circuit in which a latch circuit is connected to a data bus described in the publication, output terminals of tristate buffers T1 and T2, input terminals of gate circuits G1 and G2, and a latch circuit are connected to the data bus. And the latch circuit LA is connected to the inverter circuit I.
1 and I2 are connected to each other at an input terminal and an output terminal. One end of the connection point is connected to the data bus and the other end is connected to an initialization circuit Q1.
Is connected.

Referring to FIG. 6 showing details of the initialization circuit Q1, a circuit having this configuration includes a transfer gate TG.
Is turned on by the timing signal T, the data bus is arbitrarily set to the H level or the L level in response to the high (H) level or the low (L) level of the data D of the initialization circuit Q1. In the circuit having this configuration, during normal operation, the current capability of the tristate buffer circuits T1 and T2 connected to the data bus is larger than the current capability of the first inverter circuit I1. Therefore,
Tri-state buffers T1 and T in enabled state
When any of the data No. 2 is output on the data bus as expected, correct data can be supplied to the gate circuit G1 whose input terminal is connected to the data bus. When all the tri-state buffers connected to the data bus are in the non-enabled state, the data on the data bus in the enabled state is latched in the latch circuit LA. Not be. Further, since the potential of the data bus becomes unstable at the rise of the power supply voltage, when the timing signal T of the initialization circuit Q1 is set to H level and the data D is set to H level, the output L level of the initialization circuit Q1 is changed to the latch circuit LA. Inverter circuit I1 attains H level, and inverter circuit I2 inverts it again to L level. This state is latched. Therefore, the data bus is stabilized at H level. Stabilize.

Another example of this type of semiconductor integrated circuit is a circuit described in Japanese Patent Application Laid-Open No. Sho 63-72218. Referring to FIG. 7 which shows a circuit diagram of a semiconductor integrated circuit in which a latch circuit is connected to a data bus described in the same publication, the circuit shown in FIG. 7 is obtained by removing an initialization circuit from the configuration shown in FIG. The configuration is the same as that of FIG. 4 except that the inverter circuit I1 is replaced by a two-input NOR circuit, and the description of the configuration is omitted. One input terminal of the two-input NOR circuit is supplied with a reset signal RE.

When the level of the data bus is not determined in the initial state, the output of the two-input NOR circuit is set to the L level by setting the reset signal RE to the H level, and the level of the data bus is set.

[0006]

The above-described conventional semiconductor integrated circuit has an initialization circuit or an N circuit for stabilizing the potential of the data bus when the power supply voltage rises.
Since the OR circuit is used, there is a disadvantage that the circuit scale is increased, and the area of the chip layout is increased as the number of data buses is increased.

An object of the present invention is to eliminate the above-mentioned drawbacks and simplify the circuit configuration, thereby realizing the potential stabilization of the data bus at the rise of the power supply potential and the prevention of floating.

The semiconductor integrated circuit according to the present invention is characterized in that the output terminal of the first tristate buffer group and the input terminal of the gate circuit group are connected to a data bus group, respectively, and a capacitance is provided between the data bus group and the ground potential. An element group is connected, and an output terminal of a test circuit for inspecting a disconnection of a connection line between the capacitance element group and the data bus group is connected to these connection points, respectively, and the test circuit includes first and second test circuits. , And an output terminal of the first inverter circuit, to which data is supplied from the outside, is connected to the second tristate buffer via a second inverter circuit. The output terminals of the first inverter circuit are also connected to the input terminals of a third group of tri-state buffers, respectively. A test signal is commonly supplied from the outside to the enable terminals of the second and third tristate buffer groups, and the output terminals of these tristate buffer groups are connected to the corresponding data bus groups. The current drive capability of the second and third tri-state buffer groups is to be smaller than the current drive capability of the first tri-state buffer group.

[0009]

[0010]

Next, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a circuit diagram of a first embodiment of the present invention. Referring to FIG. 1, a data bus to which the output terminals of the plurality of tristate buffer circuits T1 and T2 are connected to the respective input terminals of the plurality of gate circuits G1 and G2, and the output terminal of the first inverter circuit I1 Is the second
, And a connection point between the output terminal of the second inverter circuit I2 and the input terminal of the first inverter circuit I1 and the ground potential G.
The capacitance element C1 is provided between the capacitor ND and ND. Although only one set of these circuits is shown here for ease of explanation, it is necessary for each data bus. Also, the first
The parasitic capacitance between the inverter circuit I1 and the power supply potential is represented by C
The parasitic capacitance between _I1-VDD , the first inverter circuit I1 and the ground potential is C _I1-GND , the capacitance of the capacitive element C1 is C _C1 ,
Inverter circuit I1 changes the input signal to H level or L level.
The input voltage of a threshold value that can be changed to an L level or an H level by determining that the signal is a bell signal is V _IHL ,
And the power supply voltage is VDD, the capacitance C _C1 that satisfies the condition represented by VDD · ((C _I1-VDD ) / (C _I1-VDD + C _I1-GND + C _C1 )) <V _IHL (1) And a capacitive element C1 having

Referring again to FIG. 1, immediately after the power is turned on, the tri-state buffer T1 connected to the data bus is connected.
If both T2 and T2 are in the non-enabled state, the relationship between the parasitic capacitances C _I1-VDD and C _{I1-GND of} the first inverter circuit I1 and the capacitance C _C1 of the capacitance element C1 is (1).
In the state shown in the equation, the input of the first inverter circuit I1 is performed.
The potential of the power terminal is in a state of low L level than V _IHL, the output of the first inverter circuit I1 becomes H level, the potential of the data bus is stable. Even when the capacitance element C1 is connected to the power supply potential, if the following expression is satisfied, the output of the first inverter circuit I1 outputs an L level, and it is clear that the data bus potential is stabilized at the L level also in this case. It is.

VDD · ((C _C1 + C _I1-VDD ) / (C _C1 + C _I1-VDD + C _I1-GND ))> V _IHL (2) In the normal operation, the first inverter is used. Circuit I
1 is designed to be sufficiently smaller than the capabilities of the tri-state buffers T1 and T2 connected to the data bus, so that the tri-state buffers T1 and T2
When 2 is enabled, these outputs are output on the data bus. On the other hand, when the tristate L buffers T1 and T2 are in the non-enabled state, the data on the data bus is held by the latch circuit LA including the first inverter circuit I1 and the second inverter circuit I2, and the data bus floats. The state can be avoided. At this time, the capacitance C1
Has no effect.

FIG. 2 shows a circuit diagram of a second embodiment of the present invention.
, A capacitive element C2 is connected between a ground bus and a data bus to which a plurality of tristate buffers T1 and T2 and gate circuits G1 and G2 are connected, and the capacitive element C2 is disconnected from a connection line A to the data bus. A test circuit TE is connected to the data bus to check whether or not the test has been performed. In addition, the parasitic capacitance between the data bus and the power supply potential is CB _-VDD , And a capacitance C _C2 of a capacitance element C2 that satisfies the following equation where the parasitic capacitance between the data bus and the ground potential is CB _-GND .

[0015] _{VDD · ((C B-VDD} ) / (C B-VDD + C B-GND + C C2) = VDD / 10 ...... ...... (3) The circuit, parasitic capacitance of the data bus immediately after the power is turned on C
_Since the relationship between _B-VDD and CB _-GND and the capacitance C _C2 of the capacitance element C ₂ is in the state of the above equation (3), the potential of the data bus is stabilized at the L level.

In a normal operation, for example, if it is assumed that the tristate buffer T1 connected to the data bus is enabled and outputs an H level on the data bus,
The above-described capacitance element C2 is charged with an H-level charge. Next, when the tri-state buffer T1 enters the non-enable state, the potential of the data bus is held at the H level by the electric charge of the capacitor C2, so that the floating state of the data bus can be avoided. Therefore, the latch circuit LA including the first and second inverter circuits I1 and I2 in the first embodiment can be replaced with the capacitance element C2. Further, even in the layout design of the chip, since the data bus passes through many circuits, a dead space is likely to be generated on the chip. However, the capacitor C2 only needs to be connected to an arbitrary part of the data bus. Therefore, the above-mentioned dead space can be used effectively, and chip layout can be performed without increasing the chip area.

Here, the test circuit TE will be described.
Referring to FIG. 3 showing details of test circuit TE, test circuit TE transmits data D to tri-state buffers T3A and T3B via inverter circuits I3 and I4.
The signals are supplied to the tristate buffers T3B and T3D only through the inverter circuit I3, respectively, and the enable signal of the tristate buffers T3A, T3B, T3C, T3C, and T3D is supplied with the timing signal T. Tri-state buffers T3A, T3B, T
The output terminals of 3C, T3C, and T3D are connected to data bus B.
A, BB, BC, and BD, respectively. Capacitors C2A, C2B, C2C, and C2D are connected between the data buses BA, BB, BC, and BD and the ground potential, respectively. Output terminals of the state buffers T1 and T2 are connected to each other, and tri-state buffers T3A, T3B, T3C, T3C,
And T3D are designed to have smaller current driving capabilities than tristate buffers T1 and T2.

Referring to FIG. 4 showing a timing chart for explaining the operation at the time of the test operation, in the normal operation,
After the power is turned on (FIG. 4A), the timing signal T
Is set to the L level, the tristate buffers T3A, T3B, T3C, T3C, and T3D of the test circuit TE enter a high impedance state (FIG. 4).
(E) There is no effect on the data bus. Therefore, data is supplied from tri-state buffers T1 and T2 to data bus BA and normal operation is performed (FIG. 4).
(E)-(f)). On the other hand, the period indicated by the dotted line is the test period, and the data D is at the H level (FIG. 4D).
When the timing signal is changed from L level to H level (FIG. 4B), the tri-state buffers T3A, T3
The outputs of B, T3C, T3C, and T3D change from the high impedance state to the H level (FIG. 4).
(E)) As described above, since these current driving capabilities are small, the capacitance elements C2A, C2B, C2C, and C2D
Since each has a predetermined capacity, it takes time to charge and discharge (FIG. 4 (g)). By measuring the charge / discharge time, the capacitance elements C2A, C2B, C2C, and C2
A connection check of D is performed. If the wiring between these capacitive elements and the data bus, for example, the wiring A between the capacitive elements C2A is broken, only the parasitic capacitance exists on the data bus BA, so that the charge / discharge time by the tri-state buffer T3A becomes short. So, the state of this data bus
Pre-failure in the manufacturing process by measuring from outside
Check to remove defective products .

[0019]

As described above, in the semiconductor integrated circuit of the present invention, when a power supply is turned on by providing a capacitive element between two inverter circuits constituting a latch circuit for holding a logical level of a data bus. , The potential of the data bus becomes stable, and the configuration is simpler than that of the conventional initialization circuit. A similar effect can be obtained by connecting a capacitance element to the data bus without using a latch circuit. Further, this capacitance element and a test circuit having a tristate buffer having a small current driving capability are connected together. Can check the disconnection of this capacitive element
Therefore, it contributes to improvement of reliability .

[Brief description of the drawings]

FIG. 1 is a circuit diagram showing a first embodiment of the present invention.

FIG. 2 is a circuit diagram showing a second embodiment of the present invention.

FIG. 3 is a circuit diagram illustrating details of a test circuit according to a second embodiment.

FIG. 4 is a time chart for explaining the operation of the test circuit in the second embodiment.

FIG. 5 is a circuit diagram showing an example of a conventional semiconductor integrated circuit.

FIG. 6 is a circuit diagram showing details of an initialization circuit in FIG. 5;

FIG. 7 is a circuit diagram showing another example of a conventional semiconductor integrated circuit.

[Explanation of symbols]

C1, C2, C2A, C2B, C2C, C2D Capacitance element D data G1, G2 Gate circuit I1, I2, I3, I4 Inverter circuit T Timing signal T1, T2, T3A, T3B, T3C, T3D Tri-state buffer TE test circuit

 ──────────────────────────────────────────────────続 き Continued on the front page (72) Inventor Nobuyuki Yuki No. 403-53, Kosugi-cho, Nakahara-ku, Kawasaki-shi, Kanagawa Prefecture Within NEC Ic Microcomputer System Co., Ltd. (56) References JP-A-6-124591 (JP, A) JP-A-63-131614 (JP, A) JP-A-5-110392 (JP, A)

Claims (1)

(57) [Claims] An output terminal of a first tristate buffer group and an input terminal of a gate circuit group are connected to a data bus group, and a capacitor element group is connected between the data bus group and a ground potential. Output terminals of a test circuit for inspecting a disconnection of a connection line between the capacitive element group and the data bus group are respectively connected to the connection points, and the test circuit is connected to first and second inverter circuits and second and second inverter circuits. And an output terminal of the first inverter circuit to which data is supplied from the outside is connected to an input terminal of the second tristate buffer group via a second inverter circuit. Further, an output terminal of the first inverter circuit is also connected to an input terminal of a third tri-state buffer group, respectively, and the second and third transistors are connected to each other. A test signal is commonly supplied from the outside to the enable terminals of the group of state buffers, and the output terminals of the group of tristate buffers are connected to the corresponding data bus groups , respectively. 2. The semiconductor integrated circuit according to claim 1, wherein the current driving capability of the state buffer group is smaller than the current driving capability of the first tri-state buffer group.