JP2808669B2 - Semiconductor integrated circuit - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention is used for a gate array type semiconductor integrated circuit, and particularly relates to a semiconductor integrated circuit having an improved basic cell structure.

〔Overview〕

According to the present invention, in a semiconductor integrated circuit of a gate array system, a basic cell is configured by a combination of a plurality of field-effect transistors having gate widths of different lengths, so that a chip can be rationally configured according to the circuit requirements. It is like that.

[Conventional technology]

Conventionally, a basic cell of a gate array using complementary MOS transistors (CMOS) has two or three long gate width polysilicon electrodes 3 having the same gate width as shown in FIGS. 5 (a) and 5 (b). And a P-channel MOS transistor region 1 and an N-channel MOS transistor region 2.

[Problems to be solved by the invention]

In the conventional CMOS gate array described above, in the case of FIG. 5 (a), one circuit of a two-input NAND gate or NOR gate is provided.
Alternatively, two inverter circuits can be realized by one basic cell. However, as shown in FIG.
When a storage circuit for one bit of M is configured, two cells are required.

By the way, the switching N-channel transistor 7 shown in FIG. 2 (b) is used as a switch gate for a storage loop when reading or writing stored data, and has the same driving power as a normal logic gate. Is not required. The same applies to the two transfer gates 8 used in the latch circuit shown in FIG. 3 (b).

In other words, the MOS transistors of the conventional gate array are all designed with the same gate width, so when configuring a large number of SRAMs and latches, the number of cells and chip area will be occupied more than necessary, and the use of basic cells There is a disadvantage that the efficiency is reduced.

The object of the present invention is to eliminate the disadvantages mentioned above,
An object of the present invention is to provide a gate array type semiconductor integrated circuit capable of rationally configuring a chip according to circuit requirements without occupying more cells or chip area than necessary.

[Means for solving the problem]

The present invention provides a first P-channel MOS transistor region having a first width, and a half of the first width connected to both ends of one side of the first P-channel MOS transistor region.
Second and third P-channel MOs having a second width as follows:
An S transistor region; a first N-channel MOS transistor region having the first width;
Second and third N connected to both ends of one side of the OS transistor region and having a second width equal to or less than 1/2 of the first width.
A channel MOS transistor region, first and second gate electrodes having the first width and provided so as to divide the first P-channel MOS transistor region into three in the gate length direction, and the second P-channel MOS transistor region. Third and fourth gate electrodes provided to divide the MOS transistor region into three in the gate length direction and having the second width;
P-channel MOS transistor region in the gate length direction
Fifth and sixth gate electrodes provided so as to divide and have the second width, and the first width provided so as to divide the first N-channel MOS transistor region into three in the gate length direction. Seventh and eighth gate electrodes having ninth and tenth gate electrodes provided so as to divide the second N-channel MOS transistor region into three in the gate length direction and having the second width; A plurality of third N-channel MOS transistor regions are arranged in an array with a cell including the eleventh and twelfth gate electrodes having the second width provided so as to divide the third N-channel MOS transistor region into three in the gate length direction. It is characterized by the following.

Note that the third gate electrode and the fifth gate electrode are commonly connected, and the ninth gate electrode and the eleventh gate electrode are commonly connected.

[Action]

The present invention provides, for example, a basic cell of a CMOS gate array in which a P-channel transistor region and an N-channel transistor region having a long gate width and both ends of one side of the P-channel transistor region and the N-channel transistor region are extended. A basic cell is configured with a configuration including a P-channel transistor region and an N-channel transistor region having a short gate width whose gate width is 1/2 or less.

As a result, a circuit is configured using the transistor having a short gate width in a place where performance is not required, such as a switching transistor of a memory. In addition, a transistor having a short gate width is used in combination with a transistor having a high gate width, similarly to a transistor having a long gate width.

By performing predetermined wiring on these basic cells, SRAM cells, latch circuits, two transfer gate circuits, and three-input NAND circuits can be freely formed, and a chip configuration can be rationally made according to circuit requirements. It becomes possible.

〔Example〕

 Hereinafter, the present invention will be described with reference to the drawings.

FIG. 1 is a layout showing a first embodiment of the present invention.
2 shows a basic cell of an OS gate array.

The basic cell of the first embodiment has a long gate width polysilicon gate electrode 3 in a P-channel MOS transistor region 1,
The short gate width polysilicon gate electrodes 4 and 5 form two transistors having a long gate width and four transistors having a short gate width. The same applies to the N-channel MOS transistor region 2. A feature of the present invention resides in that a MOS transistor having short gate width polysilicon electrodes 4 and 5 is provided in FIG.

FIG. 2 (a) is a schematic layout diagram showing a second embodiment of the present invention, and FIG. 2 (b) is a circuit diagram thereof.
The storage part of a bit is shown.

The second embodiment is applied to the bit storage portion of the static RAM of the CMOS basic cell of FIG. 2B of the first embodiment shown in FIG. 1 as follows.

First, the two inverters 6 in FIG. 2A are configured by using two P-channel transistors having the long gate width polysilicon electrode 3 in FIG. 1 and two N-channel transistors. . Further, the N-channel transistors 7 for the two switches have a short gate width of N by setting the short gate width polysilicon gate electrode 5 in the N-channel MOS transistor region 2 of FIG. 1 to the ground (GND) potential. A channel transistor is formed.

The actual wiring connection uses a two-layer wiring of the first layer wiring 9 and the second layer wiring 10, and the first wiring 9 and the underlying contact are used.
This is performed as shown in FIG. 2A via the first layer wiring 9 and the through hole 12 between the first layer wiring 9 and the second layer wiring 10.

In FIG. 2A, the short gate width transistor is not affected by the logic level of the long gate width transistor because the short gate width polysilicon gate electrode 5 is set to the ground potential (in the case of an N channel). .

FIG. 3A is a schematic layout diagram showing a third embodiment of the present invention, and FIG. 3B is a circuit diagram showing the case of a latch circuit.

In the third embodiment, the CMOS basic cell shown in FIG.
This is applied to the latch circuit of FIG.

The third embodiment uses two P-channel and N-channel transistors having short gate width polysilicon electrodes 4 and 5 in the same manner as the second embodiment shown in FIG. The two transfer gates 8 shown in FIG. 3A are configured. In this case, the short gate width polysilicon electrode 5 of the P channel MOS transistor region 1 is connected to VDD.
It is necessary to keep the potential.

FIG. 4 (a) is a schematic layout diagram showing a fourth embodiment of the present invention, and FIG. 4 (b) is a circuit diagram of the fourth embodiment.
1 shows a NAND circuit.

In the fourth embodiment, the CMOS basic cell shown in FIG.
This is applied to the three-input NAND circuit of FIG.

In the fourth embodiment, it is shown that the transistor having the short gate width as shown in the first, second and third embodiments is not used only as a switch gate of a memory circuit or a latch circuit. . In other words, a combination of transistors having a short gate width makes it possible to realize a driving force equivalent to one transistor having a long gate width.
This shows that the configuration of a normal logic gate can be performed with one basic cell without waste.

In the above description, the gate width is set to the long and short two lengths, but the gate width may be set to three or more as necessary.

Further, although a MOS transistor has been described as a field effect transistor, the present invention can be similarly applied to a compound semiconductor field effect transistor.

〔The invention's effect〕

As described above, according to the present invention, for example, in a basic cell structure of a CMOS gate array, by forming transistors having a plurality of gate widths in transistor regions of the same conductivity type, the MOS transistors having the plurality of gate widths are long. The gate width is suitable for the configuration of the logic gate,
A short gate width can be used for a storage circuit or a switch gate of a latch. Further, the same driving force as that of a transistor having a long gate width can be obtained by a combination of transistors having a short gate width, so that all transistors having a short gate width can be used for a circuit configuration.

The present invention provides a 1-bit storage cell of an SRAM and a switch for reading and writing data stored in the storage cell by providing a predetermined wiring to a basic cell including the transistor described in the embodiment. Two transfer gate circuits of a transistor circuit and a latch circuit,
Various circuits such as a three-input NAND circuit can be freely formed by a gate array method.

As described above, according to the present invention, a combination of long, short, and both gate width transistors can be designed while effectively allocating basic cells to all circuits, and the effect is great.

[Brief description of the drawings]

FIG. 1 is a layout diagram showing a first embodiment of the present invention. FIG. 2A is a schematic layout diagram showing a second embodiment of the present invention. FIG. 2 (b) is a circuit diagram thereof. FIG. 3A is a schematic layout diagram showing a third embodiment of the present invention. FIG. 3 (b) is a circuit diagram thereof. FIG. 4 (a) is a schematic layout diagram showing a fourth embodiment of the present invention. FIG. 4 (b) is a circuit diagram thereof. FIGS. 5A and 5B are layout diagrams showing a conventional example. 1 ... P-channel MOS transistor region, 2 ... N-channel MOS transistor region, 3 ... Long gate width polysilicon gate electrode, 4, 5 ... Short gate width polysilicon gate electrode, 6 ... Inverter, 7 ... N-channel transistor, 8 transfer gate, 9 first-layer wiring, 10 second-layer wiring, 11 contact, 12 through-hole.

Claims (2)

(57) [Claims] 1. A first P-channel MOS having a first width.
A transistor region; and second and third P-channel MOS transistor regions connected to both ends of one side of the first P-channel MOS transistor region and having a second width equal to or less than 1/2 of the first width. A first N-channel MOS transistor region having the first width; and a second width which is connected to both ends of one side of the first N-channel MOS transistor region and is equal to or less than 1/2 of the first width. Second and third N-channel MOS transistor regions having: a first and second gate having the first width and provided so as to divide the first P-channel MOS transistor region into three in the gate length direction. An electrode; third and fourth gate electrodes provided so as to divide the second P-channel MOS transistor region into three in the gate length direction and having the second width; and the third P-channel MOS transistor. Fifth and sixth gate electrodes having the second width provided so as to divide the region into three in the gate length direction, and provided so as to divide the first N-channel MOS transistor region into three in the gate length direction. Seventh and eighth gate electrodes having the first width, and ninth and eighth gate electrodes provided so as to divide the second N-channel MOS transistor region into three in the gate length direction and having the second width. A basic cell is a cell comprising: a tenth gate electrode; and eleventh and twelfth gate electrodes provided so as to divide the third N-channel MOS transistor region into three in the gate length direction and having the second width. A semiconductor integrated circuit, wherein a plurality of semiconductor integrated circuits are arranged in an array. 2. The semiconductor according to claim 1, wherein said third electrode and said fifth electrode are connected in common, and said ninth electrode and said eleventh electrode are connected in common. Integrated circuit.