JP2809404B2 - Error pulse addition circuit - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an error pulse adding circuit that adds a periodic error pulse to an input signal having a periodic signal sequence component having a specified period and a general signal component. More particularly, the present invention relates to an error pulse adding circuit in which a periodic error pulse is added equally to a periodic signal sequence component and a general signal component.

2. Description of the Related Art For example, when data is transmitted using a digital communication network connecting computer systems, data is divided into predetermined lengths as shown in FIG. 2 is arranged. Then, the frame signal 2 is detected on the receiving side, and the data 1 is extracted. Therefore, the frame signal 2 has a predetermined period.

In addition, as a test device for confirming that a signal processing device that inputs and outputs the data signal a having such a configuration operates properly, it is necessary to output a measurement signal b having substantially the same properties as the data signal a. There is. This measurement signal b is
As shown in the figure, the frame signal 3 is composed of an A-bit frame signal 3 having the same frequency component as the data signal a, and a B-bit pseudo-random pattern data 4 corresponding to the data 1.

Further, among the signal processing devices, there is an error detection device that detects an error bit included in the data signal a using a method such as a parity check. In order to confirm that the error detection device correctly detects the error bit included in the data signal a correctly, it is necessary to intentionally apply an error measurement signal including the error bit to the error detection device. .

This error measurement signal is configured to add an error pulse at a constant period to the above-described measurement signal b shown in FIG.

FIG. 5 is a block diagram showing an error pulse adding circuit for adding an error pulse to the aforementioned measurement signal b. In this circuit, the measurement signal b shown in FIG.
DS-3 signal is used.

That is, the measurement signal (DS-
3) b is input to one input terminal of the exclusive OR circuit 6. A clock signal c for controlling the transmission timing of each bit data of the measurement signal b input from the input terminal 7 is output from a frequency divider 8 having a frequency division ratio of (1 / N) to (1 / N).
N) and is input to the other input terminal of the exclusive OR circuit 6 as an error pulse d. Then, the output signal of the exclusive OR circuit 6 is output from the output terminal 9 as the error measurement signal e.

In such an error pulse adding circuit, an error pulse d having a data value of [1] is input from the frequency divider 8 to the N bits of the measurement signal b once per cycle to the exclusive OR circuit 6. In the state of [0] in which the error pulse d is not output from the frequency divider 8, the exclusive OR circuit 6 converts the measurement signal b input from one side into the error measurement signal e as it is.
Output as When the error pulse d of [1] is applied from the frequency divider 8, the bit data of the measurement signal b at that time is inverted. That is, the output terminal 9 outputs an error measurement signal e to which an error bit (pulse) obtained by inverting the data value of each bit data of the measurement signal b every N bits is added.

Thus, an error pulse d every N bits in the measurement signal b
Is added.

[Problems to be Solved by the Invention] However, the error bit adding circuit shown in FIG. 5 still has the following problems to be solved. That is, the error pulse adding circuit shown in FIG. 5 can accurately add the error pulse d to the measurement signal b every N bits. Therefore, the dividing ratio of the divider 8 (1 / N)
Is changed, it is possible to arbitrarily set an error bit generation period (occurrence rate).

However, in order to accurately confirm the operation of the error detection device, it is necessary to generate an error bit at a fixed period in the entire measurement signal b, and the pseudo random pattern data 4
Also, error bits need to be generated equally in each frame signal 3. That is, the probability that an error bit occurs in the pseudo random pattern data 4 and the frame signal 3
Must match the probability that an error bit will occur.
However, since the frame signal 3 has a specified period of (A + B) bits, when an error pulse d is applied with a period of N bits to the entire measurement signal b, the probability that an error bit occurs in the frame signal 3 That is, the generation period of the error bit is determined by the correlation between the period (A + B) of the frame signal 3 and the period (N) of the error pulse d. More specifically, if the bit phases of the frame signal 3 and the error pulse d match at one time, error bits are sequentially generated in a cycle indicated by the greatest common divisor of both. As a result, there arises a problem that the error bit occurrence rate of the pseudo random pattern data 4 and the error bit occurrence rate of the frame signal 3 do not match.

In order to solve such inconvenience, it is sufficient to prevent the greatest common divisor from occurring between the period of the frame signal 3 and the period of the error pulse d.
Since the period (A + B) is defined to be a constant value by a data communication standard or the like, it is necessary to adjust the period (N) of the error pulse d so that the greatest common divisor does not occur. However, when the cycle N of the error pulse d is adjusted in this manner, the selection range of the cycle N of the error pulse d is greatly limited, and a problem arises in that an arbitrary error bit occurrence rate cannot be set for the error measurement signal e. .

FIG. 6 is a diagram showing a probability (period) that an error bit occurs in the frame signal 3 when the period N of the error pulse d is set to 100 using the DS-3 signal described above as the measurement signal b.

As is well known, the DS-3 signal has a bit rate of 44.736 Mb / s and is a signal including a control signal of 1 bit for every 85 bits. In this example, the frame signal 3 is the control signal. Are assigned every other bit. That is, a frame signal 3 of 1 bit (A = 1) exists every 170 bits (A + B).

Therefore, an error pulse d is added to the measurement signal b every N = 100 bits. Then, the cycle of the frame signal 3 (A + B = 170) and the cycle of the error pulse d (N = 100)
Has the greatest common divisor of 10. As a result, as shown in FIG. 6, the 10th frame signal 3 and the 17th error pulse d are synchronized from the time when the frame signal 3 of the measurement signal b coincides with the error pulse d. The occurrence rate (period) of error bits in the signal 3 is 10% (1700), and the pseudo-random pattern data 4 having no periodic component
Error bit occurrence rate in (1/100 × 16/17 × 100 ≒ 1)
%).

FIG. 7 is a diagram showing a case where the generation timing (generation phase) of the error pulse d is shifted by, for example, 5 bits without changing the period N (= 100). In this case, the error pulse d is always out of phase by 5 bits as compared with the error pulse in FIG. 6, so that it does not synchronize with the frame signal 3 of the measurement signal b. As a result, in FIG. 7, no error bit occurs in the frame signal 3, so that the occurrence rate is 0%.

Although not shown, if the generation timing (generation phase) of the error pulse d is shifted up to 10 bits, an error pulse synchronized with the frame signal 3 is generated. That is, the error pulse d having the phase shift of 1 to 9 bits is the frame signal 3
Never sync with.

As described above, it is difficult to make the occurrence rate of the error bits included in the frame signal 3 always coincide with the occurrence rate of the error bits included in the pseudo random pattern data 4.

If the period N of the error pulse d is set to, for example, N = 99 at which the greatest common divisor does not occur, it is possible to make the occurrence rates of both error bits coincide with each other. Can not do it.

The present invention has been made in view of such circumstances, and by sequentially shifting the bit timing added to the input signal of each error pulse output from the error pulse generation circuit, a periodic signal sequence component and a general signal component It is another object of the present invention to provide an error pulse adding circuit which can apply an error pulse equally and can arbitrarily change an error bit occurrence rate.

Means for Solving the Problems In order to solve the above problems, the present invention provides a method for generating a periodic error pulse in an input signal including a periodic signal sequence component having a specified period and a general signal component having no periodic component. An error pulse adding circuit for adding and outputting an error pulse, an error pulse generating circuit for outputting an error pulse every predetermined period, an error pulse output from the error pulse generating circuit being input, and an output timing of the error pulse and the input signal. A shift register having a predetermined digit for shifting the input error pulse in synchronization with a clock signal for controlling the clock signal, and outputting a signal of the shift register every time a predetermined number of error pulses are output from the error pulse generation circuit. A signal switching circuit for sequentially switching digits, and an error pulse output from the shift register via the signal switching circuit is added to an input signal. Exclusive and a logical OR circuit, in which periodic error pulses equally to the periodic signal component and the general signal component is to be added.

[Operation] In the error pulse adding circuit having such a configuration, an error pulse is output from the error pulse generating circuit at predetermined intervals and input to a shift register having a predetermined digit. This shift register sequentially shifts the input error pulse in accordance with the clock signal. The signal switching circuit sequentially switches the signal output digits of the shift register each time an error pulse is output from the error pulse generation circuit.

Therefore, the delay time from the output of one error pulse from the error pulse generation circuit to the output digit of the shift register is longer by one clock than the delay time of the error pulse output immediately before. That is, error pulses are sequentially output from the error pulse generator at predetermined intervals, but when they are input to the exclusive OR circuit, their phases are sequentially shifted by one bit (clock). Therefore, this error pulse is prevented from being unnecessarily synchronized with the periodic signal sequence component of the input signal,
The rate of occurrence of error bits included in the periodic signal sequence component and the rate of occurrence of error bits included in the general signal component approximate.

Embodiment An embodiment of the present invention will be described below with reference to the drawings.

FIG. 1 is a block diagram showing an error pulse adding circuit according to an embodiment. The same parts as those in the circuit of FIG. 5 are denoted by the same reference numerals.

The measurement signal b as an input signal input from the input terminal 5 is input to one input terminal of the exclusive OR circuit 6. An error pulse f output from the output terminal I of the signal switching circuit 21 is input to the other input terminal of the exclusive OR circuit 6. Therefore, the exclusive OR circuit 6 outputs an error measurement signal h including an error bit of a predetermined occurrence rate, and sends it out of the output terminal 9.

Further, a clock signal c for controlling the output timing of each bit data of the measurement signal b is input from the input terminal 7. This clock signal c is input to a frequency divider 8 as an error pulse generating circuit, and is divided by 1 / N to obtain an error pulse d.
Is output as The error pulse d having the period N output from the frequency divider 8 is applied to the input terminal of the shift register 22 and is also input to the clock terminal CK of the counter 23. In the frequency divider 8 of the embodiment, the frequency division ratio (1 /
N) is set to 1/100. That is, this frequency divider 8
Has a period N of 100 bits.

The shift register 22 is composed of 10-digit registers P0 to P9 as shown in the figure, and a clock signal CK input from an input terminal 7 is input to a clock terminal CK. Therefore, every time the clock pulse of the clock signal c is input to the clock terminal CK, the input error pulse d is shifted by one digit to the right register. Therefore, when one error pulse d output from the frequency divider 8 is input to the shift register 22 and then 10 clock signals c are input, the error pulse d is stored in the register of the tenth digit (P9). To reach.

Each signal stored in each digit register P0 to P9 of the shift register 22 is input to each input terminal of A0 to A9 of the signal switching circuit 21. The signal switching circuit 21 sends the signals of the input terminals A0 to A9 corresponding to the data values applied to the control terminals B0 to B3 from the output terminal I to the exclusive OR circuit 6. Each of the control terminals B0 to B3 has a value of 0 to 10 output from the counter 23.
The type of numerical data g is input. The counter 23 counts the error pulse d input from the frequency divider 8 and uses the count value as numerical data g as each of the control terminals B0 to B3 of the signal switching circuit 21.
Send to The counter 23 returns to the initial value 0 when the counted value exceeds 9.

Next, the operation of the error pulse adding circuit thus configured will be described with reference to the time chart of FIG.

For example, it is assumed that a DS-3 signal shown in FIG. 4 composed of a 1-bit frame signal 3 and pseudo-random pattern data 4 having a period of 170 bits as described above is input as the measurement signal b input from the input terminal 5. Therefore, the frame signal 3 as a periodic signal sequence component appears every 170 bits in the measurement signal b. In addition, the period N = 10 from the frequency divider 8
An error pulse d is output for each 0 bit.

Here, assuming that the time when one frame signal 3 of the measurement signal b matches the output phase of the error pulse d is 0 bit,
The frame signal 3 of the measurement signal b is 0,170,340,510,680,85
The error pulse d appears at the bit timing of 0,1020 ...
Are output at bit timings of 0, 100, 200, 300, 400,..., 1000, 1100.

Then, the counter 23 sequentially increases the numerical data g applied to the control terminals B0 to B3 of the signal switching circuit 21 from 0 to 9 every time the error pulse d is input. As a result, each time the numerical data g increases, the digits of the registers P0 to P9 of the shift register 22 from which the error pulse f sent to the exclusive OR circuit 6 is output increase sequentially.

When the digit of the output registers P0 to P9 increases, the time delay from the time when one error pulse d is output from the frequency divider 8 to the time when the error pulse d is output from the shift register 22 is one. Increments by bits.

As described above, when the error pulse d is output from the frequency divider 8 at the bit timing of 0, 100, 200, 300, 400,..., 900, 1000, 1100, 1200. The error pulse f is sent to the exclusive-OR circuit 6 via the switching circuit 21 at 0, 101, 202, 303, 404, ..., 909, 100.
0, 1101, 1202,...

That is, the phase of the output timing of the error pulse f actually added to the measurement signal b shifts backward by one bit with respect to the error pulse d having the period N = 100 bits. When the phase is delayed by 10 bits, the phase returns to the original phase (no bit delay), and the error pulse d output from the frequency divider 8 and the error pulse f input to the exclusive OR circuit 6 are synchronized. . Thereafter, the phase of the error pulse f is sequentially delayed by one bit with respect to the error pulse d.

FIG. 3 shows the output timing of the frame signal 3 included in the measurement signal b, the output timing of the error pulse d in the conventional circuit shown in FIG. 5, and the output timing of the error pulse f in the embodiment circuit shown in FIG. FIG. 3 is a diagram showing output timing by the number of bits from a reference point at which the frame signal 3 shown in FIG. 2 and each of the error pulses d and f are synchronized.

That is, in the conventional circuit shown in FIG. 5, every time ten frame signals 3 are input, that is, at every integral multiple of 1700, the frame signal 3 and the error pulse d are synchronized. as a result,
In the conventional circuit, the occurrence rate of error bits in the frame signal 3 is 10%.

On the other hand, in the embodiment circuit, the frame signal 3
Are input, that is, at every integral multiple of 17,000, the frame signal 3 and the error pulse f are synchronized. Thus, in the circuit of the embodiment, the occurrence rate of error bits in the frame signal 3 is 1%. The 1% error bit occurrence rate matches the set error occurrence rate (1%) determined by the frequency division ratio (1 / N) output from the frequency divider 8 as an error pulse generation circuit.

In FIGS. 2 and 3, the starting point is a point in time when no phase difference occurs between the frame signal 3 and the error pulses d and f. However, for example, as shown in FIG. Even if the state where the phase difference occurs is used as a starting point, the phase difference itself sequentially changes, so that the error occurrence rate in the error measurement signal h output due to the phase difference does not change.

As described above, the rate of occurrence of error bits included in the frame signal 3 of the error measurement signal h is set in the frequency divider 8 as an error pulse generation circuit, that is, the pseudo random pattern data 4 containing no periodic component. Can be made to match the occurrence rate of error bits in Therefore, the error bit occurrence rate of each of the signal components 3 and 4 can be set to an arbitrary value in a state where the error bit occurrence rates are matched.

In the embodiment, the measurement signal b represented by the DS-3 signal is used as an input signal to which an error pulse is added. However, the present invention is not limited to the measurement signal b, and any signal having a periodic signal sequence component Can be applied to the input signal.

Further, a frequency divider having a frequency division ratio of 1 / M (for example, M = 3) may be interposed between the counter 23 and the frequency divider 8.

[Effects of the Invention] As described above, according to the error pulse adding circuit of the present invention, the bit timing added to the input signal of each error pulse output from the error pulse generating circuit using the shift register and the signal switching circuit is determined. It is shifted sequentially. Therefore, the error pulse can be equally applied to the periodic signal sequence component and the general signal component, and the error bit occurrence rate can be arbitrarily set and changed while keeping the error bit occurrence rate in each signal component.

[Brief description of the drawings]

FIG. 1 is a block diagram showing an error pulse adding circuit according to an embodiment of the present invention, FIGS. 2 and 3 are time charts showing the operation of the circuit of the embodiment, and FIG. FIG. 5 is a block diagram showing a conventional error pulse adding circuit, and FIGS. 6 and 7 are time charts showing the operation of the conventional circuit. 3 ... frame signal, 4 ... pseudo-random pattern data, 6 ... exclusive OR circuit, 8 ... frequency divider circuit (error pulse generation circuit), 21 ... signal switching circuit, 22 ... shift register, 23 ... Counter, b ... Measurement signal (input signal), c ... Clock signal, d, f ... Error pulse, g ...
... Numerical data, h ... Error measurement signal.

──────────────────────────────────────────────────続 き Continued on the front page (58) Field surveyed (Int.Cl. ⁶ , DB name) G06F 11/22-11/26 H03K 5/13-5/145

Claims (1)

(57) [Claims] An error pulse output by adding a periodic error pulse to an input signal (b) comprising a periodic signal component (3) having a specified period and a general signal component (4) having no periodic component. An additional circuit, an error pulse generator (8) for outputting an error pulse (d) every predetermined period; an error pulse output from the error pulse generator; and an output timing of the error pulse and the input signal A shift register (22) having a predetermined digit for shifting the input error pulse in synchronization with a clock signal (c) controlling the error pulse, and each time a predetermined number of error pulses are output from the error pulse generation circuit, A signal switching circuit (21) for sequentially switching a digit of the shift register to which a signal is to be output, and an error pulse output from the shift register via the signal switching circuit. XOR and a circuit (6), the periodic signal component (3) and the general signal component to be added to fill force signal (4)
An error pulse adding circuit characterized in that an even periodic error pulse is added to the error pulse.