JP2809655B2 - Digital arithmetic circuit - Google Patents

Description

Description: Object of the Invention (Field of Industrial Application) The present invention relates to a digital arithmetic circuit for calculating an average value of digital data sequentially supplied from the outside, and in particular, for driving a pointer of an analog indicating meter. The present invention relates to a digital arithmetic circuit used.

(Prior Art) In general, a pointer driving device for an analog indicating meter is provided with a digital operation circuit in order to smoothly drive the pointer of the meter. This digital arithmetic circuit calculates an average value of input data supplied from the outside in order to smooth and output the input data, and controls the pointer of the meter based on the calculation result. If the pointer is controlled using the average data in this manner, the phenomenon in which the pointer of the meter responds rapidly can be prevented and the pointer can be driven smoothly, so that the visibility of the meter can be improved.

A conventional digital arithmetic circuit latches data by the number of input data to be averaged in an averaging process of input data to obtain smoothed output data, and performs addition to obtain a sum of the latched data. , And division for obtaining the average value thereof are repeatedly performed. That is,
For example, in the case of a four-averaging process for calculating an average value of four digital data, first, data D1 to D4 are latched, an addition process for obtaining a sum thereof, and a process for dividing the sum by four are executed. . Next, data D2 to D5, data D3 to D6, and data D4 to D7 are sequentially latched, and similar averaging processing is sequentially performed.

In such a configuration, a latch circuit for the number of data to be averaged (for example, four) is required, so that there is a disadvantage that as the number of data to be averaged increases, the circuit scale increases accordingly.

(Problems to be Solved by the Invention) The present invention has been made in view of the above-described circumstances, and has been improved in that a latch circuit for the number of data to be averaged is conventionally required and the circuit scale is increased. It is an object of the present invention to provide a digital operation circuit capable of executing an average processing operation of input data for smoothing an output data value with a small number of latch circuits.

[Structure of the Invention] (Means for Solving the Problems) A digital operation circuit according to the present invention executes an averaging process for smoothing and outputting input data. Here, the averaging process is an operation for obtaining “smoothed output data” even if the input data value changes abruptly. That is, the present invention provides a digital arithmetic circuit which receives digital data sequentially supplied from the outside and calculates smoothed output data in accordance with the received data. Holding means, and adding / subtracting means for performing addition / subtraction of data, and subtracting, from the data previously calculated and held in the temporary holding means, data which is a predetermined number of the data by the adding / subtracting means. Adding the subtraction result to digital data supplied from the outside by the addition / subtraction means, holding the data calculated by the addition in the temporary holding means, and using a predetermined number of data as the output data The arithmetic processing to be output is configured to be repeatedly executed.

(Operation) In this digital arithmetic circuit, first, external first data is latched by the latch means, and data of a value obtained by subtracting a predetermined number of data from the data is calculated. It is calculated by means. Next, the calculation result by the data calculation means is added to the next data supplied from the outside. Then, the content of the latch means is updated to the addition result. By repeating this series of operations, data averaging processing for obtaining smoothed output data is performed.

Since this digital arithmetic circuit has a configuration in which each data is sequentially processed, it is not necessary to latch data by the number of data to be averaged as in the related art, and the scale of the latch means can be reduced.

(Example) Hereinafter, an example of the present invention will be described with reference to the drawings.

FIG. 1 shows a digital operation circuit according to an embodiment of the present invention. In the digital arithmetic circuit 10, the data sequentially supplied from the outside is four bits D1 to D4, and the data after the averaging process is divided into four bits of ∫B1 to ∫B4, respectively.
It is configured to output as bits. The average value obtained by the averaging process corresponds to the above-described four averaging process performed for every four data. Here, as described above, the averaging process means an averaging process for smoothing and outputting the input data. Even if the input data value changes rapidly, the “smoothed output data” is not changed. This is an operation to be obtained.

In the figure, reference numeral 11 denotes an input circuit for sequentially inputting digital data consisting of 4 bits B1 to B4 from the outside. The output of the input circuit 11 is used as the second input sections b1 to b4 of the addition / subtraction circuit 12.
It is connected to the.

The addition / subtraction circuit 12 has two operation modes, an addition mode and a subtraction mode.
The switching is controlled by the control signal GA inverted by. That is, the adder / subtractor circuit 12 operates in the first
Data supplied to the input units a1 to a6 of the second input unit b1 to
The addition processing of the data supplied to b6 is performed, and the addition result is output from the output units F1 to F6. On the other hand, in the case of the subtraction mode, the data supplied to the first input units a1 to a6
, Subtracts the data supplied to the input units b1 to b6, and outputs the subtraction result from the output units F1 to F6. Output units F1 to F6 of the addition / subtraction circuit 12 are connected to respective input units of the latch circuit 13 and the latch circuit 14.

The latch circuit 13 has a data latching capability for 6 bits. The latch timing of data is controlled by a control signal L1, and the output timing of the latched data is controlled by a control signal ▼. The output of the latch circuit 13 is connected to the first input
connected to a1 to a6.

The latch circuit 14 has a data latch capability of 6 bits, its latch timing is controlled by a control signal L2, and its output is connected to each input of the gate circuits 15 and 16. In this case, the 6-bit latch output of the latch circuit 14 is supplied to the gate circuit 15 as it is, but only the upper 4 bits of the 6-bit latch output are supplied to the gate circuit 16. That is, the gate circuit 16 outputs the LSB of the latch output of the latch circuit 14.
The upper two bits from the side are input as LSB. Therefore, the data input to the gate circuit 16
It becomes 1/4 of the data output from 14.

The output timings of these gate circuits 15 and 16 are controlled by a control signal GA, respectively.
Are output to first input portions a1 to a6 of the addition / subtraction circuit 12, and the output of the gate circuit 16 is output to second input portions b1 to b4 of the addition / subtraction circuit 12.
It is connected to the.

The output circuit 17 inputs 1/4 data of the latch output of the latch circuit 14 similarly to the gate circuit 16, and outputs the data as average data # B1 to # B4.

Next, the arithmetic processing operation of the digital arithmetic circuit 10 of FIG. 1 will be described with reference to the timing chart of FIG. As described above, the operation mode of the addition / subtraction circuit 12 is switched by the control signal ▼, and the control signal ▼ is set to “L”.
The level is set to the subtraction mode when GA is at "H" level, and the addition mode is set when the control signal ▲ is at "H" level, that is, when GA is at "L" level. When the control signal GA is at "L" level, the outputs of the input circuit 11 and the latch circuit 13 are open and the outputs of the gate circuits 15 and 16 are open. Conversely, when the control signal GA is at “H” level, the outputs of the gate circuits 15 and 16 are closed and the input circuit 11 and the latch circuit
The output of 13 is closed. Therefore, the addition / subtraction circuit 12 performs an addition process of the output of the input circuit 11 and the output of the latch circuit 13, or a subtraction process of calculating the output of the gate circuit 16 from the output of the gate circuit 15.

The first data D1 supplied from outside is a control signal
When GA is at “L” level, it is input to the addition / subtraction circuit 12. At this time, since the output of the latch circuit 13 is zero, the first input data D1 is output as it is from the addition / subtraction circuit 12 in the addition mode. When the “H” level control signal L2 is generated, the first input data D1 is latched by the latch circuit. With this state as an initial state, the following arithmetic processing is executed.

First, when the control signal GA rises from “L” to “H” level, the first data latched by the latch circuit 14 is output.
D1 is a first input section of the addition / subtraction circuit 12 via the gate circuit 15.
supplied to a1 to a4. Further, data of 部 of the data D1 is supplied to the second input units b1 to b4 of the addition / subtraction circuit 12 via the gate circuit 16. At this time, since the addition / subtraction circuit 12 is in the subtraction mode, the first data D1 is
A process of subtracting 1/4 data is executed. Then, the subtraction result, that is, D1− (D1 / 4) is latched by the latch circuit 13 when the “H” level control signal L1 is generated.

Next, when the control signal GA switches from “H” to “L” level, the data latched by the latch circuit 13, ie, D1
-(A1 / 4) is supplied to the first inputs a1 to a4 of the addition / subtraction circuit 12, and the second data D2 is supplied to the second inputs b1 to b4. Then, the addition of these data is executed,
The addition result D1-(D1 / 4) + D2 is the "H" level control signal.
L2 is latched by the latch circuit 14 when it is generated. One fourth of the data latched by the latch circuit 14 is output by the output circuit 17 as average data.

Then, the above-described arithmetic processing is executed again with the data latched by the latch circuit 14, that is, D1- (D1 / 4) + D2 as an initial value.

By repeatedly performing such processing sequentially,
The average value of the input data can be output from the output circuit 17.

The arithmetic processing characteristics of the digital arithmetic circuit 10, that is, the relationship between input data and output data are as shown in FIGS.

FIG. 3 shows that the value of the input data changes from "0" to "F" (16
(F), and then steeply increases and thereafter maintains the “F” value. As can be seen from this figure, the value of the output data output from the output circuit 17 gradually rises in a time constant and reaches "F" with an increase in the operation cycle in response to a sharp change in the input data.

FIG. 4 shows that the value of the input data changes from “F” to “0”.
, And then steeply decreases and thereafter maintains the “0” value. Also in this case, the value of the output data output from the output circuit 17 gradually decreases in a time constant to reach “0” as the operation cycle increases.

Digital arithmetic circuit having such arithmetic processing characteristics
Numeral 10 is suitable for controlling the pointer of an analog indicating meter. This is because the pointer can be driven smoothly even if the value of the input data changes sharply.

Further, since the digital arithmetic circuit 10 has a configuration in which input data is sequentially arithmetically processed, it is not necessary to provide latch circuits for the number of data to be averaged as in the related art. Therefore, even if the number of data to be subjected to the averaging process increases, the number of necessary latch circuits is only two, that is, the latch circuits 13 and 14.

Note that the latch circuit 13 is only for latching the result of subtraction between the data latched by the latch circuit 14 and 1/4 of the data. It is also possible to latch the result.
In this case, the latch circuit 14 alternately latches the result of subtraction between the data latched by the latch circuit 14 and 1/4 of the data, and the result of addition of the subtraction result and the next input data. become. Therefore, when the latch circuit 13 is not provided, it is necessary to take out the output data from the output circuit 17 only when the latch circuit 14 is latching the addition result. This makes it possible to execute data averaging processing with one latch circuit.

FIG. 5 shows a configuration example of a digital arithmetic circuit suitable for controlling hands such as a speedometer of an automobile. Generally, in a speedometer of an automobile or the like, a pulse signal whose cycle changes in accordance with the vehicle speed is given as input data. When a pulse signal whose cycle changes in this way is input, the pulse signal is converted to an F / V converter and A / D
There is also an example of a method of converting the data into digital data by using a converter. In this embodiment, the preprocessing circuit 21 is provided before the input circuit 11 of the digital arithmetic circuit 10 shown in FIG. Is provided. The preprocessing circuit 21 generates digital data of a predetermined value for a certain period each time a pulse input signal is received from the outside.

For example, when an input pulse signal as shown in FIG. 6A is supplied, the preprocessing circuit 21 synchronizes the value with the rising timing of the pulse signal as shown in FIG. 6B. Generates data of “F” for a certain period (period t).
Therefore, the input circuit 11 of the digital arithmetic circuit 10
Input data that changes rapidly from “F” to “0” is sequentially supplied from the preprocessing circuit 21.

In this case, the output data of the digital arithmetic circuit 10 gradually rises while repeatedly increasing and decreasing as shown in FIG. 6C, as is clear from the input / output characteristics of the digital arithmetic circuit 10 shown in FIG. . Therefore, if this output data is used, the pointer of the meter can be driven smoothly as in the case of the F / V, A / D method described above, and further, it is not necessary to use an F / V converter or an A / D converter. External components such as a CR filter can be eliminated, and a low-cost arithmetic circuit can be provided.

In the digital arithmetic circuit shown in FIG. 1, a value obtained by subtracting 1/4 data from the data latched in the latch circuit 14, that is, D1- (D1 / 4) is calculated by a subtraction process. To (D1 / 4) + (D1 / 4) + (D1 / 4),
Alternatively, it is also possible to calculate by only adding processing by transforming (D1 / 2) + (D1 / 4).

[Effects of the Invention] As described above, according to the present invention, it is not necessary to provide latch circuits for the number of data to be averaged as in the related art. Can be.

[Brief description of the drawings]

FIG. 1 is a circuit diagram showing a digital arithmetic processing circuit according to one embodiment of the present invention, FIG. 2 is a timing chart for explaining the operation of the digital arithmetic circuit shown in FIG. 1, and FIGS. FIG. 5 is a diagram showing the arithmetic processing characteristics of the digital arithmetic circuit shown in FIG. 1, FIG. 5 is a block diagram showing a digital arithmetic circuit according to another embodiment of the present invention, and FIG. 6 is a timing chart illustrating an operation of the arithmetic circuit. 10 ... Digital operation circuit, 11 ... Input circuit, 12 ... Addition / subtraction circuit, 13,14 ... Latch circuit, 15,16 ... Gate circuit, 17 ... Output circuit, 21 ... Preprocessing circuit.

──────────────────────────────────────────────────続 き Continued on front page (58) Field surveyed (Int.Cl. ⁶ , DB name) G06F 17/18

Claims (2)

(57) [Claims] 1. A digital arithmetic circuit for receiving digital data sequentially supplied from the outside and calculating smoothed output data in accordance with the received data. Means, and addition and subtraction means for performing addition and subtraction of data, from the data previously calculated and held in the temporary holding means, subtracted by the addition and subtraction means data that is a predetermined number of the data, The subtraction result is added to digital data supplied from the outside by the addition / subtraction means, the data calculated by the addition is held in the temporary holding means, and a predetermined number of data is output as the output data. A digital arithmetic circuit configured to repeatedly execute the arithmetic processing. A pulse signal having a cycle corresponding to the data value is supplied from the outside, and a preceding data processing circuit for generating digital data of a predetermined value for a predetermined period every time the pulse signal is generated is provided at a preceding stage. 2. The digital arithmetic circuit according to claim 1, wherein digital data generated from the pre-data processing circuit is received as external data and arithmetic processing is performed.