JP2810076B2 - Semiconductor device and manufacturing method thereof - Google Patents

Description

The present invention relates to a wiring film suitable for a semiconductor device, particularly a large scale integrated (LSI) integrated circuit device, and a method for forming the wiring film.

[Conventional technology]

As a wiring film material for an integrated circuit device, a material obtained by adding a small amount of copper to aluminum or a material obtained by adding a small amount of silicon and a noble metal to aluminum is known.

The addition of a small amount of copper to aluminum is described in U.S. Pat. No. 3,725,309, which shows that the electromigration resistance, that is, the effect of preventing disconnection failure of the wiring film due to electromigration is excellent.

A wiring material containing aluminum, a noble metal (Pt, Pd, Rh, Ir) and silicon is disclosed in Japanese Patent Application Laid-Open No. 60-26640, and a wiring film is made of P.
A semiconductor device containing 0.1 to 2 wt% of at least one of d and Pt and being an alloy precipitated in the form of a simple metal or a compound is disclosed in
No. 61-144847.

These wiring film materials are deposited on a semiconductor substrate by a method such as vapor deposition or sputtering, and then formed into a predetermined pattern mainly by wet etching.

Also for those described in JP-A-60-26640 and JP-A-61-144847, it is necessary to improve the resistance to electromigration and the resistance to stress migration.

JP-A-61-144847 discloses a dry etching, but does not disclose any problems.

[Problems to be solved by the invention]

The wiring of a semiconductor device is generally made of Al to which several percent of Si is added. When this device is operated under high current and high temperature conditions, the constituent atoms of the Al wiring film move due to the current flowing therethrough, and the wiring film is raised in a certain section to form a hillock, and the other section is formed. Then, a void is formed. When this hillock grows, it causes a short circuit between wirings. When a void grows, the resistance of the wiring film increases in that section, and the wiring film melts due to heat generated by resistance heating, causing a failure of the semiconductor device.

According to the above-mentioned U.S. Pat.No. 3,725,309, in order to avoid this electromigration problem, 0.1 to 54
The weight percent of Cu is added. Therefore, a precipitation structure of CuAl ₂ particles is formed, which intervenes at the grain boundary and the triple point of the grain boundary of the Al matrix, hinders the movement of Al atoms, and extends the life of the semiconductor device with respect to electromigration. However, CuAl ₂ has a high possibility of segregation, and has a disadvantage that an early failure due to electromigration occurs in a place where CuAl ₂ is not precipitated.

Drawback to be remarkably corrosion Te cowpea to ions, machining accuracy below 1μm is very difficult ^- The Al-Cu alloy is difficult to dry Etsu quenching when processed into wiring patterns, Cl elemental and residual Cl is used There is. In addition, the reliability of moisture resistance when using a semiconductor element may be a problem at the same time.

A passivation film is formed on the Al wiring film to protect the surface. For this reason, a tensile stress is applied to the Al wiring film to cause disconnection, which is a problem caused by so-called stress migration. In particular, in the case of Al-Cu wiring, there is a problem in pattern accuracy, and therefore, there is a disadvantage that disconnection is easily caused from a portion where netting is caused.

Japanese Patent Application Laid-Open No. Sho 60-2664 discloses a method of improving the electromigration resistance of an Al wiring film by adding Cu to Al.
In the above prior arts such as Japanese Patent No. 0 and JP-A-61-144847, no consideration is given to the segregation of Cu, and there is a problem that the life between lots varies. Also, since the Al-Cu alloy has poor corrosion resistance, there is a problem of inferior fine workability due to dry etching or wet etching, and a defect caused during etching due to stress received from the passivation film. There was a problem.

Further, the above-mentioned prior art does not take into account the wiring of the wiring film material in a predetermined pattern by dry etching and the problem in that case.

The inventors of the present invention dry-etch an aluminum wiring film or an aluminum-based alloy wiring film in which a small amount of noble metal, silicon, copper, or the like is added to aluminum, and the side walls of the wiring film are etched obliquely (hereinafter, referred to as side etching). It has been found that a dimensional error occurs in the line width of the wiring film between the upper part and the lower part of the wiring film. Although the problem of side etching does not occur in wet etching, the line width that can be processed by etching is at most several μm.
m, which is not suitable for fine wiring of 1 μm or less.

Recently, in order to further increase the integration of LSIs, there is a tendency to reduce the line width of the wiring film.
The importance of an etching method that can be reduced to μm or less is increasing.

SUMMARY OF THE INVENTION An object of the present invention is to provide a method of manufacturing a semiconductor device having a wiring film on a semiconductor substrate and capable of preventing side etching from occurring during dry etching of the wiring film.

Another object of the present invention is to provide a semiconductor device having a wiring film on a semiconductor substrate, in which side etching is prevented or significantly suppressed.

Still another object of the present invention is to provide a semiconductor device in which side etching of a wiring film is prevented or significantly suppressed, thereby achieving fine wiring.

Still another object of the present invention is to provide a semiconductor device which improves the fine workability of an Al wiring film, is excellent in electromigration resistance and stress migration, and a method of manufacturing the same.

[Means for solving the problem]

The present invention resides in that, in a semiconductor device having a wiring film made of an aluminum-based alloy on a semiconductor substrate, a layer of a substance containing a component contained in a wiring film material is formed on a side wall of the wiring film. This layer can be formed by depositing a wiring film material on a semiconductor substrate, performing a heat treatment, and then performing dry etching.

In the present invention, first, palladium or platinum or palladium and silicon are used as alloy elements for improving corrosion resistance in order to secure dimensional accuracy of fine processing of Al wiring.
Disperse uniformly in the wiring film. Thereby, fine processing can be easily performed. Addition of 5% or less of palladium, platinum, or palladium and silicon can also improve the electromigration resistance. Preferably, in addition to palladium or platinum, lithium, beryllium, magnesium, manganese, iron, cobalt, nickel, copper, lanthanum, chromium, zirconium, cadmium, titanium, tungsten, vanadium, in order to further improve the resistance to stress migration.
At least one of tantalum, niobium and cerium
% Or less.

Further, a thin film of an Al alloy wiring film material having the above composition is deposited on the semiconductor substrate by a known vapor deposition (CVD), electron beam evaporation, or sputtering method, and then subjected to a predetermined heat treatment to obtain a subsequent wiring pattern. In the dry etching step for forming the layer, a layer of a substance containing a component contained in the wiring film material is deposited again on the side wall of the wiring film, so that side etching of the wiring film is prevented or suppressed. Here, it is desirable that the wiring film material is deposited to a thickness of 0.5 to 1 μm. This protective layer is mainly a layer of Pd or Pt oxide and a substance containing carbon contained in an atmosphere gas or resist used for dry etching, and its thickness is desirably 100 nm or less. That is, the carbon contained in the protective layer is contained in the atmosphere gas used for dry etching or in the resist.

Further, this layer may be a layer of a substance containing oxides of Pd and Pt and carbon.

The formation of the protective layer for preventing side etching on the side wall of the wiring layer is not so important in the content of the specific additive element in the aluminum-based alloy. Importantly, the specific additive element is included in the aluminum-based alloy, and the additive element reacts with oxygen or other gas in the etching atmosphere in the dry etching process to form a layer of a material different from the aluminum-based alloy That is. As shown in Table 1 below, the amount of the additive element contained in the aluminum-based alloy was actually small enough.

Here, the gas used for dry etching is CC
l ₄ , at least one of chlorine gas such as BCl ₃ and Cl ₂ or CH
Freon gas containing carbon such as F ₃ and CF ₄ is used.

According to the semiconductor manufacturing method of the present invention, a predetermined heat treatment is performed after a wiring film material made of an aluminum-based alloy having the above-described composition is deposited on a semiconductor substrate, followed by dry etching to form a predetermined wiring pattern. Forming a protective layer containing Pd or Pt oxide of the component in the wiring film material and carbon on the side wall of the wiring film during the dry etching step, thereby preventing or suppressing the side etching of the wiring film during the dry etching. I do.

 The carbon content in the protective layer is approximately 0.01 at% or more.

Further, a protective layer having at least one oxide of palladium and platinum contained in the aluminum alloy and a substance contained in the dry etching gas is formed.

Annealing is the most suitable heat treatment method for a wiring film material deposited on a semiconductor substrate. As a method of annealing, it is desirable to perform a two-stage heat treatment in which the material is heated to a temperature of 200 to 500 ° C., rapidly cooled to room temperature, and heated to 350 ° C. or less, preferably 150 ° to 350 ° C. again. Latter stage 35
The heat treatment of heating to 0 ° C. or lower may be further divided into a plurality of times.

The heat retention time of the heat treatment is desirably 3 to 180 minutes at a temperature of 200 to 500 ° C in the former stage, and 10 to 600 minutes at a temperature of 350 ° C or lower in the latter stage. Even when the heat treatment in the subsequent stage is further divided into a plurality of times, the total time is desirably in the range of 10 to 600 minutes.

The layer formed on the side wall of the wiring film by annealing the wiring film material deposited on the semiconductor substrate and then dry-etching, the aluminum in the wiring film grows during the use of the semiconductor device, and the layer grows to the outside of the wiring film. It has the effect of preventing the hillock from protruding and preventing short circuits. It also has corrosion resistance to the resin used in the mold, and functions as a corrosion protection layer when the passivation film covering the wiring film is broken and components in the resin reach the wiring film.

When palladium or platinum or palladium and silicon are contained as additional elements in the aluminum-based alloy, a layer containing palladium or platinum oxide and carbon can be formed on the side wall of the wiring film during dry etching, and the thickness of this layer is It was confirmed that it was 100 nm or less.

Furthermore, if this palladium or platinum-containing aluminum alloy is dry-etched immediately without heat treatment,
It was confirmed that, in addition to PdO or PtO, a compound of palladium or platinum and aluminum was formed on the etching surface, and that this compound was corroded by chlorine (Cl) gas in the etching gas to cause side etching.

Annealing the palladium or platinum-containing aluminum alloy film, precipitating the compound of palladium or platinum and aluminum, and then performing dry etching, prevents precipitation of the palladium or platinum and aluminum compound on the etching surface during dry etching, Side etching can be suppressed. For this reason, the above-described two-stage heat treatment method is preferable as the annealing method.

As the aluminum alloy containing palladium or platinum, an alloy composed of 5% by weight of palladium or platinum and the balance aluminum, or 0.01 to 3% by weight of palladium
It is desirable to use an alloy consisting of 0.1% to 3% by weight of silicon and the balance of aluminum.

As a method for depositing the wiring film material on the semiconductor substrate, it is desirable to carry out the deposition method as described above, for example, a chemical vapor deposition method called chemical vapor deposition (CVD), an electron beam vapor deposition method, or a sputter method. In particular, the spatter method forcibly dissolves palladium or platinum in an aluminum alloy, and thus has an effect that a subsequent heat treatment can easily precipitate a compound of aluminum and palladium or platinum.

In the semiconductor device of the present invention, a semiconductor substrate having a wiring film is mounted on a lead frame preferably made of copper or an iron-nickel alloy, and the space between the lead frame and the wiring film is preferably substantially made of copper or aluminum. It can be used as a structure electrically connected by metal wires or a structure in which the periphery thereof is sealed with a resin.

Silicon can be used for the semiconductor substrate, and in this case, an intermetallic compound formed by bonding silicon of the substrate and palladium in the wiring film is precipitated at the interface between the substrate and the wiring film.

Further, it can be used as an integrated circuit device (IC), a hybrid IC, a large-scale integrated circuit device (LSI), and the like.

According to the present invention, side etching of a wiring film due to dry etching can be prevented. As a result, the line width of the wiring film can be reduced, and high integration of ICs and LSIs can be achieved.

Since the side wall of the wiring film is cut at a right angle or almost at a right angle, the line width can be 1.3 μm or less, and the ratio of line width / line spacing can be 1 or less, and the line width can be reduced over the entire height of the wiring film. Almost the same can be achieved, and high integration can be achieved. The dimensional error of the line width in the height direction of the wiring film is 0.
It is desirable that the thickness be 1 μm or less. Further, by using a palladium or platinum-containing aluminum alloy wiring, migration resistance and contact property between the semiconductor substrate and the wiring film can be simultaneously improved.

The semiconductor device of the present invention can be applied to a large computer, a personal computer, a word processor, and the like. Of course, it is not limited to these.

[Action]

Hereinafter, the reason why the fine workability, the electromigration resistance, and the contact property with the semiconductor substrate of the wiring film can be improved will be described using an example of a palladium-containing aluminum alloy wiring.

1) Fine workability When palladium is contained in the aluminum (Al) wiring film in an amount equal to or more than the solid solubility limit for Al, specifically, 0.01% by weight or more, the palladium oxide becomes thin in the alumina film formed on the wiring film surface. Produces as a uniform layer. This palladium oxide has a very high corrosion resistance to Cl gas used for dry etching, and prevents parts other than the etching surface from being corroded during dry etching to become AlCl ₃ and sublimate.

In dry etching, the etching gas containing Cl destroys the alumina film on the wiring film surface and combines with active Al to form Al.
Proceed by sublimation as Cl ₃ . By containing palladium in the Al wiring, a palladium oxide layer is formed in the alumina film, and first, a portion which is not etched is protected from an etching gas.

When heat treatment for precipitating a compound of aluminum and palladium in the wiring film is performed, the compound precipitates mainly at the crystal grain boundaries of the aluminum alloy, and the palladium that has not become a compound is finely dispersed in the crystal grains.

At the time of dry etching, the palladium combines with oxygen in the atmosphere to form a palladium oxide, and the palladium oxide is formed in a thin layer on the side wall of the etching surface to prevent side etching.

As described above, since side etching can be prevented, fine wiring, which is an advantage of dry etching, can be realized. According to the present invention, it is possible to achieve a fine wiring having a line width of 1.3 μm or less, which is almost impossible by wet etching, specifically, a fine wiring of 0.5 to 1.3 μm. Further, since the side wall of the wiring film is cut at a right angle or almost at a right angle, the ratio of line width / heat interval can be made 1 or more.

When the palladium-containing aluminum alloy wiring film was used, the line width was substantially the same over the entire area in the height direction of the wiring film, and the dimensional error was 0.05 μm on one side and 0.1 μm or less on the entire area.

Palladium has the best protection against corrosion by Cl gas compared to noble metals such as platinum, gold, iridium and silver or transition metals such as chromium, hafnium, nickel, cobalt, tantalum and niobium.

2) Electromigration resistance In electromigration, Al atoms move through the crystal grain boundaries of the Al wiring film due to the current flowing through the Al wiring, and voids are formed especially at the triple point of the grain boundaries. Is what leads to disconnection. The electromigration resistance can be improved by strengthening the crystal grain boundary of the Al wiring, particularly the grain boundary triple point. 0.01-3% by weight of palladium in Al
By adding and heat-treating, fine precipitates mainly composed of aluminum and palladium compounds can be precipitated at the grain boundaries of Al. Especially 200 ~ 500 as heat treatment method
℃, quenched after annealing for 3 to 180 minutes, then 350 ℃ or less,
By performing the reheating treatment for 10 to 600 minutes, a precipitate can be formed intensively at the triple point of the grain boundary, and the electromigration resistance can be improved.

In order to precipitate a compound of Al and palladium at the triple point of the grain boundary, it is preferable that palladium be contained at a solid solubility limit to aluminum or higher.

The present inventors succeeded in precipitating the compound Al ₃ Pd of aluminum and palladium in a region of 30% or more of the grain boundary triple point by performing the two-stage heat treatment under the above-described conditions. The particle size of the precipitate is 0.3 μm or less.

3) Contact property between semiconductor substrate and wiring film A palladium-containing aluminum alloy wiring film deposited on a silicon substrate by vapor deposition or sputtering is
At the contact hole portion between the silicon substrate and the wiring film, silicon diffuses from the silicon substrate into the wiring film, causing a problem of alloy pits. When the alloy pits are generated, the Si diffusion layer penetrates, and the Al wiring and the Si under the diffusion layer are short-circuited and do not function as a semiconductor element.

In order to prevent alloy pits due to dissolution of silicon (Si) into the Al wiring and to suppress silicon precipitation from the Al, it is necessary to form silicide at the interface between Si and Al. However, it is not yet known that an element added to Al forms silicide. An Al alloy film to which a transition metal and a noble metal were added was prepared and annealed at 450 ° C., and as a result, only the Al—Pd system formed silicide at the interface with Si.

In order to prevent the silicon in the silicon substrate from dissolving into the Al alloy wiring, it is desirable that the wiring film contains silicon. This amount of silicon is particularly effective when it is 0.1% by weight or more. However, the upper limit is preferably limited to 3% by weight from the viewpoint of preventing disconnection of the wiring film.

〔Example〕

 Embodiments of the present invention will be described with reference to the accompanying drawings.

FIG. 1 is an enlarged view of a wiring film portion of a semiconductor device according to the present invention. In FIG. 1, a wiring film 2 made of an aluminum alloy containing palladium is formed on a semiconductor substrate 1, and a layer 3 of carbon-containing palladium oxide is formed on the side wall of the wiring film that has been dry-etched. The layer 3 prevents side etching of the side wall of the wiring film in the dry etching step when forming the wiring film pattern. FIG. 2 schematically shows a state in which the wiring film is side-etched. When the wiring film is dry-etched without performing the heat treatment according to the present invention, such side etching occurs.

FIG. 3 shows a semiconductor device according to an embodiment of the present invention, for example, 4M.
FIG. 3 is a cross-sectional view showing a partial structure of a DRAM, a 1MSRAM, and the like. In Figure 3, 1 is a semiconductor substrate made of silicon substrate, for example, the insulating film 5, 4 denotes an insulating material forming a contact hole, a thickness of SiO ₂ film or PS of 0.1~0.5μm
Made of G film. Reference numeral 2 denotes an Al alloy wiring film obtained by adding 0.01 to 3% by weight of Pd to pure Al or Al with Si. The thickness of the wiring film is LS
In I, it is generally 0.5 to 1 μm. The Al alloy wiring film 2 is in contact with the semiconductor substrate 1 through a contact hole. The exposed surface of the Al alloy wiring film 2 is protected by a passivation film (not shown), for example, a 0.5 to 2.0 μm thick SiO ₂ or PSG or PIQ film. The Al alloy wiring film 2 is connected to a metal wire 6 such as a copper wire, an aluminum wire, a gold wire, or the like by a ball bonding with a bonding pad.
The ball is formed by melting the end of the wire, for example, in a non-oxidizing atmosphere, and forming the ball using surface tension. After the wiring film material is formed on the semiconductor substrate 1, heat treatment is performed to precipitate a compound of aluminum and palladium in the wiring film. After that, dry etching is performed, and wiring is performed in a predetermined pattern. At the time of dry etching, a portion not to be etched is covered with a mask. As a mask, for example, a resist mask is desirably used.

FIG. 4 shows a resin-sealed type in which a semiconductor substrate having a wiring film is mounted on a lead frame 7, the wiring film 2 and the lead frame 7 are electrically connected by metal wires 6, and further sealed with a resin 8. 1 shows a semiconductor device. In FIG. 4, reference numeral 9 denotes a passivation film.

As the metal wire, it is preferable to use a copper wire made of pure copper or substantially copper containing no additional element, and an aluminum wire made of pure aluminum or substantially aluminum containing no additional element.

It is desirable to use copper or an iron-nickel alloy for the lead frame.

FIG. 22 shows a 4MDRAM having a storage element of 4M bits or more.
Also, an example of application to a large-scale integrated circuit device such as a 1MSRAM having a storage element of 1M bits or more is shown.

As shown in the figure, a semiconductor substrate with a large-scale integrated circuit (LS
I) 181, a metal plate 185 of Mo or the like on which the semiconductor substrate is mounted, a wiring film 2 wired on the semiconductor substrate, metal wires 183 for electrically connecting the wiring film to a lead frame 182, An electric insulating cap 184 for hermetically sealing the wiring film and the metal wire is provided. The wiring film 2 is formed by the method described in the above-described embodiment, the side wall of the wiring film is cut at a right angle or almost a right angle, and the palladium contained in the wiring film material is formed along the side wall surface. A protective film containing an oxide and carbon is formed.

The metal plate supporting the semiconductor substrate is composed of a molybdenum plate 185 and a gold-plated copper stud 186. LSI181
Is brazed to a molybdenum (Mo) plate by gold brazing 187.

FIG. 5A shows that the Al-1 wt% Si-0.5 wt% Pd alloy wiring film
This shows the structure when heat treatment was performed at 50 ° C for 30 minutes.
FIG. 5B shows the second time at 300 ° C. for 1 hour and 350 ° C. for 1 hour.
The structure at the time of performing the step heat treatment is shown. The second-stage heat treatment may be performed a plurality of times as described above.
In FIG.5A, precipitates are present at normal grain boundaries,
In FIG. 5B, it can be seen that it exists concentrated at the grain boundary triple point. A detailed examination of the state of grain boundary precipitation in both structures showed that, in the structure of Fig. 5A, grain boundary precipitation mainly accounted for 90% or more, and precipitation at the grain boundary triple point was less than 10%. found. In the structure shown in Fig. 5B, precipitation at the grain boundary triple point is 30.
Accounted for more than%.

FIG. 6 shows the ratio of the precipitate to the grain boundary triple point of the wiring, and the wiring until the wiring is broken by electromigration when a current of 2 × 10 ⁶ A / cm ² is applied to the stripe of the same lot. shows the relationship between the average time t ₅₀ in. Also it shows the average breaking time t ₅₀ and the Pd amount of relationship precipitation 30% of the wiring to the grain boundary triple points in Figure 7. It turns out that Pd addition of 0.01 weight% or more is effective. 6 and 7, the content of Pd is suitably 0.01 to 3% by weight, and when the rate of forming precipitates at the grain boundary triple point by the heat treatment according to the present invention is increased, the electromigration resistance is further improved. Can be enhanced.

FIG. 8 shows that the Al-0.5 wt% Pd-1 wt% Si alloy wiring film was annealed and then re-heated (precipitation heat treatment).
Crystal grains (111) shows the relationship between the average disconnection time t ₅₀ and the dispersion angle of the preferred orientation. Al crystal grains are usually oriented to the most stable (111) plane, but the <111> orientation of each crystal grain is slightly shifted. This shift was measured with X-rays, and the average was defined as the dispersion angle. A large dispersion angle means that the disorder of the crystal grain boundaries is large. The larger the dispersion angle as can be seen from FIG. 8, the average breaking time t ₅₀ becomes shorter. FIG. 9 shows the relationship between the dispersion angle and the annealing temperature. 10A to 10D show the relationship between the precipitation heat treatment and the crystal structure when the annealing temperature is 400 ° C. for 30 minutes. According to FIG. 9, if the annealing temperature is too low, the rearrangement of the crystal grains does not occur. If the annealing temperature is too high, recrystallization occurs and the dispersion angle does not become small. From now on, the annealing condition should be 3 at 200-450 ° C.
Up to 180 minutes can improve migration resistance. On the other hand, from FIG. 10A to FIG. 10D, the grain boundary precipitation does not occur if the temperature of the precipitation heat treatment is too low, and if the temperature is too high, the particle diameter of the precipitate becomes too large, so that Al atoms easily move and migration resistance is improved. Impair. From these, when the precipitation heat treatment is performed at 100 to 400 ° C for 10 to 600 minutes, the precipitate particle size becomes 0.3
It has been found that the migration resistance can be suppressed to not more than μm and the migration resistance can be enhanced.

After subjecting the Al-0.5 wt% Pd-1 wt% Si alloy wiring film to the two-step heat treatment as described above, dry etching is performed to form a predetermined wiring film pattern, as shown in FIG. A layer of palladium oxide is formed on the sidewall.
As described above, this palladium oxide contains carbon, and its content can be controlled by adjusting the conditions of dry etching. FIG. 21 is a drawing showing the relationship between the carbon content and the corrosion current at a natural corrosion potential in an aqueous solution of 100 ppm of chlorine ions showing the corrosiveness of the wiring film. As can be seen from the figure, when the carbon content is 0.01% or more, the corrosion current is reduced to 1/100.

Table 1 shows the amount of dimensional reduction when a wiring film having a thickness of 0.5 μm was formed with a sputter for various wiring film materials, and was subjected to dry etching after heat treatment to be processed to a line width of 1 μm.

It is clear that the wiring film of Al-0.5 wt% (meaning wt%) Pd-1 wt% Si alloy has the smallest dimensional reduction.

FIG. 11 is a schematic sectional view showing a structure of a semiconductor device according to one embodiment of the present invention, in which palladium silicide 25 is partially formed between Al alloy wiring film 2 and Si diffusion layer 24. Reference numeral 22 denotes a passivation film, and 23 denotes a thermally oxidized SiO ₂ film. 12A to 12C show an example of a manufacturing process of the semiconductor device of the present invention. First, the semiconductor substrate 1
A conventional Al-1 wt% Si-1 wt% Pd alloy wiring film is formed thereon by a sputter method, and a wiring pattern is formed as shown in FIG. 12A through a photo-etching step. At this time, lattice defects 27 caused by sputtering of the wiring film material are diffused into the diffusion layer.
An oxide film 28 remains inside 24 and on the surface of the diffusion layer 24. Next, annealing is performed at 400 ° C. for 30 minutes. As shown in FIG. 12B, by this step, the defect 27 at the time of spatter is recovered and a good ohmic contact is formed. Also Al
The native oxide film 28 remaining on the surface when depositing the alloy wiring film is
Reduced by Al, the semiconductor substrate surface becomes clean Si.
Thereafter, a reheating treatment is performed at 200 ° C. for 2 hours. As shown in FIG. 12C, this causes Pd in the Al alloy to concentrate at the Si interface, where it reacts with Si to form silicide 25. At this time, FIG. 13 shows the result of etching the upper Al alloy film and performing XPS analysis of the Si interface. In this case, the Al alloy and the Al intermetallic compound are removed at the time of etching, but the precipitates at the other interfaces remain and are detected by XPS analysis. The elements to be detected are Pd, Si, O, and C. Of these, O and C originate from dirt on the Si surface in the etching step.
As a result of further detailed examination of the detected Pd3d5 / 2 peak, it was found that Pd formed Pd ₂ Si as shown in FIG. Here, even if annealing at 400 ° C. is continued for 2 hours or more, the intensity of the Pd ₂ Si peak in FIG. 14 does not increase, so that the Si interface is completely covered with Pd ₂ Si by annealing under these conditions. At this time, no Si deposition on the Si interface is observed. After that, even if reheating treatment is performed at 200 ° C for 60 minutes, S
i No precipitation occurs and contact resistance hardly changes. The area ratio of Pd ₂ Si covering the Si interface when the heat treatment was reduced at 200 ° C. for 60 minutes and 30 minutes was determined from the XPS spectrum intensity and is shown in Table 2.

80% of the Si interface is not silicided after 30 minutes of reheating
Although it is still Si, even after annealing at 450 ° C. for 60 minutes, the Si precipitation generated at the interface is fine and does not grow large. Therefore, the contact resistance increased only 77% before and after annealing at 450 ° C. for 60 minutes. This is a resistance increase of 1/2 or less as compared with the prior art using Al-1% by weight Si, which shows the effect of the present invention. That is, the formation of silicide is effective even if it does not extend over the entire Si interface. Meanwhile, the reheating temperature of 200 ° C was lowered to 150 ° C,
FIG. 15 shows the XPS spectrum of the Si interface after the heat treatment when the temperature was set to 2 ° C. and 2 hours. In this case, precipitation of Pd alone as well as Pd ₂ Si occurs at the interface. Thereafter, when annealing is performed at 450 ° C. for 60 minutes, the precipitate of Pd alone is re-absorbed into the Al alloy film, and the effect of suppressing Si precipitation is weak. However, also in this case, Pd ₂ Si is sufficiently formed at the interface, and a sufficient effect of suppressing Si precipitation can be obtained. See Table 3.

In this embodiment, the silicide needs to be formed as uniformly as possible at a low temperature. Table 4 shows the silicides formed at relatively low temperatures.

Pd, which forms silicide at the lowest temperature, is advantageous,
Others that form only a kind of silicide at low temperature
Mg. However, when Mg is added to Al, it forms a solid solution with Al and does not appear at the Si interface.

In the above embodiment, a wiring film material in which Pd and Si are dispersed in an Al alloy is used. However, a similar effect can be obtained by using a wiring film material in which Pt or Pt and Si are dispersed in an Al alloy.

The deposition of the wiring film material is desirably performed by vapor phase deposition (CVD), electron beam (EB) deposition, or sputtering. In the case of using the sputtering method, an Al wiring film having uniform and excellent characteristics can be obtained by using a target in which the concentration distribution of the added element is controlled within ± 0.05% of a target value.

Next, palladium or platinum (first additive element)
Less than 5% by weight and at least one of lithium, beryllium, magnesium, manganese, iron, cobalt, nickel, copper, lanthanum, cerium, chromium, zirconium, cadmium, titanium, tungsten, vanadium, tantalum, and lithium. An example in which a wiring film material made of aluminum containing less than 5% by weight (additional element) and the balance containing aluminum or silicon containing less than 3% by weight is used.

The above material is deposited on a semiconductor substrate by a sputtering method, and as a first stage heat treatment, an annealing heat treatment is performed at 400 to 500 ° C. for 10 minutes or more to solid-dissolve the second additive element in the Al base. Quenched at a rate of 10 ° C./sec or more in each case to make the added element a supersaturated solid solution in the Al matrix. Next, to precipitate the supersaturated solid solution as a fine compound, 35
After performing the precipitation heat treatment at a temperature of 0 ° C. or less for 20 to 60 minutes, the solid solution heat treatment is performed within 10 minutes at the annealing temperature in order to re-dissolve the added element in the Al matrix.

In the Al wiring film thus obtained, initially, a precipitate formed of an intermetallic compound of palladium or platinum with aluminum is present, and other additive elements which are dissolved as a current flows through the wiring are included. It can be deposited continuously over time. Therefore, the electromigration resistance and the stress migration resistance of the fine wiring film having a wiring film of 2 μm or less can be significantly improved.

FIG. 16 shows a comparison of wiring life by electromigration of a wiring film formed as described above and a wiring film formed by a conventional method in a high-temperature conduction test. In the figure, the first three examples are wiring films formed by a conventional method. The wiring life is defined as the time at which half of the test samples are disconnected. As is apparent from FIG. 16, the life of the Al alloy wiring of the present invention is longer than that of the conventional wiring.

FIG. 17A shows the microstructure of the Al alloy wiring by the heat treatment of the above embodiment. FIGS. 17B, 17C, and 17D show Al-Si, Al-Pd-
The microstructure of a Si, Al-Pd-Cu-Si wiring material subjected to heat treatment at 450 ° C for 1 hour according to a conventional method is shown. This organization is 8x
After applying a high current density of 10 ⁶ A / cm ² and energizing for 3 hours,
1 shows the structure of an Al alloy film. According to this example, coarse precipitates and fine precipitates are mixed and appear at the grain boundaries, and it can be seen that a fine precipitation reaction is occurring. On the other hand, in the other three examples, the precipitates are coarsened, and the effect of suppressing grain boundary diffusion by pinning of dislocations is lost.

FIG. 18 shows an Al alloy wiring according to the present embodiment and a conventional Al containing Si.
The figure shows the pattern dimensional accuracy when wiring and dry etching were performed with a chlorine-based gas. As is clear from FIG.
When the Al-containing wiring with Si is compared with the Al alloy wiring of this embodiment, it can be seen that this embodiment is more excellent in workability especially in a semiconductor device having a pattern size of 1 μm or less such as 4MDRAM or 1MSRAM.

FIG. 19 shows the results of examining the cumulative failure rate due to stress migration for the conventional Al-Si wiring, the Al-Pd-Si wiring, and the Al-Pd-Mg-Si wiring of the present embodiment. As is clear from FIG. 19, the addition of Mg can significantly improve the resistance to stress migration.
Similar effects can be obtained by adding at least one of the above-mentioned additional elements other than Mg. Figure 20 shows Al-Pd-Si
The graph shows the change in wiring life due to stress migration when Mg is added to the wiring film and the crystal grain size is made smaller than the wiring width (0.8 μm) by heat treatment as described above. As is clear from FIG. 20, the smaller the crystal grain size by adding Mg, the higher the stability. If the crystal grain size is larger than the wiring width, the stress migration life is shorter.

The reason for this is that the disconnection due to stress migration occurs due to the grain boundary diffusion of Al atoms caused by tensile stress. It is thought that this is because the probability of leading to disconnection increases. Note that the effect of making the crystal grains fine can also be obtained when the above-described additive element other than Mg is used. It is considered that the reason why the crystal grain size becomes smaller than 1 μm is that recrystallization of the Al matrix occurs by reheating for a short time at the annealing temperature after the precipitation treatment in the heat treatment of the present invention.

〔The invention's effect〕

According to the present invention, it is possible to obtain a wiring film for a semiconductor which is excellent in corrosion resistance, electromigration resistance and stress migration resistance, and can easily process a wiring pattern of 1 μm or less.

As a result, the density of the semiconductor element of the resin mold or the ceramics mold can be increased, and the semiconductor element can be applied to a fine wiring pattern, and the reliability of the semiconductor device can be improved.

[Brief description of the drawings]

1 is a cross-sectional view of a wiring film schematically showing a semiconductor device of the present invention, FIG. 2 is a cross-sectional view of a wiring film schematically showing a conventional semiconductor device, and FIG. 3 is according to one embodiment of the present invention. FIG. 4 is a partial cross-sectional view of a range-sealed semiconductor device according to another embodiment of the present invention, FIGS. 5A and 5B are organizational diagrams when a wiring film is heat-treated, FIG. 6 is a graph showing the relationship between the rate of precipitation of the compound of Al and Pd at the triple point of the grain boundary and the life (time) against disconnection by electromigration, and FIG. 7 is a graph showing the relationship between the concentration of Pd contained in the wiring film material and the electromigration. FIG. 8 is a graph showing the relationship between the lifetime (time) of the disconnection due to the electromigration, and FIG. 8 is a graph showing the relationship between the lifetime (time) and the dispersion angle of the Al crystal grain. Between annealing temperature and annealing temperature Graph showing, the FIG. 10A-first
FIG. 0D is a drawing showing the structure of each wiring film subjected to the second heat treatment under different conditions, FIG. 11 is a cross-sectional view of a main part of a semiconductor device according to another embodiment of the present invention, and FIGS. 12A to 12C. FIG. 13 is a sectional view showing a change in the structure of the contact portion between the wiring film and the diffusion layer by two heat treatment steps according to the present invention.
After the second heat treatment at 0 ° C. for 2 hours, the Al alloy film was etched away, and the characteristic diagram showing the XPS analysis results performed on the Si interface was removed. FIG. 14 shows the results of detailed measurements performed on Pd3d in FIG. FIG. 15 is a characteristic diagram showing the result of measuring the Pd3d XPS spectrum after the second heat treatment at 200 ° C. for 2 hours by the same procedure as in FIG. 14, and FIG. 16 is a diagram showing various compositions and electro-mechanical properties of the wiring film material. FIGS. 17A to 17D are diagrams showing the relationship of the wiring life to migration disconnection, FIGS. 17A to 17D are diagrams showing the structure of the wiring film when the heat treatment according to the present invention is performed and when the conventional heat treatment is performed, and FIG. FIG. 19 is a drawing showing a comparison of the dimensions of the wiring film after etching according to the present invention with the conventional technique, and FIG. 19 is a drawing showing a comparison between the present invention and the prior art of the failure rate for stress migration disconnection, and FIG. Is added element and stress Graph showing the relationship between the wire life by gray Chillon disconnection, FIG. 21 PdO
FIG. 22 is a drawing showing the relationship between the carbon content in the coating and the corrosion resistance of the wiring, and FIG. 22 is a drawing showing an example in which the present invention is applied to a large-scale integrated circuit device. DESCRIPTION OF SYMBOLS 1 ... Semiconductor substrate, 2 ... Wiring film, 3 ... Palladium oxide layer, 4 and 5 ... Insulating film, 6 ... Metal wire, 7 ...
... Lead frame, 8 ... resin, 9 ... Passivation film.

──────────────────────────────────────────────────続 き Continued on front page (72) Inventor Shinichi Fukada 4026 Kuji-cho, Hitachi City, Ibaraki Prefecture Inside Hitachi, Ltd.Hitachi Research Laboratories (72) Inventor Katsuhiko Shioda 4026 Kuji-machi, Hitachi City, Ibaraki Prefecture Hitachi Research, Ltd. In-house (72) Inventor Motoji Taki 4026 Kuji-cho, Hitachi City, Ibaraki Prefecture Inside Hitachi, Ltd.Hitachi Research Laboratory Co., Ltd. (72) Inventor Tatsuo Itagaki 5-20-1, Kamimizuhoncho, Kodaira-shi, Tokyo Inside Musashi Factory, Hitachi, Ltd. (56) References JP-A-61-144847 (JP, A) (58) Fields investigated (Int. Cl. ⁶ , DB name) H01L 21/3205

Claims (8)

(57) [Claims] 1. A semiconductor device comprising: a silicon substrate; and a plurality of wiring films formed on the silicon substrate.
Weight percent or less, and palladium is precipitated as a simple substance or an intermetallic compound in a region of 30% or more of a triple point of a grain boundary of the alloy, and a wiring film is formed at an interface between the wiring film and the silicon substrate. A film having a precipitate made of palladium silicide formed by combining palladium and silicon therein, and a film having palladium oxide and carbon generated at the time of forming a wiring by dry etching on a side wall of the wiring film; A semiconductor device characterized by the above-mentioned. 2. A step of depositing a layer of a wiring film material of an aluminum alloy containing 5% by weight or less of one selected from palladium and platinum on a semiconductor substrate, and heat-treating the deposited layer of the wiring film material. To deposit an intermetallic compound of one selected from the palladium and platinum and aluminum, and dry-etch the heat-treated wiring film material layer to form a predetermined wiring film pattern A method for manufacturing a semiconductor device, comprising: 3. The dry etching step according to claim 2, wherein one side of each wiring film forming the formed wiring film pattern has one oxide and carbon selected from palladium and platinum. A method for manufacturing a semiconductor device, comprising forming a protective film. 4. A step of depositing a layer of an aluminum alloy wiring film material containing 5% by weight or less of one selected from palladium and platinum on a semiconductor substrate, and annealing the deposited wiring film material layer. Performing a first-stage heat treatment; and performing a second-stage heat treatment on the layer of the wiring film material subjected to the first-stage heat treatment, thereby forming a metal selected from the group consisting of one selected from the group consisting of palladium and platinum and aluminum. A step of depositing an intermetallic compound; and a step of forming a predetermined wiring film pattern by performing dry etching on the layer of the wiring film material that has been subjected to the second-stage heat treatment. Manufacturing method. 5. A method according to claim 4, wherein said palladium and platinum are selected on the side wall of each wiring film forming said wiring film pattern.
A method for manufacturing a semiconductor device, comprising: forming a protective film having two oxides and carbon. 6. A step of depositing a layer of a wiring film material of an aluminum alloy containing palladium on a semiconductor substrate; and a step of subjecting the deposited layer of the wiring film material to a heat treatment to precipitate a compound of aluminum and palladium. Dry etching is performed on the layer of the wiring film material subjected to the heat treatment to form a predetermined pattern of the wiring film, and a palladium oxide is formed on each side wall of the wiring film forming the formed wiring film pattern. Forming a protective film having carbon and carbon, and mounting the semiconductor substrate on a lead frame after the step of forming the wiring pattern and the protective film, and connecting the wiring film and the lead frame with a metal wire. Forming a ball at an end of the metal wire, and connecting the ball to the wiring film by connecting the metal wire to the wiring film. The method of manufacturing a semiconductor device, which comprises a. 7. A semiconductor substrate and a plurality of wiring films formed on the substrate, wherein each of the wiring films contains 5% by weight of a first additive element selected from palladium and platinum. Selected from the following and a second group of additional elements: lithium, beryllium, magnesium, manganese, iron, cobalt, nickel, copper, lanthanum, cerium, chromium, zirconium, cadmium, titanium, tungsten, vanadium, tantalum, and niobium. An aluminum alloy containing at least one of 5% by weight or less;
A protective film having an oxide of an additional element and carbon. 8. A semiconductor substrate comprising a first additive element selected from palladium and platinum in an amount of 5% by weight or less, lithium, beryllium, magnesium, manganese, iron, cobalt, nickel, copper, and lanthanum. Depositing a layer of a wiring film material of an aluminum alloy containing at least 5% by weight of at least one selected from a second additive element group of cerium, cerium, chromium, zirconium, cadmium, titanium, tungsten, vanadium, tantalum, and niobium; Performing a first-stage heat treatment of annealing the deposited wiring film material layer at 200 to 500 ° C. for 10 minutes, and then quenching at a rate of 10 ° C./sec. 35 layers of the applied wiring film material
Heat at a temperature of 0 ° C or less, and then at the annealing temperature of 1 ° C.
Performing a second-stage heat treatment including reheating within 0 minutes; and dry-etching the layer of the wiring film material subjected to the second-stage heat treatment to form a predetermined wiring film pattern. A method of manufacturing a semiconductor device, comprising: