JP2811327B2 - Heterojunction bipolar semiconductor device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Summary] A heterojunction bipolar semiconductor device which can be manufactured by a self-alignment method has a configuration in which an emitter layer can be selectively mesa-etched. To provide a transistor, an n-type compound semiconductor emitter layer and a p-type compound semiconductor
Wide energy band in which the composition for widening the energy band gap between the emitter side and the base side between the type compound semiconductor base layer and the base side is increased in graded and serves also as an etching stop layer -It is configured such that a gap compound semiconductor thin film is interposed.

[Industrial applications]

The present invention relates to a heterojunction bipolar transistor (hetero junction transistor) that can be manufactured by a self-alignment method.
The present invention relates to a semiconductor device called a junction bipolar transistor (HBT).

Since HBTs have high-frequency characteristics that cannot be realized by ordinary silicon-based bipolar transistors, improvements such as higher speeds and higher current gains are currently being made.

[Conventional technology]

FIG. 6 shows an energy band diagram for a conventional graded HBT.

In FIG, E _C is the bottom of the conduction band, the top of E _V valence band, E is n-type AlGaAs emitter layer, G is graded layer, B is p ⁺ -type
A GaAs base layer and C indicate an n-type GaAs collector layer, respectively. In the graded layer G, the x value approaches 0 from the emitter side toward the base side, that is, Al in AlGaAs is gradually reduced to GaAs.

As is well known, in the HBT, a so-called wide gap emitter is formed by using AlGaAs having a wide energy band gap as a material for forming the emitter layer E. Therefore, the emitter efficiency γ is improved.

Fig. 7 shows the energy consumption of the conventional abrite HBT.
It represents a band diagram, and the same symbols as those used in FIG. 6 indicate the same parts or have the same meanings.

As can be seen from the drawing, in this conventional example, the interface between the graded layer G and the base layer B is anabrupt.

Currently, HB as described with reference to FIG. 6 or FIG.
In order to obtain high-speed performance by reducing the size of T, it has been considered to manufacture by a self-alignment method. That is, this kind of
In the HBT, the uppermost layer is usually an emitter layer or an emitter layer + gap layer. In this case, the emitter layer or the emitter layer + gap layer is formed by using an etching protection film having an emitter electrode or an emitter electrode pattern as a patterning mask. The electrode contact surface of the base layer is exposed by mesa etching.

In that case, the applicable etching technique is BC, which can etch GaAs or AlGaAs at a constant speed.
Dry etching method using l ₃ as etching gas, or wet etching using HF or H ₂ SO ₄ based etchant
Using an etching method or the like, the etching of the emitter layer made of AlGaAs is performed with time control so that the base layer is exposed.

[Problems to be solved by the invention]

When manufacturing an HBT by a self-alignment method, mesa etching for exposing the surface of the base layer is extremely important.

Conventionally, for example, a high electron mobility transistor (high eleot
In the case of manufacturing a semiconductor device including a RON mobility transistor (HEMT), for example, when etching GaAs, the etching is performed by using AlGa as an underlayer and interposing AlGaAs.
The so-called selective etching, which automatically stops at the surface of As, is performed. However, in the mesa etching in the case of the HBT, what is etched is AlGa.
As, and the base is GaAs, this mesa
There is no technique for selectively performing etching.

Therefore, as described above, the mesa etching is performed by controlling the time, which causes unevenness in the accuracy of exposing the base surface and the thickness of the base layer.

By the way, recently, an n-type Al _x Ga _1-x As graded layer is provided between an n-type GaAs emitter layer and a p ⁺ -type GaAs base layer, and the composition is changed from the emitter layer to the base layer by x: 0 → 0.3 ,
An HBT in which x = 0.3 and x: 0.3 → 0 is known (if necessary, “IEEE Electron Device Letters, vol. 10, No. 5, MAY
1989 pp202 "). With such a configuration, the emitter layer can be selectively etched with respect to the base layer. However, according to this configuration,
When a bias voltage is applied between the emitter and the base, high-speed electrons must be injected into the base because the shape of the bottom E _C of the conduction band at the junction between the graded layer and the base layer does not become broken. However, there is a problem that the operation speed is reduced.

An object of the present invention is to provide an HBT that can selectively mesa-etch an emitter layer and can operate at high speed.

[Means for solving the problem]

FIG. 1 is an energy band diagram in a thermal equilibrium state for explaining the principle of the present invention, and FIG. 2 is an energy band diagram in an operation state (flat band state) to which a bias voltage is applied. The symbols used in FIGS. 6 and 7 indicate the same parts or have the same meaning.

The difference between the HBT shown in FIGS. 1 and 2 and that shown in FIGS. 6 and 7 is that the constituent material of the emitter layer E is n-type GaAs.
This is because the n-type AlGaAs graded layer G of about 600 [Å] is reverse graded. Here, reverse graded means x from the emitter layer toward the base side.
This means that, for example, x = 0 → 0.3 so that the value gradually increases, and the interface is, of course, anabrupt junction.

In this case, the emitter layer E made of n-type GaAs is formed.
Is etched by n-type AlGa
Automatic stop in As graded layer G.

Thus, in the heterojunction bipolar semiconductor device according to the present invention, the energy is continuously read from the emitter side to the base side between the n-type compound semiconductor emitter layer and the p-type compound semiconductor base layer. The composition for widening the band gap is graded and the wide energy band gap compound semiconductor thin film also serving as an etching stop layer is interposed.

[Action]

By adopting the above means, the emitter layer can be formed by selective etching, and the reverse graded layer inserted as an etching stopper can be removed with high reproducibility and high accuracy, so that the base layer has the required thickness. Thus, a structure suitable for fine processing by performing a self-alignment method is obtained, and is effective for speeding up and reducing power consumption. In addition, since an abrasive junction exists between the emitter layer and the base layer, a hot electron injection effect easily occurs,
Therefore, it is possible to improve the operation speed and the current gain due to hole confinement. The base layer is GaAs
In this case, since the wide energy band gap compound semiconductor thin film exists on the surface of the base layer facing the emitter layer, the surface recombination in the base layer is suppressed and the current gain is reduced. It can also prevent a drop.

〔Example〕

FIG. 3 is a cutaway side view of an essential part of one embodiment of the present invention.

In the figure, 1 is a substrate, 2 is a buffer layer, 3 is a sub-layer.
A collector layer, 4 is a collector layer, 5 is a base layer, 6 is an inverted graded layer, 7 is an emitter layer, 8 is a gap layer, 9 is an emitter electrode, 10 is a base electrode, and 11 is a collector electrode.

The main data of each part is as follows.

(1) About substrate 1 Material: semi-insulating GaAs (2) About buffer layer 2 Material: i-type GaAs Thickness: 2000 [Å] to 3000 [Å] (3) About sub-collector layer 3 Material: n ⁺ type GaAs thickness: 5000 [Å] Impurity concentration: 5 × 10 ¹⁸ [cm ^-3 ] (4) About collector layer 4 Material: n ^- type GaAs Thickness: 5000 [Å] Impurity concentration: 3 × 10 ¹⁶ [cm ³ (5) Base layer 5 Material: p ⁺ -type GaAs Thickness: 1000 [Å] Impurity concentration: 4 × 10 ¹⁹ [cm ^-3 ] (6) Inverted graded layer 6 Material: n-type Al _x Ga _{1- x} As x = 0 (emitter side) → 0.3 (base side) Thickness: 300 [Å] to 500 [Å] Impurity concentration: 5 × 10 ¹⁷ [cm ^-3 ] (7) About emitter layer 7 Material: n-type GaAs Thickness: 2000 [Å] to 3000 [Å] Impurity concentration: 5 × 10 ¹⁷ [cm ⁻³ ] (8) About cap layer 8 Material: n ⁺ type IN _y Ga _{1 -y} Asy = 0 (emitter side) ) → 0.5 (cap side) Thickness: 1000 [Å] Impurity concentration: 1 ~ 5 × 10 ¹⁹ [cm ^-3 ] (9) About emitter electrode 9 Material: Ti / Pt / Au Thickness: 100 [Å] / 900 [Å] / 4000 [Å] (10) About base electrode 10 Material: Ti / Pt / Au Thickness: 100 [Å] / 900 [Å] / 4000 [Å] (11) Collector electrode 11 Material: AuGe / Au Thickness: 200 [Å] / 3000 [Å] In the example, the material of the base layer 5 is p ⁺ -type Ga
Although As is used, this may be replaced with a graded p ⁺ -type AlGaAs layer. In this case, the x value is, for example, 0.1 → 0 from the reverse graded layer side to the base layer side.

FIG. 4 shows an energy band diagram of the semiconductor device shown in FIG. 3, and the same symbols used in FIGS. 1, 2, and 4 indicate the same parts or have the same meanings. Have

As is apparent from the figure, in this HBT, since an emitter-base junction is formed, an electron injected into the base becomes a hot electron, so that the speed is improved. Further, since the ABAP is present not only on the conduction band side but also on the valence band side, holes in the base are unlikely to diffuse to the emitter side, and therefore, the current gain is improved.

It is very easy to manufacture the semiconductor device described with reference to FIGS.

FIG. 5 is a cutaway side view of a main part of a semiconductor device for explaining a case where an emitter layer is formed by a self-alignment method. In FIG. 3, the same symbols as those used in FIG. Shall have the same meaning.

Next, a case of manufacturing the embodiment shown in FIG. 3 will be described with reference to FIG. 3 and FIG.

See Fig. 5. (5) -1 Molecular beam epitaxy
y: MBE) method, the semi-insulating GaAs substrate 1
An i-type GaAs buffer layer 2, an n ⁺ -type GaAs sub-collector layer 3, an n ^-- type GaAs collector layer 4, a p ⁺ -type GaAs base layer 5, an n-type AlGaAs reverse graded layer 6, an n-type GaAs emitter layer 7 , N ⁺ -type InGaAs gap layer 8 are sequentially grown.

(5) -2 A photo resist film 12 having an emitter pattern to be formed is formed by applying a resist process in photolithography technology.

(5) Mesa etching of the n ⁺ -type InGaAs cap layer 8 using the photoresist film 12 as a mask and etching of CCl ₂ F ₂ by applying the ion milling method using Ar Reactive ion etching (reac
By applying the tive ion etching (RIE) method, the n-type GaAs emitter layer 7 is mesa-etched using the photoresist film 12 as a mask.

In this case, the n-type AlGaAs reverse graded layer 6 is made of CCl ₂ F ₂
Is hardly etched due to
Acting as a stopper, the mesa etching thus automatically stops at the surface of the reverse graded layer 6.

See FIG. 3. (3) -1 For example, the n-type AlGaAs reverse graded layer 6 is wet-etched using an HF-based
All parts other than the part that is the base of the etched emitter layer 7 are removed.

In this case, the etching is performed by time control. However, since the thickness of the inversely graded layer 6 is very thin, 300 [300] to 500 [Å], high etching accuracy can be obtained.
When the base layer 5 is made of GaAs, as shown in the illustrated example, the recombination on the base surface is suppressed by leaving the reverse graded layer 6 made of AlGaAs on the base surface. Can be.

(3) -2 After that, a stepwise mesa etching, formation of an electrode, and the like are performed by applying a normal technique to complete the process.

〔The invention's effect〕

In the heterojunction bipolar semiconductor device according to the present invention, the energy band gap is continuously increased from the emitter side to the base side between the n-type compound semiconductor emitter layer and the p-type compound semiconductor base layer. In this case, a wide energy band gap compound semiconductor thin film, which has a large composition for a graded grade and also serves as an etching stop layer, is inserted.

By adopting the above configuration, the emitter layer can be formed by selective etching, and the inverted graded layer inserted as an etching stopper can be removed with high reproducibility and high accuracy, so that the base layer has the required thickness. Thus, a structure suitable for fine processing by performing a self-alignment method is obtained, and is effective for speeding up and reducing power consumption. In addition, since an abrasive junction exists between the emitter layer and the base layer due to the insertion of the reverse graded layer, the hot junction
The electron injection effect is likely to occur, and therefore can contribute to the improvement of the operation speed. Similarly, due to the presence of the break junction, the barrier on the valence band side suppresses injection of holes into the emitter and confine it to the base. Has an effect, which leads to an improvement in the current gain.

[Brief description of the drawings]

FIG. 1 is an energy band diagram in a thermal equilibrium state for explaining the principle of the present invention, and FIG. 2 is an energy band diagram in an operation state (flat band state) to which a bias voltage is applied. FIG. 3 is a cutaway side view of an essential part of one embodiment of the present invention, FIG. 4 is an energy band diagram of the semiconductor device shown in FIG. 3, and FIG. 5 is a case where an emitter layer is formed by a self-alignment method. FIG. 6 is an energy band diagram of a conventional graded-type HBT, and FIG. 7 is an energy band diagram of a conventional-type HBT. I have. In the figure, E _C is the bottom of the conduction band, E _V is the top of the valence band, E is the n-type AlGaAs emitter layer, G is the graded layer, and B is the p ⁺ type.
GaAs base layer, C is n-type GaAs collector layer, 1 is substrate, 2
Is a buffer layer, 3 is a sub-collector layer, 4 is a collector layer, 5 is a base layer, 6 is a reverse graded layer, 7 is an emitter layer, 8 is a cap layer, 9 is an emitter electrode, 10 is a base electrode, 11 is Each shows a collector electrode.

Claims (1)

(57) [Claims] 1. A method for continuously reading energy from an emitter side to a base side between an n-type compound semiconductor emitter layer and a p-type compound semiconductor base layer.
A heterojunction bipolar semiconductor device comprising a wide energy band gap compound semiconductor thin film having a graded composition for widening the band gap and also serving as an etching stop layer.