JP2811580B2 - LSI memory test method - Google Patents

Description

Description: FIELD OF THE INVENTION The present invention relates to a memory test method for a chip-based highly integrated memory.

(Prior art)

Conventional memory test methods include (1) a method of writing "1" or "0" data at all addresses and then reading and checking the data, (2) a march pattern test method, and (3) ) There is a galloping test method.

Here, the march pattern test method means that data “0” is written to all addresses, and “0” is written first from the first address.
After reading and confirming, the sequence of writing data "1" to the first address is repeated until the last address, and "1" is written to the last address. Next, a test method is to read and confirm the last address "1", and then write "0" therefrom, repeating the sequence from the last address to the first address.

The galloping test method is to write data "0" to all addresses and then write the first address data "1". Next, the first address "0" other than the first address is read and confirmed, and then the first address "1" is read and confirmed. Further, after confirming "0" of all addresses other than the first address, data "0" is written to the first address. Thereafter, a similar sequence is repeated until the last address.

[Problems to be solved by the invention]

Recently, with the high integration of memory ICs, the following problems, which have not been a problem in the conventional IC memory, have become problems.

(B) If a write or read operation is performed for a specific address, an error may occur at a different address.

(B) The error (a) occurs only when writing or reading is continuously performed on a specific plurality of addresses.

On the other hand, the test methods according to the prior arts (1) and (2) cannot detect the above-mentioned errors (a) and (b). Further, the error (b) cannot be detected by the method according to the prior art (3), and the memory test requires a long time in this method due to the large capacity of the highly integrated memory.

[Object of the invention]

SUMMARY OF THE INVENTION It is an object of the present invention to effectively solve such a problem in the conventional test method and to provide a memory test method in which the above errors (a) and (b) can be found in a relatively short time test. .

[Means for solving the problem]

The present invention focuses on the fact that the above memory errors (a) and (b) often occur due to the physical structure of an IC memory (such as the arrangement of memory cells and lines). Memory cells to be divided into a plurality of blocks based on common elements of physical configuration such as arrangement and wiring in the memory chip, and writing into the memory cells of any one of the divided blocks This is a method of checking a defect in an LSI memory for examining the effect on memory cells of other blocks when accessed.
By writing to all memory cells of IC memory,
This is charged with the same electric charge, test data is written in a memory cell of one block, and each time the writing is performed, the contents of the memory cells of all other blocks are read out in block units, and the read is performed. The data is compared with the back data. If the result of the comparison is that the read data is different from the back data, error processing is performed. If the read data is equal to the back data, the error processing is sequentially performed. The above problem of the prior art has been solved by writing test data in the block (1) and performing the above-described processes.

The above object was achieved by performing a memory test by the method described above.

〔Example〕

 Next, an embodiment of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram showing a means for executing a test method according to the present invention, and FIG. 2 is a diagram showing a basic flow of the test method according to the present invention. FIG. 3 (A),
FIG. 3B is a diagram for explaining an arrangement relationship of each cell and a state of charges charged in each cell when the memory chip is divided into blocks based on a row address or a column address. In FIG. 1, reference numeral 2 denotes initial setting means for setting the division of blocks and setting test data and back data. Reference numeral 4 denotes a cell characteristic detecting means for examining cell characteristics of each cell in the memory chip when setting back data or the like. Reference numeral 6 denotes a test sequence control means, which controls the entire memory test. Reference numeral 8 denotes back data writing / reading means for testing the basic read / write operation of the memory chip, filling the entire memory with predetermined back data, and preparing for the next test. Numeral 10 is an inter-block error checking means for checking an influence between blocks such as an influence of a write operation to a specific block on another block. Numeral 12 denotes an error processing means for displaying an error such as an error address when the occurrence of an error is confirmed by the back data writing means 8 or the inter-block error checking means 10. 14 is memory tested
It is an IC memory (memory under test).

The operation of each unit in FIG. 1 will be described according to the basic operation flow in FIG.

A. Initial setting (Step 20) Initial setting is performed by the initial setting means 2 and the cell characteristic detecting means 4. (1) Designation of block division, (2) Setting of back data, (3) Setting of test data Consists of

(1) Designation of Block Division Designation of block division, which is one unit of the memory test, is performed based on elements common to the physical configuration of the memory 14 to be inspected.

 FIGS. 3A and 3B show an example.

FIGS. 3A and 3B show the memory under test 14 according to the physical arrangement of cells. FIG. 3A shows a case where a block is divided on the basis of a row address. In this case, a cell common to a row address line in a row is one block. FIG. 3 (B) shows the column
This shows the case where the block is divided based on the address.
Cells common to the column address lines in a column form one block.

(2) Setting of back data The read / write test using the back data is a basic operation test of the entire memory, and at the same time, a test for filling the entire memory with the same data for a subsequent memory test. It is. Therefore, the back data is basically set to all bits “1” or “0”.

In order to fill the entire memory with the same data in this manner, the potential charged in each cell is set to a predetermined level in advance, so that the influence between the blocks due to the charge charge in the subsequent test can be more efficiently reduced. This is because it is possible to perform a test.

However, in this regard, there are the following problems due to the difference in cell structure of the memory chip.

In other words, a memory cell has the same logic level (eg, "1") but has the potential "high" (hereinafter referred to as "H").
Or a row (hereinafter referred to as "L"). Depending on the memory chip, both of these two types of cells may be mixed and used in the same chip. Therefore, even if the back data is simply written as logic "1" or "0" and written to all the addresses of the memory, the charge potential of each cell may not be equalized. For example, in FIG. 3 (A), it is assumed that a block 2 indicated by a row address 1 is constituted by cells indicating a logic "1" by a potential "L", and cells in other blocks are all logic "1". Is composed of cells represented by “H”. If writing is performed on the entire memory chip with the back data set to “1”, only the cells in the block 2 will be at the potential “L”. For a chip having such a configuration, only the address corresponding to the block 2 sets the back data to logic “0” and the others to “1”, thereby setting the charge potential of the entire memory to “H”. "

From the above explanation, to investigate the degree of influence between blocks caused by the charged charge by charging a specific block with the charge on the opposite side to other blocks, the characteristics of each cell constituting the memory chip must be determined. You will understand that you need to know.

The characteristics of each cell in the memory chip can be known by the cell characteristic detecting means 4 (FIG. 1). The cell characteristic detecting means 4 knows the cell characteristics by reading each memory cell immediately after the power is turned on. That is, since the cell is not charged immediately after the power is turned on, the logic level read immediately after the power is turned on is set to “L” of each cell.
It corresponds to the potential. For example, assuming that only block 2 is "L" and represents logic "1" in FIG. 3A, only block 2 of data read immediately after power-on becomes logic "1", and all other blocks are logic "1". Read as "0".
Therefore, for example, if it is desired to set the entire memory cell to the "H" state, data opposite to the logical level read by the cell characteristic detecting means 4 (in the example of FIG. "And" 1 "for the other) may be set as the back data.

(3) Setting of test data Test data refers to data written to a specific block in an inter-block error test.
The test data can be set freely according to the purpose of the test. For example, as shown in FIGS. 3A and 3B, when it is desired to conduct an operation test in which only a specific block (block 2) is charged with a charge opposite to that of another block, the opposite of the back data is performed. Data may be set as test data. Also, if necessary, “101010
The bits may be alternately inverted like... 10 ".

(1) Block division designation as described above,
(2) Setting of back data and (3) designation of test data can be specifically performed as follows. First, according to the basic structure of various IC memories, block division patterns, back data, and test data patterns corresponding to the types of the respective ICs are stored in advance. Then, during the initial setting, the operator
Select and input a storage pattern according to the type of memory or the chip configuration of the IC memory. Alternatively, all data may be input by the operator every time the initial setting is performed.

B. Write and read test of back data (Step 2
2) Write back data specified by the initial setting to the entire memory, read all addresses thereafter, and compare the read data with the back data to check whether a write error has occurred.

C. Inter-block error test (step 24) The inter-block error test is a test for checking the effect of access to one block on another block.

When the writing of the back data and the check thereof are completed, the test data is written to the first block. Thereafter, in order to check whether an error has occurred in another block due to the write operation, a block other than the block in which the test data is written (hereinafter referred to as a “write block”) (hereinafter referred to as a “read block”). That)
Is read and compared with the back data. Next, in order to check whether an error has occurred in the write block by the read operation of the read block, one of the read blocks is checked.
Each time one is read, the write block is read and its contents are compared with test data.

For one write operation to the first block, the above read comparison test is performed for all blocks. After that, the write block number is updated, the next write is performed on the second block, and the same read comparison test is repeated.

By repeating the above write and read operations, when the test data write to all blocks and the read comparison test for each write operation are completed, 1
The inter-block error test using two pieces of back data and test data ends. If necessary, the back data and the test data can be changed to further perform an inter-block error test.

Next, an embodiment of the present invention will be described more specifically with reference to FIG.

FIG. 4 is a flowchart showing a more specific embodiment of the memory test method of the present invention. In this embodiment, it is assumed that each memory cell stores a logic "1" at "H". First, the initial setting means 2 sets the back data to "0", the test data to "1", and the write block number.
WB = 1 and read block number RB = 2 are set (step 30).

Next, the back data "0" is stored in all the blocks by the back data reading / writing means 8 through the sequence control means 6.
Is written (step 32). When the writing is completed, all the data is read and it is checked whether or not the back data has been correctly written (steps 32 and 34). If an error occurs, the process jumps to step 58 for error processing, and an error display or the like is performed. If there is no error, the sequence control means 6 controls the inter-block error test means 10 to perform the following test.

First, test data "1" is written into the block of the write block number WB (block 1 because WB = 1 at present) (step 36). Thereafter, the block with the read block number RB (RB = 2, therefore, block 2) is read, and the read data is compared with the back data to check whether an error has occurred. (Steps 38, 40). By reading and comparing the block 2 in this manner, it is possible to confirm whether or not an error has occurred in the data of the block 2 due to the write operation to the block 1.

Next, thereafter, the write block WB = 1 is read, and the read data is compared with the test data to check whether an error has occurred (steps 42 and 44). Thus, it is possible to check for a write error in the write block and to check the influence on the write block (block 2) due to the read operation of block 2.

In any case, if an error occurs, error processing is performed (steps 40, 42, 58). If no error has occurred, the read block number "RB" is incremented by "1" (step 46). If the result of the addition is equal to the write block number WB, "1" is further added (step
46).

Next, the RB is compared with the last block number LB, and if the RB is smaller than the last block number LB, the process returns to step 38,
The reading of the block RB and the reading test of the block 1 are repeated in the same manner as the previous time (steps 48, 38, 40, 44, 46).

The fact that “RB” has exceeded the last block number LB indicates that the read test of all blocks for the write operation of block 1 has been completed. Therefore, in this case, after writing the same "0" as the back data to block WB = 1 (step 49), "1" is added to WB to update the write block and perform writing. (Step 50). Next, “WB” is compared with the last block number LB. Since WB = 2 has not yet exceeded LB, test data "1" is written for block WB = 2 (steps 52 and 3).
6).

Thereafter, the read comparison test is repeated in the same manner as in the case of writing to the block 1 (steps 38 to 48), and all the effects of the writing operation on the block WB on other blocks are checked. The above operation is performed for all blocks while updating the write block WB. When the WB becomes larger than the last block LB, the process goes from step 52 to step 54 to check whether or not the test for all test data has been completed. You. If not completed, change the initial setting data such as the back data and test data (step 5).
6) Repeat the same test (steps 32-54).

When the test for all the test data is completed, the memory test ends (step 54).

In the present embodiment, the method of writing the updated write block WB by the normal write operation (steps 50, 52, and 36) has been described. However, other instructions that require a higher-speed operation, for example,
The data may be written to the block WB by a MOVE command or the like.

Further, the test of the IC memory according to the present invention may be performed at the final product test stage of a product (for example, ECR) using the IC memory. For example, the final product (ECR
If the IC memory test of the present invention is performed while performing the heat resistance test, etc.), the memory test can be performed under more severe conditions, and the test time can be greatly reduced.

〔The invention's effect〕

As described above, the present invention divides an IC memory into a plurality of blocks so that an error-prone combination may occur in accordance with the structural characteristics of an IC, and then performs another writing when writing into one block. By checking all the effects on the block in block units, a memory error occurring at an address unrelated to the write address can be checked in a short time.

In addition, since back data and test data can be determined after checking the cell characteristics in IC memory in advance, more strict tests are specified in consideration of the influence of charge charge between cells or wiring. Can be performed in block units.

[Brief description of the drawings]

FIG. 1 is a block diagram for explaining means for implementing the test method of the present invention. FIG. 2 is a flowchart showing the basic operation of the test method of the present invention. FIGS. 3A and 3B are diagrams showing the relationship between the blocks of the IC memory divided according to the physical configuration and the charge. FIG. 4 is a flowchart showing one embodiment of the present invention more specifically. 2 ... Initial setting means, 4 ... Cell characteristic detecting means, 6 ...
Test sequence control means 8, back data reading / writing means 10, inter-block error checking means 12, error processing means 14, memory under test.

Continuation of the front page (56) References JP-A-61-27000 (JP, A) JP-A-56-153594 (JP, A) JP-A-1-91399 (JP, A) JP-A-49-70542 (JP) JP-A-51-29040 (JP, A) JP-A-52-85429 (JP, A) JP-A-55-122298 (JP, A) JP-B-56-4999 (JP, B2) JP-B-sho 56-47640 (JP, B2) (58) Fields investigated (Int. Cl. ⁶ , DB name) G11C 29/00

Claims (1)

(57) [Claims] 1. Each of the memory cells constituting an LSI memory is divided into a plurality of blocks based on a common physical configuration element such as arrangement and wiring in the memory chip, and any one of the divided blocks is divided. A method of checking a defect of an LSI memory for examining an influence on a memory cell of another block when a write access is made to a memory cell of (a). By writing to all the memory cells of the IC memory, it is charged with the same electric charge, (b) test data is written to one block memory cell, and (c) every other writing is performed. Reading the contents of the memory cells of the block in block units and comparing the read data with the back data; (d) as a result of the comparison, If the data is different from the back data, error processing is performed. (E) If the read data is equal to the back data, test data is sequentially written to the next block block, and (b) And (d) a method of testing an LSI memory comprising the respective steps for performing the respective steps.