JP2811658B2 - Logic circuit - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a logic circuit, and more particularly to an NTL (non-threshold logic) or an ECL (emitter coupled logic) having an active pull-down circuit.
The present invention relates to technology that is effective when used in circuits.

[Conventional technology]

Conventional high-speed bipolar logic LSIs are configured exclusively using ECL (emitter-coupled logic).
In a logic circuit having an emitter follower output transistor such as an ECL circuit, a good signal rising characteristic can be obtained due to the low output impedance of the emitter follower output transistor. However, the fall characteristics of the signal are determined by the time constant of the load capacitance and the emitter follower resistance.
The power consumption in I will inevitably increase. For this reason,
An active pull-down circuit that suppresses power consumption in a steady state while improving the fall characteristic of an output signal of an emitter follower output circuit has been proposed, for example, in Japanese Patent Application Laid-Open No. 50-134356.

Also, unlike the above ECL circuit, which refers to a threshold voltage and distinguishes between a high level and a low level, NT which does not have a specific logic threshold is used.
There is an L circuit. In an NTL circuit, a signal is amplified through a plurality of gate circuits, and if the input / output transfer characteristics of the plurality of gate circuits cross at approximately the center voltage, the input level higher than this crossing point is sequentially increased. By being amplified, the light finally converges on the high level side. In a logic gate circuit, since a plurality of logic gates are formed in a multi-stage configuration, even if the transfer characteristics of the NTL circuit vary, the level can be increased by passing through another logic gate circuit having similar variation. Since the correction is performed, the dispersion of the transfer characteristics does not actually matter much. like this
For details on NTL circuits, see, for example, March 20, 1976, published by Radio Technology Co., Ltd.
There is.

[Problems to be solved by the invention]

Figure 6 shows an EC with an active pull-down circuit.
A circuit diagram of an example of the L circuit is shown. In a steady state, the transistor Q4 provided at the emitter of the emitter follower output transistor Q3 is biased to its base and emitter voltage V _BE by a bias circuit composed of the resistor R4 and the transistor Q5, so that almost no current flows. And
When the signal that the transistor Q3 switches from the on state to the off state changes, the transistor Q3 is turned on by the opposite phase signal transmitted through the emitter follower transistor Q9,
Discharge output terminal OUT at high speed.

However, if signal switching occurs within the discharge time of the capacitor C1, sufficient fall characteristics of the output signal cannot be obtained. Further, in order to obtain a sufficient fall characteristic of the output signal, it is necessary to increase the capacitance value of the capacitor C1 or increase the steady-state current of the active pull-down transistor Q4. However, this causes problems such as variations in the fall characteristics of the output signal, deterioration of the rise characteristics due to undershoot of the output signal, and an increase in power consumption.

SUMMARY OF THE INVENTION It is an object of the present invention to provide a logic circuit that realizes high-speed output signals while maintaining low power consumption.

The above and other objects and novel features of the present invention will become apparent from the description of the present specification and the accompanying drawings.

[Means for solving the problem]

The outline of a typical invention disclosed in the present application will be briefly described as follows. That is,
For an emitter follower output transistor that receives an output signal formed by a logic unit, an active / inactive signal that is supplied to the base via a capacitor through a phase-inverted signal with respect to an input signal supplied to the base of the output transistor.
A capacitive element that connects a pull-down transistor in series and uses a bias circuit consisting of a transistor receiving a predetermined bias voltage between its base and emitter and an emitter resistor, and feeds back an output signal to the emitter of the transistor constituting the bias circuit. Connect.

(Operation)

According to the above-described means, the base potential of the active pull-down transistor can be lowered via the bias transistor when the output signal falls due to the feedback capacitive element, and excessive operation thereof can be suppressed. Can be prevented.

〔Example〕

FIG. 1 is a circuit diagram showing an embodiment in which the active pull-down circuit according to the present invention is used in an NTL circuit. Each circuit element in the figure is formed on one semiconductor substrate such as single crystal silicon by a known bipolar integrated circuit manufacturing technique.

Transistors Q1 and Q2 that receive signals from input terminals IN1 and IN2
The circuit consisting of the resistor R1 provided at the common collector of the transistors Q1 and Q2 and the resistor R2 provided at the common emitter constitutes an NTL circuit. That is, when the signal of the input carrier IN1 or IN2 is at a high level,
When these transistors Q1 or Q2 are turned on,
A low-level output signal such as about -0.5 V determined by the resistance ratio of R1 and R2 is formed, and when the signals at the input terminals IN1 and IN2 are both low, the transistors Q1 and Q2 are both turned off, and their collectors are turned off. To form a high-level output signal b such as 0V. Therefore, this NTL circuit constitutes a two-input NOR gate logic circuit.

The collector output signal b of the transistors Q1 and Q2 is supplied to the base of the emitter follower output transistor Q3. The active pull-down transistor Q4 is connected in series to the emitter of the transistor Q3. The base of the transistor Q4 has a phase inverted output signal c obtained from the emitters of the transistors Q1 and Q2.
Is supplied via the capacitor C1. This transistor
To allow a relatively small idling current to flow when Q4 is in a steady state, the following bias circuit is provided.

A transistor Q6 receiving a predetermined bias voltage VB2 and an emitter resistor R4 are provided between the base and the emitter of the transistor Q4. The emitter of a transistor Q5 receiving a predetermined bias voltage VB1 is connected to the base of the transistor Q4. The collector of this transistor Q5 is connected to the ground potential point.

In order to prevent undershoot of the output signal, in this embodiment, a capacitor C2 for feeding the output signal back to the emitter of the bias transistor Q6 is provided.

For example, when the signals at the input terminals IN1 and IN2 are both low and the transistors Q1 and Q2 are off, the collector output goes to a high level such as the ground potential 0V. Therefore, the potential of the output terminal OUT is at a high level such as about -0.8 V because the high level is level-shifted via the base and the emitter of the emitter follower output transistor Q3.

From this state, when the signal a of the input terminal IN1 changes from low level to high level, the output signal b changes from high level to low level. In response, the output transistor Q3 is substantially turned off, and the inverted output signal c obtained from the emitter of the transistor Q1 changes from the low level to the high level, and the capacitor C1 changes in response to the change to the high level. The base potential of the transistor Q4 is temporarily set to the high level via the transistor Q4. This allows the transistor Q4
Is turned on, and the output signal d of the output terminal OUT changes from the high level to the low level at high speed. At this time, the emitter potential of the transistor Q6 is AC-lowered on the low level side via the capacitor C2. As a result, the collector current of the transistor Q6 flows, and acts to lower the base potential of the transistor Q4. In other words, the capacitor C1 corresponds to the high-level change of the signal c.
From the transistor Q4 to the base of the transistor Q4 is suppressed by the low-level signal fed back via the capacitor C2. Thus, it is possible to prevent undershoot from occurring in the output signal d.

As described above, since the undershoot of the output signal d can be prevented, the capacitance value of the capacitor C1 is set to be relatively large in order to improve the fall characteristic of the output signal d to the low level, and the fall characteristic is set. While improving
It is possible to prevent the output signal d from undershooting due to the feedback as described above by the capacitor C2. This means that the rise characteristic of the base potential of the transistor Q4 can be substantially prevented from deteriorating.

The capacitor C1 can be set to a relatively large capacitance value by using the base extraction electrode of the transistor Q2 without substantially increasing the layout area. Note that the feedback capacitor C2 is also configured using an emitter extraction electrode such as the transistor Q6, so that the layout area can be reduced.

The operating voltage of the output circuit through which a relatively large current flows is configured separately from the input logic unit having a relatively small operating current. That is, the power supply lines of the input logic section are set to Vcc and -VEE, and the output section is divided to Vcc 'and -VEE'. This prevents the noise generated on the power supply lines Vcc 'and -VEE' from being transmitted to the input logic unit due to the operation of the output circuit, thereby preventing the signal level margin from deteriorating.

FIG. 2 is a circuit diagram of another embodiment in which the active pull-down circuit according to the present invention is used in an NTL circuit.

In this embodiment, the output signal d is fed back to the base of the transistor Q5 via the capacitor C3. Although not particularly limited, the bias voltage supplied to the bases of the transistors Q6 and Q5 is formed by a series circuit including diodes D1 and D2 and a resistor R5. That is, the base of the transistor Q6, the forward voltage V _F by the diode D1 is supplied. The base of the transistor Q5 is supplied with a forward voltage 2V _F by the diodes D1 and D2. Resistance R5
Forms a bias constant current flowing through the diodes D1 and D2. A constant current of − (VEE−2V _F ) / R5 flows through the resistor R5, and a constant current according to this constant current flows through the transistors Q5 and Q6.

In this configuration, a circuit for forming the bias voltages VB1 and VB2 can be formed from a simple circuit such as the resistor R5 and the diodes D1 and D2.

The feedback capacitor C3 improves the rising characteristic of the output signal d. That is, when the output signal d changes from the low level to the high level, the base potential of the transistor Q5 is increased via the capacitor C3. This allows
When the inverted input signal c changes from the high level to the low level, the decrease in the potential of the transistor Q4 due to the capacitor C1 is suppressed. In other words, when the potential of the transistor Q4 drops below the steady state, the transistor Q4 is turned on after the recovery, and the response when the signal c is rapidly switched from the low level to the high level according to the input signal. Poor characteristics. In this embodiment, when the output signal d changes to a high level, the base signal of the transistor Q4 transmitted from the capacitor C1 by the feedback signal from the capacitor C3 is prevented from becoming lower than the bias point.

Thus, in this embodiment, the feedback capacitor C2
With C3, input switching response characteristics can be significantly improved.

FIG. 3 is a circuit diagram of still another embodiment in which the active pull-down circuit according to the present invention is used in an NTL meeting.

When an active pull-down circuit is used, a circuit for generating a bias voltage VB1 for allowing an idling current to flow through the pull-down transistor Q4 as described above is required. The bias circuit of this embodiment includes series diodes D1 and D2 and a resistor R5, similarly to the bias circuit used in the above embodiment.

That is, the forward voltage 2V _F formed by the diodes D1 and D2 is supplied to the base of the transistor Q5. As a result, the transistor Q5 and the diodes D1 and D2 are in a current mirror form, and a constant current according to the constant current formed by the resistor R5 can flow through the transistors Q5 and Q4. By adopting such a configuration, the active
This makes it possible to simplify the bias circuit when a pull-down circuit is used.

FIG. 4 is a circuit diagram of an embodiment in which the active pull-down circuit according to the present invention is used in an ECL circuit.

In the ECL circuit, an output signal and an inverted signal are obtained from the differential transistor circuit. Therefore, the inverted signal transmitted to the base of the active pull-down transistor Q4 is obtained from the emitter of the emitter follower output transistor Q9 receiving the collector output of the inverted output transistor Q7 receiving the reference voltage VBB.

In this case, the load resistance in the differential transistor circuit
It is divided into RC2 and RC3, and sets the amount of signal transmitted to the base of the active pull-down transistor Q4 via the capacitor C1. This allows the active
The base response characteristics of the pull-down transistor Q4 can be optimally set. That is, it is possible to prevent an undershoot caused by transmission of an excessive signal to the base of the transistor Q4 through the capacitor C1, and an excessive reverse bias of the transistor Q4 when the output signal rises.

Incidentally, the bias circuit of this embodiment has the series diodes D1 and D2 and the resistor R as in the bias circuit used in the above embodiment.
Consists of five. That is, the forward voltage 2V _F formed by the diodes D1 and D2 is supplied to the base of the transistor Q5. This allows the transistor Q5 and the diode
D1 and D2 are in the form of a current mirror, and a constant current according to the constant current formed by the resistor R5 can flow through the transistors Q5 and Q4. By adopting such a configuration, the simplification of the bias circuit in the case of using the active pull-down circuit is facilitated. Instead of this configuration, the bias circuit may supply a predetermined bias current VB1 to the base of the transistor Q5.

FIG. 5 is a circuit diagram of still another embodiment in which the active pull-down circuit according to the present invention is used in an NTL circuit.

In this embodiment, the diode D3 is used as a variable capacitance element, and is used to feed back an output signal to the base of the active pull-down transistor Q4. In this configuration, when the input signal IN1 rises to a high level, the diode D1 is reverse-biased and has a small capacitance value. Therefore, the pulse current that escapes through the diode D3 can be reduced. On the other hand, when the input IN1 falls, the transistor Q4
Can be compensated for by the rise of the output signal at the output terminal OUT which is fed back via the diode D1. At this time, since the reverse bias voltage is low, the capacitance value increases in proportion to the reverse bias voltage, and the feedback amount of the output signal can be increased. That is, this diode D3 is the capacitor of FIG.
It has the same effect as C3. In the circuit of FIG. 2, there is no problem because the capacitor C3 and the capacitor C1 are separated by the transistor Q5. However, as in this embodiment, the capacitor C1 and the feedback capacitive element are connected in series with the output terminal OUT. Then, as described above, the signal transmitted to the base of the transistor Q4 through the capacitor C1 escapes to the output terminal side via the feedback capacitance element, but the diode D1 as a variable capacitance element as described above is used. This can be prevented.

The transistor Q5 receiving the bias voltage VB1 supplies a bias current to the transistor Q4, and the transistor Q5 'and the resistor R4' provided at the emitter thereof are biased to reverse bias the diode D1 to act as a capacitive element. Form a voltage.

The operational effects obtained from the above embodiment are as follows. That is, (1) For an emitter follower output transistor receiving an output signal formed by a logic unit, a signal whose phase is inverted with respect to an input signal supplied to the base of the output transistor is supplied to the base via a capacitive element. The active pull-down transistor is connected in series, and a bias circuit consisting of a transistor receiving a predetermined bias voltage between its base and emitter and an emitter resistor is used to output an output signal to the emitter of the transistor constituting the bias circuit. Connect the capacitive element to be fed back. In this configuration, the base potential of the active pull-down transistor is lowered via the bias transistor when the output signal falls due to the feedback capacitive element,
Since the excessive operation can be suppressed, the effect of improving the fall characteristic of the output signal and preventing the occurrence of output undershoot can be obtained.

(2) With respect to the emitter follower output transistor receiving the output signal formed by the logic unit, a signal whose phase is inverted with respect to the input signal supplied to the base of the output transistor is supplied to the base via the capacitive element. An active pull-down transistor is connected in series, and a bias current supply transistor having an emitter coupled to the base of the active pull-down transistor as a bias circuit provided at the base of the active pull-down transistor; The use of two resistive elements, which are provided between the base and the emitter of the active pull-down transistor and allow two bias currents to flow, has the effect of simplifying the circuit.

(3) When the logic section is configured by an ELC circuit, by dividing the load resistance forming the inverted output signal of the differential transistor circuit and adjusting the signal amount supplied to the base of the active pull-down transistor, The effect that the operation of the active pull-down transistor can be optimally set by a simple configuration is obtained.

Although the invention made by the inventor has been specifically described based on the embodiments, the invention is not limited to the above-described embodiments, and various changes can be made without departing from the gist of the invention. Nor. For example, the circuit of the embodiment shown in FIGS. 1 and 2 may be replaced with an input logic unit ECL circuit. The load resistance RL provided at the output terminal OUT in each embodiment circuit generally represents a load, and does not mean that such a resistance element is connected. The power supply line and the operating voltage of the logic unit and the output unit may be divided as necessary. The number of input terminals may be increased or decreased as needed.

INDUSTRIAL APPLICABILITY The present invention can be widely used for a logic circuit including a high-speed logic unit such as NTL or ECL and an active pull-down circuit.

〔The invention's effect〕

The effects obtained by the representative inventions among the inventions disclosed in the present application will be briefly described as follows. That is, an active follower in which a signal whose phase is inverted with respect to an input signal supplied to the base of the output transistor is supplied to the base via the capacitor with respect to the emitter follower output transistor receiving the output signal formed by the logic unit. A capacitor for connecting a pull-down transistor in series and using a bias circuit consisting of a transistor receiving a predetermined bias voltage between its base and emitter and an emitter resistor to feed an output signal back to the emitter of the transistor constituting the bias circuit; Connect the elements. With this configuration, the base potential of the active pull-down transistor can be reduced via the bias transistor when the output signal falls due to the feedback capacitive element, and the excess operation can be suppressed. And the occurrence of output undershoot can be prevented.

[Brief description of the drawings]

FIG. 1 is a circuit diagram showing an embodiment in which an active pull-down circuit according to the present invention is used in an NTL circuit, and FIG. 2 is a circuit diagram showing an active pull-down circuit according to the present invention in an NTL circuit. FIG. 3 is a circuit diagram showing another embodiment in which the active pull-down circuit according to the present invention is used in an NTL circuit, and FIG. FIG. 5 is a circuit diagram showing an embodiment in which an active pull-down circuit according to the present invention is used in an ECL circuit. FIG. 5 is a diagram showing an active pull-down circuit according to the present invention used in an NTL circuit. FIG. 6 is a circuit diagram showing an example of a conventional active pull-down circuit. Q1-Q9: Transistor, R1-R9, RC1-RC3: Resistance, D
1 to D1 ... diode, D3 ... diode (variable capacitance element), C1 to C3 ... capacitor, IN1, IN2 ... input terminals, O
UT …… Output terminal

────────────────────────────────────────────────── ─── Continuing on the front page (72) Inventor Kazuyoshi Sato 2326 Imai, Ome-shi, Tokyo Inside the Device Development Center, Hitachi, Ltd. (58) Field surveyed (Int. Cl. ⁶ , DB name) H03K 19/086 , 19/088

Claims (5)

(57) [Claims] A logic unit; an emitter follower output transistor for receiving an output signal formed by the logic unit; a collector connected to an emitter of the emitter follower output transistor; and a logic unit connected to a base of the emitter follower output transistor. A signal whose phase is inverted with respect to the output signal supplied from the logic unit is supplied from the logic unit to the base via the first capacitive element, and a transistor receiving a predetermined bias voltage between the base and the emitter, and an emitter resistor An active pull-down transistor provided with a bias circuit comprising: an emitter-follower output transistor; and an output signal at a connection point between the emitter of the active pull-down transistor and the collector of the active pull-down transistor. The second to return to Logic circuit which comprises a capacitive element. 2. A logic section, an emitter follower output transistor receiving an output signal formed by the logic section, a collector connected to the emitter of the emitter follower output transistor, and a logic section connected to a base of the emitter follower output transistor. A signal whose phase is inverted with respect to the output signal supplied from the logic unit is supplied to the base from the logic unit via the first capacitor, and an active pull-up circuit having a resistor provided between the base and the emitter is provided. A down-transistor; a bias current supply transistor having an emitter coupled to the base of the active pull-down transistor; and 2 provided between the base of the bias current supply transistor and the emitter of the active pull-down transistor. And a forward diode consisting of Logic circuit which comprises a resistor for flowing a bias current in the forward direction diode. 3. The logic circuit according to claim 1, wherein said logic unit is constituted by an NTL circuit or an ECL circuit. 4. A logic unit, an emitter follower output transistor receiving an output signal formed by the logic unit, a collector connected to an emitter of the emitter follower output transistor, and a logic unit connected to a base of the emitter follower output transistor. A signal whose phase is inverted with respect to the output signal supplied from the logic unit is supplied to the base from the logic unit via the first capacitor, and an active pull-up circuit having a resistor provided between the base and the emitter is provided. A down transistor; a bias current supply transistor having an emitter coupled to the base of the active pull down transistor; and a resistor provided between the base of the bias current supply transistor and the emitter of the active pull down transistor. And the emitter follower output A variable capacitance element as a second capacitance element for feeding back an output signal of a connection point between the emitter of the transistor and the collector of the active pull-down transistor to the base of the active pull-down transistor. Logic circuit. 5. The logic circuit according to claim 4, wherein said logic section is constituted by an ECL circuit.