JP2813838B2 - Analog memory device and control circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION (Industrial Application Field) The present invention relates to an analog memory element for storing an amount of charge storage as an analog amount, and an element capable of easily increasing and decreasing the amount of charge little by little, and an element thereof. It relates to a control circuit.

(Prior Art) There have been many cases where it is necessary to store an analog signal amount on an LSI. For example, storage of voice and image signals, storage of weighting factors of neural circuits, and the like are typical examples. However, there has been no semiconductor device that can be practically used for storing an accurate analog amount. Therefore, when analog storage is required, there is no choice but to digitize it and store each bit in a digital memory. As a result, the number of memory devices and the occupied area increase.

Therefore, development of a memory element capable of directly storing an analog signal amount has been desired. The most likely of the conventional devices is a so-called floating gate MOS transistor which performs analog storage with the amount of charge stored in a gate electrically isolated from the surroundings. However, this floating gate MOS transistor is not suitable for accurate analog storage as it is. That is, in the conventional floating gate MOS transistor, when a voltage pulse is applied to the floating gate to inject electric charge from the tunnel junction into the floating gate, the amount of injected electric charge is the amount of electric charge already accumulated in the floating gate, and However, it is not easy to accurately set and store an arbitrary analog amount because it depends greatly on the height and width of the applied voltage pulse. The problem is briefly described below with reference to the drawings.

(Problem to be Solved by the Invention) FIG. 5 shows a structure of a conventional floating gate MOS transistor. In the figure, 1 is a floating gate, 2 is a control gate, 3
Indicates a tunnel junction, 4 indicates a drain, and 5 indicates a source. In this device, when a voltage for charge injection is applied to the control gate 2, a high electric field is applied to the electron barrier of the tunnel junction 3, and as a result, the drain 4 and the floating gate 1
During this time, a tunnel current flows, and charges are injected into the floating gate 1. FIG. 6 shows a temporal change in the amount of charge injected into the floating gate 1 when a constant pulse voltage for charge injection (writing: positive voltage pulse, erasing: negative voltage pulse) is repeatedly applied to the control gate 2. As the charge is injected, the potential of the floating gate 1 changes, the voltage applied to the tunnel junction decreases, and the tunnel current stops flowing, reaching an equilibrium state.
That is, the amount of charge injected differs depending on the amount of charge already stored in the floating gate 1. Conversely, in order to inject a certain amount of electric charge, it is necessary to measure the amount of electric charge stored in the floating gate 1 and then apply a pulse having a different voltage and width according to the measured value. Moreover,
Complicated calculations are required to determine the pulse voltage and width values for this purpose. As described above, it is not easy to control the charge amount of the floating gate 1.

The present invention has been proposed in order to improve the above-mentioned drawbacks, and an object of the present invention is to provide a pulse control gate structure that solves the point that it was difficult to adjust the amount of charge stored in the floating gate minutely and efficiently. An object of the present invention is to provide an analog memory device having the same and a control circuit therefor.

(Means for Solving the Problems) In order to achieve the above object, the present invention relates to a MOS transistor memory device having a floating gate which is arranged via a tunnel junction with respect to a source and a drain. An object of the present invention is to provide an analog memory element characterized in that a control gate electrode and a pulse control gate electrode for applying a pulse voltage are stacked on the floating gate.

Further, the present invention provides a method in which a drain current or voltage is set to a desired value for an analog memory element formed by stacking a bias control gate electrode for applying a bias potential and a pulse control gate electrode for applying a pulse voltage on the floating gate. An object of the present invention is to provide an analog memory element control circuit, characterized in that a gate bias generation circuit for maintaining the above-mentioned condition is connected to a bias control gate and a control pulse is applied to the pulse control gate.

(Function) In the present invention, in a MOS transistor memory element having a floating gate, charges are injected into the floating gate by providing a bias control gate electrode for applying a bias potential to the floating gate and a pulse control gate electrode for applying a pulse voltage. In this case, the floating gate charge amount can be adjusted with high accuracy only by applying the control voltage pulse.

(Example) Next, an example of the present invention will be described. It should be noted that the embodiments are merely examples, and it is needless to say that various changes or improvements can be made without departing from the spirit of the present invention.

FIG. 1 shows an embodiment of the analog memory device of the present invention. In the figure, 1 is a floating gate, 6 is a bias control gate, 7 is a pulse control gate, 8 is an oxide film, 4 is a drain, and 5 is a gate. That is, the bias control gate 6 and the pulse control gate 7 are stacked on the floating gate 1 and formed.

Next, the operation of the analog memory device of the present invention will be described.

First, a voltage is applied to the bias control gate 6 so that the potential of the floating gate 1 is adjusted to a certain value. Next, a voltage pulse is applied to the pulse control gate 7 to induce a pulse voltage on the bias control electrode 6 and the floating gate 1, and charges are injected into the floating gate 1 via the tunnel junction 3. However, at this time, a high resistance is connected in series with a voltage source in an external circuit coupled to the bias control gate 6 so that a pulse voltage is induced in the bias control gate electrode 6 (third resistor). Figure). When a constant pulse is applied while the floating gate potential is controlled to a constant value, the amount of injected charge is always constant.

As described above, according to the analog memory element of the present invention, by performing the bias control of the floating gate potential 1, a constant amount of charge is always injected for a constant voltage pulse. It is easy to make accurate adjustments in small quantities.

FIG. 2 shows a second embodiment of the analog memory device of the present invention. The difference from the first embodiment is that the high resistance layer 9 connected in series to the bias control gate electrode is formed as an integral structure. The high-resistance layer 9 is for reducing the capacitive load of the pulse control gate 7 with respect to the voltage pulse so that the pulse voltage is sufficiently induced. Also, the time constant of the bias control circuit is increased, and the variation and oscillation of the bias control circuit due to the influence of pulse application are suppressed. The same effect can be obtained even if the entire bias control gate electrode is formed of a high resistance layer.

Next, a control circuit of the bias control gate of the analog memory element will be described. This control circuit is a circuit that controls the voltage of the bias control gate in order to maintain the potential of the floating gate at a certain value.

FIG. 3 shows a control circuit of the present invention. The source / drain current / voltage measuring circuit 10 measures the source / drain current or voltage of the MOS transistor. The gate bias voltage generation circuit 11 compares the source / drain current or voltage with a fixed target value, and changes the output voltage, that is, the gate voltage, in a direction in which the source / drain current or voltage approaches the fixed target value. For example, in the case of an n-channel MOS transistor, when the source / drain current is smaller than the target value, the source / drain current is increased by increasing the output voltage to increase the gate voltage. Conversely, when the output voltage is larger than the target value, the output voltage is lowered and the gate voltage is lowered to reduce the source / drain current. p
In the case of a channel MOS transistor, the increase and decrease are reversed. A high resistance is connected to the bias control gate electrode in series equivalently, or the output of the gate bias voltage generation circuit is set to a high impedance. Thereby, the oscillation phenomenon in the feedback control circuit of the bias control gate can be suppressed.

By controlling the voltage of the bias control gate 6 and holding the source / drain current or voltage at a certain value, the MOS
The electric field applied to the channel region of the transistor is kept at a certain value. That is, the potential of the floating gate 1 is controlled to be substantially equal to a certain value. After this state, if a voltage pulse is applied to the pulse control gate 7, the amount of injected charge can be kept substantially constant regardless of the amount of charge stored in the floating gate. The amount of charge injected in one pulse can be adjusted by the pulse width, and the amount of change can be reduced by shortening the pulse width. When a constant pulse voltage for charge injection (writing: positive voltage pulse, erasing: negative voltage pulse) is repeatedly applied to the control gate, the time variation of the amount of charge injected to the floating gate is substantially linear as shown in FIG. Become FIG. 4 shows the pulse application circuit on the horizontal axis and the charge amount of the floating gate on the vertical axis.

As described above, if write / erase control is performed using the control circuit of the present invention, it is easy to arbitrarily set and store an analog amount with a certain accuracy by repeatedly applying a certain voltage pulse. Can be. As the memory output, the gate bias voltage in the operation state of the control circuit may be used, or the drain voltage or the drain current when the gate bias voltage is fixed to a specific value may be used.

(Effects of the Invention) As described above, according to the present invention, in a MOS transistor memory element having a floating gate, a bias control gate electrode for applying a bias potential and a pulse control gate electrode for applying a pulse voltage are connected to the floating gate. By injecting charge into the floating gate, it is possible to easily and efficiently adjust the amount of charge of the floating electrode easily and efficiently by applying a constant control voltage pulse by forming a stack on the floating gate. .

Therefore, if the analog memory element of the present invention is used for storing the synapse load in the synapse circuit of the neural network, a so-called learning function for gradually increasing or decreasing the synapse load and converging to the optimal synapse load can be easily performed by simple pulse control. This has the effect that a neurochip with learning ability can be made.

[Brief description of the drawings]

FIG. 1 is a diagram showing a basic structure of a floating gate type MOSFET of the present invention (first embodiment), FIG. 2 is a second embodiment of the floating gate type MOSFET of the present invention, and FIG. 3 is a floating gate of the present invention. FIG. 4 is a schematic diagram of a control circuit diagram of a MOSFET, FIG. 4 is a schematic diagram of a time change of an injected charge amount when a constant pulse is repeatedly applied to the floating gate of the present invention, and FIG. 5 is a structural diagram of a conventional floating gate type MOSFT. 6
The figure shows a schematic diagram of a time change of the injected charge amount when a constant pulse is repeatedly applied to the floating gate of the conventional structure. DESCRIPTION OF SYMBOLS 1 ... Floating gate 2 ... Control gate 3 ... Tunnel oxide film 4 ... Drain 5 ... Source 6 ... Bias control gate 7 ... Pulse control gate 8 ... Oxide film 9 ... High resistance layer 10 ... Drain current voltage measurement circuit 11 …… Gate bias voltage generation circuit

──────────────────────────────────────────────────続 き Continued on the front page (58) Fields surveyed (Int. Cl. ⁶ , DB name) H01L 27/115 H01L 21/8247 H01L 29/788

Claims (2)

(57) [Claims] In a MOS transistor memory device having a floating gate disposed via a tunnel junction with respect to a source and a drain, a bias control gate electrode for applying a bias potential and a pulse control gate electrode for applying a pulse voltage are provided. An analog memory element, which is formed by being stacked on the floating gate. 2. An analog memory device comprising a bias control gate electrode for applying a bias potential and a pulse control gate electrode for applying a pulse voltage formed on the floating gate, wherein a drain current or a voltage is set to a desired value. An analog memory element control circuit, characterized in that a gate bias generation circuit for maintaining a constant voltage is connected to a bias control gate, and a control pulse is applied to the pulse control gate.