JP2815042B2 - E4 signal CMI encoding output circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to an SDH (Synchr)
For example, a transmission output circuit that processes an on digital digital hierarchy (IOU-T Rec. G. FIG. 139.264 Mbps multiplexed on the STM-1 signal specified in 703
And an E4 signal CMI encoding output circuit that separates the E4 signal, performs CMI encoding, and outputs the result.

[0002]

2. Description of the Related Art Conventionally, an E4 signal CMI encoding output circuit of this kind has been used, for example, as shown in FIG. 2 for an E4 signal multiplexed on a VC-4 signal multiplexed on an STM-1 signal included in an SDH signal. The signal is written using the STM-1 signal clock signal and the E4 signal read clock signal 1
9, a control circuit 18 for monitoring a buffer address difference signal 17 indicating a difference between a write address and a read address of the buffer circuit 16 to generate a control signal, and a control for controlling a clock generation circuit. Circuit and a CMI controlled by the control signal.
A clock generation circuit 20 for generating the signal transmission clock signal 14 and the E4 signal read clock signal 19;
A CMI encoding circuit 15 converts the E4 signal multiplexed on the output from the buffer circuit 16 into a CMI code according to the MI signal sending clock signal 14 and outputs a CMI signal.

Among them, the clock generation circuit 20 is controlled by a control signal to generate a differential clock
A differential clock generation circuit (VOC) for generating a differential clock signal serving as the MI signal transmission clock signal 14, and doubling the period of the differential clock signal to E4
A 1/2 frequency divider circuit for generating the signal read clock signal 19 is provided.

Incidentally, as a well-known technique relating to the clock signal generated by the E4 signal CMI encoding output circuit, for example, a variable speed clock recovery circuit disclosed in Japanese Patent Application Laid-Open No. 2-166940, -92034
Clock recovery circuit disclosed in Japanese Patent Laid-Open No.
A clock reproducing apparatus disclosed in Japanese Patent No. 1398 is cited.

[0005]

The above-mentioned E4 signal CM
In the case of the I-coded output circuit, the short-period jitter generated when the E4 signal is multiplexed on the VC-4 signal and the long-period jitter generated when the VC-4 signal is multiplexed on the STM-1 signal are reduced by one. Since the buffer circuit is configured to absorb the short-period jitter in the CMI signal transmission clock signal, the long-period jitter remains, while the long-period jitter is mainly absorbed. In this case, short-period jitter remains.

SUMMARY OF THE INVENTION The present invention has been made to solve such a problem, and a technical problem of the present invention is to provide an E4 signal CMI encoding output circuit capable of reducing jitter remaining in a CMI signal transmission clock signal. Is to do.

[0007]

According to the present invention, an SDH is provided.
The VC-4 signal multiplexed on the STM-1 signal included in the signal is written using the STM-1 signal clock signal,
A pointer buffer circuit to be read by the read clock signal for the VC-4 signal, a pointer buffer address difference signal indicating a difference between a write address and a read address for the pointer buffer circuit, and a first byte indicated by a predetermined byte. A pointer / buffer control circuit for monitoring a first stuff signal including stuff information and generating a first control signal; and a VC-controller for generating a VC-4 signal read clock signal controlled by the first control signal. The read signal generation circuit for four signals and the E4 signal multiplexed on the output from the pointer buffer
A stuff buffer circuit to be written by the read clock signal for the C-4 signal and read by the read clock signal for the E4 signal; a stuff buffer address difference signal indicating a difference between a write address and a read address of the stuff buffer circuit; A stuff buffer control circuit for monitoring a second stuff signal including second stuff information indicated by a predetermined justification control bit to generate a second control signal, and controlled by the second control signal The E4 signal for mixing the output of the differential clock component and the output of the VC-4 signal read clock generation circuit to extract the 278.528 MHz component to generate a CMI signal transmission clock signal and an E4 signal read clock signal. Read clock generation circuit No E4 signal CMI coded output circuit is obtained.

According to the present invention, the E4 signal CMI
In the coded output circuit, the VC-4 signal read clock generation circuit includes a first difference clock signal generation circuit that generates a first difference clock signal based on a first control signal, and reads out the E4 signal. The clock generating circuit includes a second differential clock signal generating circuit that generates a second differential clock signal for performing mixing with the first differential clock signal as a differential clock component based on the second control signal. The provided E4 signal CMI encoding output circuit is obtained.

Further, according to the present invention, any one of the above E4
In the signal CMI encoding output circuit, a predetermined byte is A
U4, indicated by the H1 and H2 bytes of U-4,
The predetermined justification control bit is the E4 signal C included in the payload of the VC-4 signal.
An MI coded output circuit is obtained.

[0010]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Embodiments will be described below to explain the E4 signal CM of the present invention.
The I-coded output circuit will be described in detail with reference to the drawings.

FIG. 1 is a block diagram showing a basic configuration of an E4 signal CMI encoding output circuit according to an embodiment of the present invention. In this E4 signal CMI encoding output circuit, a VC-4 signal multiplexed on the STM-1 signal included in the SDH signal is written using a clock signal for the STM-1 signal, and a read clock signal for the VC-4 signal is written. 2
And a pointer buffer address difference signal 4 indicating a difference between a write address and a read address for the pointer buffer circuit 1 and H1, AU-4 of the AU-4 as a predetermined byte.
A pointer / buffer control circuit 3 for monitoring a first stuff signal 5 including first stuff information indicated by the H2 byte to generate a first control signal; and a VC-4 controlled by the first control signal. VC-4 signal read clock generation circuit 6 for generating a signal read clock signal
And are provided.

The E4 signal multiplexed on the output from the pointer buffer circuit 1 is written to the E4 signal CMI encoding output circuit by the VC-4 signal read clock signal 2, and the E4 signal read clock signal is written to the E4 signal CMI encoded output circuit. 8 and a stuff buffer circuit 7
A stuff buffer address difference signal 1 indicating the difference between the write address and the read address of the buffer circuit 7
A second control signal is generated by monitoring a second stuff signal 11 including second stuff information indicated by predetermined justification control bits included in the payload of the 0 and VC-4 signals. 278. Mixing the output of the differential clock component and the output of the VC-4 signal read clock generation circuit 6 under the control of the stuff buffer control circuit 9 and the second control signal;
An E4 signal read clock generation circuit 12 for extracting a 528 MHz component to generate a CMI signal transmission clock signal 14 and an E4 signal read clock signal 8, and a multiplexed E4 signal read as an output from the stuff buffer circuit 7 To a CMI code and outputs a CMI signal.

The VC-4 signal read clock generation circuit 6 includes a first differential clock signal generation circuit (VOC) for generating a first differential clock signal based on the first control signal, and a second differential clock signal generation circuit (VOC). A 1/2 frequency divider circuit for generating a VC-4 signal read clock signal 2 by doubling the cycle of one differential clock signal.

The E4 signal read clock generation circuit 12 supplies a second differential clock signal for performing mixing with the first differential clock signal as the above differential clock component based on the second control signal. Second generated
A differential clock signal generation circuit (VOC) 13, a multiplier as a mixing circuit for mixing the first differential clock signal and the second differential clock signal, and a differential clock signal that has been mixed (multiplied). And a filter circuit (FIL) for generating a CMI signal transmission clock signal 14 by filtering in the band of 1 and generating the E4 signal read clock signal 8 by doubling the cycle of the CMI signal transmission clock signal 14. / 2 frequency divider circuit.

The basic operation and function of each section in the E4 signal CMI encoding output circuit will be described below.

In the pointer buffer circuit 1, VC
When the −4 signal is written using the STM-1 signal clock signal, writing of the overhead portion other than the VC-4 signal of the STM-1 signal is prohibited. When multiplexing the VC-4 signal into the STM-1 signal, the pointer buffer circuit 1 uses H1, H2 of the AU-4 to absorb the deviation between the read clock signal 2 for the STM-1 signal and the VC-4 signal. Pointer justification processing is performed using bytes, but the technique here is $ ITU-
T Rec. G. FIG. 709} applies. V written into the pointer buffer circuit 1 by such pointer justification processing
When the C-4 signal is read by the smooth VC-4 signal read clock signal 2 generated by the VC-4 signal read clock generation circuit 6, jitter is removed. Incidentally, the first differential clock signal generation circuit (VCO) of the VC-4 signal read clock generation circuit 6 has a center frequency of 300.672 MHz.

Further, in the pointer / buffer control circuit 3, H1, H of the AU-4 are
The frequency of the VC-4 signal read clock signal 2 is predicted by monitoring 2 bytes to control the VC-4 signal read clock generation circuit 6, and the difference between the write address and the read address of the pointer buffer circuit 1 is determined. Is monitored from the pointer buffer address difference signal 4, when the pointer buffer circuit 1 is likely to overflow, the VC-4 signal read clock signal 2
Is increased, and when underflow is likely to occur, control is performed to decrease the frequency.

On the other hand, in the stuff buffer circuit 7, the E4 signal multiplexed on the VC-4 signal is
When writing by the signal read clock signal 2,
The overhead and fixed stuff bits of the VC-4 signal are write protected. When the E4 signal is multiplexed with the VC-4 signal, the stuff buffer circuit 7 uses a justification control bit to absorb a deviation between the E4 signal and the read clock signal 8 for the STM-1 signal. The processing is performed, and the technology here is also described in {ITU-T Rec. G. FIG. 70
What is disclosed in 9｝ applies. When the E4 signal written into the stuff buffer circuit 7 by such stuffing processing is read by the smooth E4 signal read clock signal 8 generated by the E4 signal read clock generation circuit 12, jitter is removed. Incidentally, the second read clock generation circuit 12 for the E4 signal
Has a center frequency of 22.144 MHz.

Further, the stuff buffer control circuit 7 monitors the justification control bit based on the second stuff signal 11, predicts the frequency of the E4 signal read clock signal 8, and generates the E4 signal read clock. The second difference clock generation circuit (VCO) 13 of the circuit 12 is controlled. As a result of monitoring the difference between the write address and the read address of the stuff buffer circuit 7 from the stuff buffer address difference signal 10, the stuff When the buffer circuit 7 is likely to overflow, control is performed such that the frequency of the read clock signal 8 for the E4 signal is increased, and when the buffer circuit 7 is likely to underflow, the frequency is decreased.

In addition, in the E4 signal read clock generation circuit 12, the first differential clock signal output from the VC-4 signal read clock generation circuit 6 and the second differential clock generation circuit (VCO) 13 generate the E4 signal. The second differential clock signal thus obtained is mixed with a multiplier, and a 278.528 MHz component is extracted by a filter circuit (FIL) to obtain a C
An MI signal transmission clock signal 14 is generated, and the CMI signal transmission clock signal 14 is frequency-divided by a 1/2 frequency divider circuit to generate a 139.264 MHz E4 signal read clock signal 8.

The E4 signal finally read from the stuff buffer circuit 7 is a CMI signal transmission clock signal 8 generated by the E4 signal read clock generation circuit 12.
Is converted by the CMI encoding circuit 15 in the CMI encoding circuit 15 and output from the CMI encoding circuit 15 as a CMI signal.

[0022]

As described above, according to the E4 signal CMI encoding output circuit of the present invention, the E4 signal is
A buffer circuit for independently absorbing the jitter generated when multiplexing the signal and the jitter generated when multiplexing the VC-4 signal into the STM-1 signal is provided to absorb each jitter. Therefore, the jitter remaining in the CMI signal transmission clock signal is sufficiently reduced.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a basic configuration of an E4 signal CMI encoding output circuit according to one embodiment of the present invention.

FIG. 2 is a block diagram showing a basic configuration of a conventional E4 signal CMI encoding output circuit.

[Explanation of symbols]

 REFERENCE SIGNS LIST 1 pointer buffer circuit 2 read clock signal for VC-4 signal 3 pointer buffer control circuit 4 address difference signal for pointer buffer 5 first stuff signal 6 read clock generation circuit for VC-4 signal 7 stuff buffer circuit 8 , 19 E4 signal read clock signal 9 Stuff buffer control circuit 10 Stuff buffer address difference signal 11 Second stuff signal 12 E4 signal read clock generation circuit 13 Difference clock generation circuit (VCO) 14 CMI signal transmission clock Signal 15 CMI encoding circuit 16 Buffer circuit 17 Buffer address difference signal 18 Control circuit 20 Clock generation circuit

Continuation of the front page (58) Field surveyed (Int.Cl. ⁶ , DB name) H04J 3/06 H04J 3/00 H04L 7/00 H04L 7/08 H04L 25/49

Claims (3)

(57) [Claims] 1. A pointer buffer circuit for writing a VC-4 signal multiplexed on an STM-1 signal included in an SDH signal by using a clock signal for the STM-1 signal and reading the VC-4 signal by a read clock signal for the VC-4 signal. Monitoring a pointer buffer address difference signal indicating a difference between a write address and a read address related to the pointer buffer circuit, and a first stuff signal including first stuff information indicated by a predetermined byte. A pointer buffer control circuit for generating one control signal, and the VC-4 controlled by the first control signal.
A read clock generation circuit for a VC-4 signal for generating a read clock signal for a signal; an E4 signal multiplexed on an output from the pointer buffer circuit is written by the read clock signal for the VC-4 signal; A stuff buffer circuit read by a read clock signal, a stuff buffer address difference signal indicating a difference between a write address and a read address of the stuff buffer circuit, and a second justification control bit. A stuff buffer control circuit for monitoring a second stuff signal including stuff information of the stuff buffer and generating a second control signal; an output of a differential clock component controlled by the second control signal; The output of the read clock generator for Packaging and CMI signaling clock signal by extracting a 278.528MHz component and the E
An E4 signal read clock generation circuit for generating a four-signal read clock signal.
Signal CMI encoding output circuit. 2. The E4 signal CMI encoding output circuit according to claim 1, wherein said VC-4 signal read clock generation circuit generates a first differential clock signal based on said first control signal. And a second differential clock signal for performing the mixing between the E4 signal read clock generating circuit and the first differential clock signal as the differential clock component. An E4 signal CMI encoding output circuit, comprising: a second differential clock signal generation circuit that generates based on the second control signal. 3. The E4 signal CMI encoding output circuit according to claim 1, wherein said predetermined bytes are indicated by H1 and H2 bytes of AU-4, and said predetermined justification control circuit is provided. An E4 signal CMI encoding output circuit, wherein bits are included in a payload of the VC-4 signal.