JP2817526B2 - Chip type electric double layer capacitor - Google Patents
Chip type electric double layer capacitorInfo
- Publication number
- JP2817526B2 JP2817526B2 JP20864592A JP20864592A JP2817526B2 JP 2817526 B2 JP2817526 B2 JP 2817526B2 JP 20864592 A JP20864592 A JP 20864592A JP 20864592 A JP20864592 A JP 20864592A JP 2817526 B2 JP2817526 B2 JP 2817526B2
- Authority
- JP
- Japan
- Prior art keywords
- electric double
- layer capacitor
- double layer
- electrode plate
- doughnut type
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
- 239000003990 capacitor Substances 0.000 title claims abstract description 35
- 229920005989 resin Polymers 0.000 claims abstract description 20
- 239000011347 resin Substances 0.000 claims abstract description 20
- OKTJSMMVPCPJKN-UHFFFAOYSA-N Carbon Chemical compound [C] OKTJSMMVPCPJKN-UHFFFAOYSA-N 0.000 claims abstract description 17
- 229910052799 carbon Inorganic materials 0.000 claims abstract description 12
- 235000012489 doughnuts Nutrition 0.000 claims abstract description 8
- 230000002093 peripheral effect Effects 0.000 claims abstract 3
- 238000000465 moulding Methods 0.000 abstract description 7
- 238000002347 injection Methods 0.000 abstract description 5
- 239000007924 injection Substances 0.000 abstract description 5
- 238000010030 laminating Methods 0.000 abstract 1
- 238000000034 method Methods 0.000 abstract 1
- 229910000679 solder Inorganic materials 0.000 description 4
- 229920005992 thermoplastic resin Polymers 0.000 description 4
- 238000007654 immersion Methods 0.000 description 3
- XEEYBQQBJWHFJM-UHFFFAOYSA-N Iron Chemical compound [Fe] XEEYBQQBJWHFJM-UHFFFAOYSA-N 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 239000008151 electrolyte solution Substances 0.000 description 2
- 239000012212 insulator Substances 0.000 description 2
- 229910000640 Fe alloy Inorganic materials 0.000 description 1
- 229910000990 Ni alloy Inorganic materials 0.000 description 1
- 239000011248 coating agent Substances 0.000 description 1
- 238000000576 coating method Methods 0.000 description 1
- 238000005336 cracking Methods 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 238000007598 dipping method Methods 0.000 description 1
- 239000011810 insulating material Substances 0.000 description 1
- -1 polyphenylene sulfur Polymers 0.000 description 1
Classifications
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02E—REDUCTION OF GREENHOUSE GAS [GHG] EMISSIONS, RELATED TO ENERGY GENERATION, TRANSMISSION OR DISTRIBUTION
- Y02E60/00—Enabling technologies; Technologies with a potential or indirect contribution to GHG emissions mitigation
- Y02E60/13—Energy storage using capacitors
Landscapes
- Electric Double-Layer Capacitors Or The Like (AREA)
Abstract
Description
【0001】[0001]
【産業上の利用分野】本発明は電気二重層コンデンサに
関し、特に表面実装に対応するチップ型電気二重層コン
デンサの素子積層体、及び上部電極板、下部電極板の構
造に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an electric double layer capacitor, and more particularly, to a structure of a chip type electric double layer capacitor for surface mounting and a structure of an upper electrode plate and a lower electrode plate.
【0002】[0002]
【従来の技術】近年、ヘッドホンステレオ、コードレス
電話等携帯用の電気機器の小形化・薄型化には著しいも
のがある。これらの電子機器に実装される電気二重層コ
ンデンサも他の電子部品と同様に小形化、薄型化し、さ
らには表面実装化への要求が頻繁化しつつある。従来、
この種の電気二重層コンデンサとしては、大容量のコン
デンサを得る手段の一つとして、米国特許第35369
63号明細書にて開示されているように、カーボン粉末
と電解液とを接触させて電気二重層を発生させることを
利用したものがある。図4は円筒型の電気二重層コンデ
ンサ素子(以下、素子と称す)の断面図である。図4に
おいて、5は電子伝導性でかつイオン不浸透性の導電性
セパレータ、7は粉末活性炭と電解質溶液からなるカー
ボンペースト電極、8はカーボンペースト電極間の導通
を防止するために設けたイオン透過性で、かつ非電子伝
導性を有する多孔性セパレータ、6はカーボンペースト
電極を保持し、かつ外界から遮断するために設けた非導
電性ガスケットである。2. Description of the Related Art In recent years, there has been a remarkable reduction in the size and thickness of portable electric devices such as headphone stereos and cordless telephones. Electric double-layer capacitors mounted on these electronic devices are becoming smaller and thinner like other electronic components, and demands for surface mounting are increasing. Conventionally,
As one of means for obtaining a large-capacity capacitor as this kind of electric double-layer capacitor, US Pat.
As disclosed in the specification of Japanese Patent No. 63, there is an apparatus utilizing the generation of an electric double layer by contacting carbon powder with an electrolytic solution. FIG. 4 is a cross-sectional view of a cylindrical electric double layer capacitor element (hereinafter, referred to as an element). In FIG. 4, 5 is a conductive separator that is both electron conductive and ion impervious, 7 is a carbon paste electrode made of powdered activated carbon and an electrolyte solution, and 8 is an ion permeation provided for preventing conduction between the carbon paste electrodes. A non-conductive gasket 6 is provided to hold the carbon paste electrode and to shield it from the outside world.
【0003】図5は従来のチップ型電気二重層コンデン
サの断面図である。図5において、1は絶縁性を有する
外装熱可塑性樹脂、2及び3はそれぞれリード端子部2
a及び3aを有する上部電極板と下部電極板、4aは素
子4を積層した素子積層体である。従来の電気二重層コ
ンデンサは素子積層体4aの上下面に、リード端子部2
aを有する上部電極板2、リード端子部3aを有する下
部電極板3をリード端子部が相対する方向に突出するよ
うに配置した状態でモールド成形金型にセットし、電極
板の上下方向に所定の圧力を加えた状態で、モールド成
形金型に熱可塑性樹脂等の絶縁樹脂を注入して成形を行
っていた。FIG. 5 is a sectional view of a conventional chip type electric double layer capacitor. In FIG. 5, reference numeral 1 denotes an exterior thermoplastic resin having an insulating property;
The upper and lower electrode plates having a and 3a are element stacks in which the element 4 is stacked. In the conventional electric double layer capacitor, the lead terminal 2 is provided on the upper and lower surfaces of the element laminate 4a.
The upper electrode plate 2 having a and the lower electrode plate 3 having the lead terminal portion 3a are set in a molding die in a state where the lead terminal portions are arranged to protrude in opposite directions, and a predetermined vertical direction of the electrode plate is set. Under such a pressure, an insulating resin such as a thermoplastic resin is injected into a mold for molding.
【0004】[0004]
【発明が解決しようとする課題】上述した従来の表面実
装型電気二重層コンデンサは、円筒型の素子積層体の上
下面に上部電極板、下部電極板をそれぞれ所定の位置に
配置し、上部電極板を介して素子積層体を加圧した状態
で熱可塑性樹脂にてモールド成形を行っていた。そのた
め半田ディップ槽内での230℃、10秒間浸漬等の高
温環境下において素子内残存空気や粉末活性炭が吸着し
ているガスが放出されることにより生じる素子の膨張ス
トレスにより外装絶縁樹脂に亀裂が入るという問題点が
あった。また前述したように電子部品の表面実装化に伴
い、部品自体の小形化、薄型化がはかられるようにな
り、ますますこの問題が大きくなる傾向にある。In the above-mentioned conventional surface mount type electric double layer capacitor, an upper electrode plate and a lower electrode plate are arranged at predetermined positions on the upper and lower surfaces of a cylindrical element laminate, respectively. Molding was performed with a thermoplastic resin while the element laminate was pressed through a plate. Therefore, under the high temperature environment such as immersion in a solder dip tank at 230 ° C. for 10 seconds, cracks are caused in the exterior insulating resin due to expansion stress of the element caused by release of gas remaining in the element and gas adsorbed by powdered activated carbon. There was a problem of entering. Also, as described above, with the surface mounting of electronic components, the size and thickness of the components themselves can be reduced, and this problem tends to increase.
【0005】本発明の目的は、半田ディップ槽内の高温
環境下においても素子の膨張ストレスにより外装絶縁樹
脂に亀裂が入ることがなく耐熱性に優れ、かつ小形なチ
ップ型電気二重層コンデンサを提供することにある。SUMMARY OF THE INVENTION An object of the present invention is to provide a small chip type electric double layer capacitor which is excellent in heat resistance without cracking of an exterior insulating resin due to expansion stress of an element even in a high temperature environment in a solder dipping bath. Is to do.
【0006】[0006]
【課題を解決するための手段】本発明の電気二重層コン
デンサは、電気二重層により静電容量を発現する電気二
重層コンデンサ素子を複数直列に積層して積層体とな
し、積層体の上下に各一つの電極板を配して、電極板の
外部との接続端子となるべき部分を残してモールド成形
により電気絶縁性樹脂で外装してなるチップ型電気二重
層コンデンサにおいて、前記電気二重層コンデンサ素子
を、非電子伝導性を有するドーナッツ状の多孔性セパレ
ータと、前記多孔性セパレータを挟んで上下に配置され
たドーナツ状のカーボンペースト電極と、前記カーボン
ペースト電極の外周部及び内周部にそれぞれ配置された
ドーナツ状の非伝導性ガスケットと、前記カーボンペー
スト電極の多孔性セパレータに対置する側に、前記外周
部の非導電性ガスケットと内周部の非導電性ガスケット
に懸かるように配置されたドーナッツ状の導電性セパレ
ータとで構成すると共に、前記電極板をドーナッツ状に
することにより、前記積層体と前記電極板を合せたもの
を、中心部に積層方向に通じる透孔を有する構造とし、
前記積層体及び電極板の中心部に存在する前記透孔内
に、前記外装の電気絶縁性樹脂と同一の樹脂を充填した
ことを特徴とする。 An electric double layer capacitor according to the present invention is an electric double layer capacitor which exhibits a capacitance by an electric double layer.
A multilayer body is formed by stacking multiple multilayer capacitor elements in series.
And placing one electrode plate on each of the upper and lower sides of the laminate,
Mold forming leaving the part to be the connection terminal with the outside
In the chip-type electric double layer capacitor formed by sheathed with electrically insulating resin by, the electric double layer capacitor element
Is a doughnut-shaped porous separator having non-electronic conductivity.
And the separators are arranged vertically with the porous separator interposed therebetween.
Donut-shaped carbon paste electrode, and the carbon
Placed on the outer and inner periphery of the paste electrode
A donut-shaped non-conductive gasket and the carbon paper
On the side of the strike electrode facing the porous separator,
Non-conductive gasket and inner non-conductive gasket
Donut-shaped conductive separator placed on top of
And the electrode plate is in a donut shape.
By combining the laminate and the electrode plate
Has a structure having a through hole in the center in the stacking direction,
In the through hole present at the center of the laminate and the electrode plate
Was filled with the same resin as the electrically insulating resin of the exterior.
It is characterized by the following.
【0007】[0007]
【実施例】次に、本発明について図面を参照して説明す
る。図1は本発明の第一の実施例の構成の説明図で
(a)は上面図、(b)は上面図(a)のA−A1 断面
図、(c)は右側面図(e)のB−B1 断面図、(d)
は下面図、(e)は右側面図、また図3は本発明の電気
二重層コンデンサ素子の構成を示す図で、(a)は下面
図(b)のC−C1 断面図、(b)は下面図である。Next, the present invention will be described with reference to the drawings. Figure 1 is a schematic view for illustrating a constitution of a first embodiment of the present invention (a) is a top view, (b) the A-A 1 cross-sectional view of a top view (a), (c) is a right side view (e ) BB 1 sectional view, (d)
Bottom view is, (e) is a right side view, and FIG. 3 is a diagram showing the structure of the electric double layer capacitor device of the present invention, C-C 1 section of (a) a lower surface <br/> view (b) FIG. 3B is a bottom view.
【0008】図1及び図3において、まず直径8.0m
m、厚さ1.1mmの素子4を2枚積層し、素子積層体
4aを得る。この素子積層体4aの中心部には直径2m
mの穴があけてある。素子積層体4aの上下面に中心部
に直径2mmの穴をあけた1辺が9.8mm厚さ0.2
mmの正方形で厚さ0.2mm、長さ3.0mmのリー
ド端子2a,3aを突出させ、鉄・ニッケル合金にはさ
んだメッキを施した1対の電極板2,3を配置する。電
極板2,3素子積層体4aの相対位置関係を維持するよ
うに配置し、固定した後、縦13mm,横12mm,厚
さ3.0mmの中空部を有するモールド金型にセット
し、電極板2,3を介して、上下各4個のピン(図示省
略)で素子積層体4aを無負荷時の約80%の厚さにな
るように圧縮させ、PPS(ポリフェニレンサルファル
ド)等の熱可塑性で高耐熱性の絶縁樹脂1を金型内の全
間隙へ、下部電極板3上部中央の絶縁樹脂注入ゲート1
cより注入し、成形する。絶縁樹脂注入ゲート1cは通
称ピンポイントゲートと呼ばれるもので、モールド成形
完了時点の金型が開く際に自動的に製品側の根本より切
断される。また上部電極板側穴部1a及び下部電極板側
穴部1bは前記金型ピンの跡である。素子積層体4aモ
ールド成形完了後も無負荷時の約80%の厚さに圧縮さ
れているため、等価直列抵抗が低いコンデンサとなる。
以上により、本発明の第1の実施例の電気二重層コンデ
ンサを得た。In FIGS. 1 and 3, first, the diameter is 8.0 m.
m, two elements 4 each having a thickness of 1.1 mm are stacked to obtain an element stack 4a. The central part of the element stack 4a has a diameter of 2 m.
There is a hole of m. One side having a hole of 2 mm in diameter at the center of the upper and lower surfaces of the element laminate 4a is 9.8 mm in thickness and 0.2 in thickness.
A pair of electrode plates 2 and 3 each of which is formed by projecting lead terminals 2a and 3a having a thickness of 0.2 mm and a length of 3.0 mm with a square of mm and protruding from an iron / nickel alloy. The electrode plates 2 and 3 are arranged so as to maintain the relative positional relationship between the element stacks 4a, fixed, and then set in a mold having a hollow portion having a length of 13 mm, a width of 12 mm and a thickness of 3.0 mm. The element stack 4a is compressed to a thickness of about 80% of the no-load state by four pins (not shown) through upper and lower pins 2 and 3, and the thermoplastic resin such as PPS (polyphenylene sulfur) is used. The insulating resin 1 having high heat resistance is injected into the entire gap in the mold, and the insulating resin injection gate 1 at the upper center of the lower electrode plate 3
Inject and mold from c. The insulating resin injection gate 1c is commonly called a pin point gate, and is automatically cut from the root of the product when the mold at the time of completion of molding is opened. The upper electrode plate side hole 1a and the lower electrode plate side hole 1b are traces of the mold pins. Even after the completion of the molding of the element laminate 4a, the capacitor is compressed to a thickness of about 80% at the time of no load, so that the capacitor has a low equivalent series resistance.
Thus, the electric double layer capacitor according to the first embodiment of the present invention was obtained.
【0009】図2は本発明の第2の実施例を説明するた
めの図面でそれぞれ第1の実施例の図1(b)及び図1
(c)に相当する断面図である。第1の実施例とは、下
部電極板3にかしめ率を一定にし、耐熱性向上のため設
けた絶縁剤塗布済みストッパー3b、上部終端電極板に
設けた絶縁剤塗布済み対ストッパー摩擦防止壁2bが存
在していることのみ異なる。FIG. 2 is a drawing for explaining a second embodiment of the present invention, and FIGS. 1 (b) and 1 (b) of the first embodiment respectively.
It is sectional drawing corresponding to (c). The first embodiment is different from the first embodiment in that the lower electrode plate 3 has a fixed caulking rate and is provided with an insulator-coated stopper 3b provided for improving heat resistance, and an insulator-coated stopper-provided anti-stopper friction preventing wall 2b provided on the upper terminal electrode plate. The only difference is that
【0010】次に、本発明の第1の実施例、第2の実施
例及び従来例のチップ型電気二重層コンデンサ各100
0個について、半田槽240℃、10秒浸漬試験を行い
クラックの発生率及び製品厚み増加率を測定し、その結
果を表1に示した。Next, each of the first and second embodiments of the present invention and the conventional chip type electric double layer capacitors 100 will be described.
For 0 pieces, a solder tank was subjected to a immersion test at 240 ° C. for 10 seconds to measure a crack generation rate and a product thickness increase rate, and the results are shown in Table 1.
【0011】 [0011]
【0012】表1の結果から明らかなように、本発明の
電気二重層コンデンサは耐熱性において従来例にくらべ
顕著な改善が認められる。As is apparent from the results shown in Table 1, the electric double layer capacitor of the present invention has a remarkable improvement in heat resistance as compared with the conventional example.
【0013】[0013]
【発明の効果】以上説明したように本発明は、素子中央
部に絶縁樹脂注入穴を設けたため、素子中央部に柱状絶
縁樹脂が形成され、リフロー炉内等の高温環境下での素
子の膨張ストレスに対し、膨張ストレスを分散させ、外
装樹脂表面に亀裂の入り難い、強じんな電気二重層コン
デンサが得られるという効果を有する。As described above, according to the present invention, since the insulating resin injection hole is provided in the central portion of the element, the columnar insulating resin is formed in the central portion of the element, and the expansion of the element in a high temperature environment such as in a reflow furnace. This has the effect of dispersing the expansion stress against the stress, and providing a tough electric double layer capacitor in which the surface of the exterior resin is less likely to crack.
【0014】本発明の第2の実施例では、図2に示すよ
うに、下部電極板及び上部電極板に絶縁剤を塗布したス
トッパー及び対ストッパ摩擦防止壁を設けた。そのた
め、本発明の第2の実施例の電気二重層コンデンサでは
本発明の第1の実施例の電気二重層コンデンサで得た半
田槽浸漬結果を上廻ることができた。また本発明の第2
の実施例ではストッパーの存在により、加圧治具により
加圧保持せずにモールド成形が行えるという効果を有す
る。In the second embodiment of the present invention, as shown in FIG. 2, the lower electrode plate and the upper electrode plate are provided with a stopper coated with an insulating material and a friction preventing wall against the stopper. Therefore, in the electric double layer capacitor of the second embodiment of the present invention, the result of immersion in the solder bath obtained by the electric double layer capacitor of the first embodiment of the present invention could be exceeded. The second aspect of the present invention
In the embodiment of the present invention, the presence of the stopper has an effect that the molding can be performed without pressing and holding by the pressing jig.
【図1】本発明の第1の実施例の図面で(a)は上面
図、(b)はA−A1 断面図、(c)はB−B1 断面
図、(d)は下面図、(e)は右側面図である。[1] In the drawings of the first embodiment of the present invention (a) is a top view, (b) the A-A 1 cross-sectional view, (c) the B-B 1 cross-sectional view, (d) is a bottom view (E) is a right side view.
【図2】本発明の第2の実施例の図面で(a)はA−A
1 断面図、(b)はB−B1 断面図である。FIG. 2A is a drawing of a second embodiment of the present invention, wherein FIG.
1 is a cross-sectional view, and (b) is a BB 1 cross-sectional view.
【図3】本発明によるチップ型電気二重層コンデンサの
素子の図面で、(a)はC−C1 断面図、(b)は下面
図である。[3] In the drawings of the elements of the chip-type electric double layer capacitor according to the present invention, (a) is C-C 1 cross-sectional view, (b) is a bottom <br/> view.
【図4】従来の電気二重層コンデンサ素子の断面図であ
る。FIG. 4 is a cross-sectional view of a conventional electric double layer capacitor element.
【図5】従来の電気二重層コンデンサのA−A1 断面図
である。5 is a A-A 1 cross-sectional view of a conventional electric double layer capacitor.
1 絶縁樹脂 1a 上部電極板側穴部 1b 下部電極板側穴部 1c 絶縁樹脂注入ゲート 2 上部電極板 2a 上部電極板のリード端子 2b 対ストッパー摩擦防止壁 3 下部電極板 3a 下部電極板のリード端子 3b ストッパー 4 素子 4a 素子積層体 5 導電性セパレータ 6 非導電性ガスケット 7 カーボンペースト電極 8 多孔性セパレータ 9 絶縁剤塗布膜 DESCRIPTION OF SYMBOLS 1 Insulating resin 1a Upper electrode plate side hole 1b Lower electrode plate side hole 1c Insulating resin injection gate 2 Upper electrode plate 2a Lead terminal of upper electrode plate 2b Anti-friction wall against stopper 3 Lower electrode plate 3a Lead terminal of lower electrode plate 3b stopper 4 element 4a element stack 5 conductive separator 6 non-conductive gasket 7 carbon paste electrode 8 porous separator 9 insulating coating film
フロントページの続き (58)調査した分野(Int.Cl.6,DB名) H01G 9/155 H01G 9/016 H01G 9/058Continuation of the front page (58) Field surveyed (Int.Cl. 6 , DB name) H01G 9/155 H01G 9/016 H01G 9/058
Claims (1)
気二重層コンデンサ素子を複数直列に積層して積層体と
なし、積層体の上下に各一つの電極板を配して、電極板
の外部との接続端子となるべき部分を残してモールド成
形により電気絶縁性樹脂で外装してなるチップ型電気二
重層コンデンサにおいて、前記電気二重層コンデンサ素子を、非電子伝導性を有す
るドーナッツ状の多孔性セパレータと、前記多孔性セパ
レータを挟んで上下に配置されたドーナツ状のカーボン
ペースト電極と、前記カーボンペースト電極の外周部及
び内周部にそれぞれ配置されたドーナツ状の非伝導性ガ
スケットと、前記カーボンペースト電極の多孔性セパレ
ータに対置する側に、前記外周部の非導電性ガスケット
と内周部の非導電性ガスケットに懸かるように配置され
たドーナッツ状の導電性セパレータとで構成すると共
に、前記電極板をドーナッツ状にすることにより、前記
積層体と前記電極板を合せたものを、中心部に積層方向
に通じる透孔を有する構造とし、 前記積層体及び電極板の中心部に存在する前記透孔内
に、前記外装の電気絶縁性樹脂と同一の樹脂を充填した
ことを特徴とするチップ型電気二重層コンデンサ。1. An electric double layer having an electrostatic capacity.
By stacking multiple air-double layer capacitor elements in series,
None, one electrode plate at the top and bottom of the laminate
Leave the part that should be the connection terminal with the outside of the mold
In a chip-type electric double-layer capacitor externally formed of an electrically insulating resin, the electric double-layer capacitor element has non-electronic conductivity.
Donut-shaped porous separator, and the porous separator
Donut-shaped carbon placed vertically above and below the radiator
A paste electrode and an outer peripheral portion of the carbon paste electrode;
Donut-shaped non-conductive gas
Sket and porous separator of the carbon paste electrode
The non-conductive gasket of the outer peripheral part
And arranged to hang on the non-conductive gasket on the inner circumference
And donut-shaped conductive separator
By making the electrode plate a donut shape,
The stack of the laminate and the electrode plate is placed in the center in the stacking direction.
A structure having a through-hole communicating with the inside of the laminate and the through-hole existing in the center of the electrode plate.
A chip-type electric double-layer capacitor , wherein the same resin as the outer insulating resin is filled .
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP20864592A JP2817526B2 (en) | 1992-08-05 | 1992-08-05 | Chip type electric double layer capacitor |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP20864592A JP2817526B2 (en) | 1992-08-05 | 1992-08-05 | Chip type electric double layer capacitor |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH0661096A JPH0661096A (en) | 1994-03-04 |
| JP2817526B2 true JP2817526B2 (en) | 1998-10-30 |
Family
ID=16559679
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP20864592A Expired - Lifetime JP2817526B2 (en) | 1992-08-05 | 1992-08-05 | Chip type electric double layer capacitor |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2817526B2 (en) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100603052B1 (en) * | 1999-03-11 | 2006-07-24 | (주)에스와이하이테크 | Manufacturing method of chip type electric double layer capacitor |
-
1992
- 1992-08-05 JP JP20864592A patent/JP2817526B2/en not_active Expired - Lifetime
Also Published As
| Publication number | Publication date |
|---|---|
| JPH0661096A (en) | 1994-03-04 |
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| Date | Code | Title | Description |
|---|---|---|---|
| A01 | Written decision to grant a patent or to grant a registration (utility model) |
Free format text: JAPANESE INTERMEDIATE CODE: A01 Effective date: 19980721 |