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JP2819282B2 - Semiconductor package and manufacturing method thereof - Google Patents
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JP2819282B2 - Semiconductor package and manufacturing method thereof - Google Patents

Semiconductor package and manufacturing method thereof

Info

Publication number
JP2819282B2
JP2819282B2 JP8342950A JP34295096A JP2819282B2 JP 2819282 B2 JP2819282 B2 JP 2819282B2 JP 8342950 A JP8342950 A JP 8342950A JP 34295096 A JP34295096 A JP 34295096A JP 2819282 B2 JP2819282 B2 JP 2819282B2
Authority
JP
Japan
Prior art keywords
package
package body
semiconductor chip
groove
lead
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
JP8342950A
Other languages
Japanese (ja)
Other versions
JPH09186273A (en
Inventor
ドン キム スン
Original Assignee
エルジー セミコン カンパニー リミテッド
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by エルジー セミコン カンパニー リミテッド filed Critical エルジー セミコン カンパニー リミテッド
Publication of JPH09186273A publication Critical patent/JPH09186273A/en
Application granted granted Critical
Publication of JP2819282B2 publication Critical patent/JP2819282B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W40/00Arrangements for thermal protection or thermal control
    • H10W40/01Manufacture or treatment
    • H10W40/03Manufacture or treatment of arrangements for cooling
    • H10W40/037Assembling together parts thereof
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W74/00Encapsulations, e.g. protective coatings
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W40/00Arrangements for thermal protection or thermal control
    • H10W40/10Arrangements for heating
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W40/00Arrangements for thermal protection or thermal control
    • H10W40/20Arrangements for cooling
    • H10W40/22Arrangements for cooling characterised by their shape, e.g. having conical or cylindrical projections
    • H10W40/226Arrangements for cooling characterised by their shape, e.g. having conical or cylindrical projections characterised by projecting parts, e.g. fins to increase surface area
    • H10W40/228Arrangements for cooling characterised by their shape, e.g. having conical or cylindrical projections characterised by projecting parts, e.g. fins to increase surface area the projecting parts being wire-shaped or pin-shaped
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/40Leadframes
    • H10W70/479Leadframes on or in insulating or insulated package substrates, interposers, or redistribution layers
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60Insulating or insulated package substrates; Interposers; Redistribution layers
    • H10W70/62Insulating or insulated package substrates; Interposers; Redistribution layers characterised by their interconnections
    • H10W70/65Shapes or dispositions of interconnections
    • H10W70/657Shapes or dispositions of interconnections on sidewalls or bottom surfaces of the package substrates, interposers or redistribution layers
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00Interconnections or connectors in packages
    • H10W72/50Bond wires
    • H10W72/541Dispositions of bond wires
    • H10W72/5449Dispositions of bond wires not being orthogonal to a side surface of the chip, e.g. fan-out arrangements
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00Interconnections or connectors in packages
    • H10W72/60Strap connectors, e.g. thick copper clips for grounding of power devices
    • H10W72/651Materials of strap connectors
    • H10W72/652Materials of strap connectors comprising metals or metalloids, e.g. silver
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00Package configurations
    • H10W90/701Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/751Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires
    • H10W90/754Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires between a chip and a stacked insulating package substrate, interposer or RDL
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00Package configurations
    • H10W90/701Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/751Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires
    • H10W90/756Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires between a chip and a stacked lead frame, conducting package substrate or heat sink

Landscapes

  • Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
  • Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)

Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【0001】[0001]

【発明の属する技術分野】本発明は、導体パッケージ
に係るもので、詳しくは、複数のリード樹脂成形体に
埋蔵された板状の半導体パッケージに関するものであ
る。
BACKGROUND OF THE INVENTION The present invention relates to a semi-conductor package, more particularly, to a plurality of semiconductor packages leads shaped plate which is buried in the resin molding.

【0002】[0002]

【従来の技術】従来、QFP(Quad Flat Package )半
導体パッケージにおいては、図4に示したように、イン
ナーリード1aとアウトリード1bとからなる複数のリ
ードフレーム1と、該リードフレーム1に囲まれた中央
部に配設されたパドル2と、該パドル2上に接着された
半導体チップ3と、該半導体チップ3上面に設けられた
複数の電極と前記各インナーリード1aとをそれぞれ連
結する金属ワイヤー4と、前記インナーリード1a、パ
ドル2、半導体チップ3および金属ワイヤー4をモール
ドする樹脂製の成形体5とから構成されている。
2. Description of the Related Art Conventionally, in a QFP (Quad Flat Package) semiconductor package, as shown in FIG. 4, a plurality of lead frames 1 each having an inner lead 1a and an out lead 1b are surrounded by the lead frame 1. A paddle 2 disposed at a central portion, a semiconductor chip 3 adhered on the paddle 2, a plurality of electrodes provided on the upper surface of the semiconductor chip 3, and metal wires connecting the inner leads 1a, respectively. 4 and a resin molded body 5 for molding the inner lead 1 a, the paddle 2, the semiconductor chip 3 and the metal wire 4.

【0003】そして、このような従来のQFP半導体パ
ッケージの製造方法においては、(1) リードフレーム1
およびパドル2を供給する工程と、(2) パドル2上に半
導体チップ3を接着する工程と、(3) 該半導体チップ3
上面に設けられた電極とリードフレーム1のインナーリ
ード1aとを金属ワイヤ4によりボンディングする工
程と、(4) インナーリード1a、パドル2、半導体チッ
プ3および金属ワイヤ4を、樹脂により密閉して成形
体5を形成する工程と、(5) 成形体5をトリミング(tr
iming )およびフォーミング(forming )する工程と、
を順次施していた。
In such a conventional method of manufacturing a QFP semiconductor package, (1) lead frame 1
And (2) bonding the semiconductor chip 3 on the paddle 2, and (3) bonding the semiconductor chip 3 to the paddle 2.
A step of the electrode and that is provided and the inner lead 1a of the lead frame 1 are bonded by a metal wire - 4 on the upper surface, (4) the inner lead 1a, paddle 2, the semiconductor chip 3 and the metal wire over 4, sealed by a resin (5) trimming the molded body 5 (tr
iming) and forming steps;
Was sequentially applied.

【0004】[0004]

【発明が解決しようとする課題】しかしながら、このよ
うな従来のQFP半導体パッケージおよびその製造方法
においては、樹脂成形の工程で、施行中の圧力によりパ
ドルの位置が崩れて不良品が発生するおそれがあるとい
う不都合な点があった。また、成形体の外部にアウトリ
ードが突成されているため、外部の衝撃により該リード
の撓み現象が発生するおそれがあり、このようなアウト
リードを印刷回路基板上に実装するときの整合が難し
く、極めて煩雑であるという不都合な点もあった。
However, in such a conventional QFP semiconductor package and a method of manufacturing the same, in the resin molding process, there is a possibility that the position of the paddle may be distorted due to the pressure during the operation and defective products may be generated. There was an inconvenience that there was. In addition, since the outlead is formed outside the molded body, there is a possibility that the lead may be bent due to an external impact, and the alignment when mounting such an outlead on a printed circuit board may be reduced. There was an inconvenience that it was difficult and extremely complicated.

【0005】さらに、印刷回路基板上に半導体パッケー
ジを実装した後、電力が供給されて半導体チップが動作
する過程において、半導体パッケージの温度が上昇して
もその高温の熱が速やかに外部に放出されず、動作エラ
ーが発生するおそれがあるという不都合な点もあった。
本発明は、このような従来の問題点に鑑み、印刷回路基
板上に簡便に実装することができ、動作中に発生する熱
を外部に速やかに放出する導体パッケージを安価に提
供することを目的とする。
Furthermore, after the semiconductor package is mounted on the printed circuit board, in the process of supplying power and operating the semiconductor chip, even if the temperature of the semiconductor package rises, the high-temperature heat is quickly released to the outside. However, there is also an inconvenience that an operation error may occur.
The present invention, such view of the conventional problems, can be conveniently mounted on a printed circuit board, to provide an inexpensive semi-conductor package to quickly dissipate heat generated during operation to the outside Aim.

【0006】[0006]

【課題を解決するための手段】このため、請求項1に係
る発明では、脂製のパッケージ本体と、該パッケージ
本体の内部に埋設され、前記パッケージ本体の上下両面
および外周縁部に表面が露出された複数のリードと、前
記パッケージ本体中央部位を貫通させて埋設された板状
の金属性熱放出部と、前記パッケージ本体上面中央所定
部位に所定深さを有して形成された溝部と、該溝部内の
前記熱放出部表面に接着された半導体チップと、該半導
体チップ上面に設けられた複数の電極と前記各リードと
を夫々連結する金属ワイヤーと、前記溝部内に配設され
た前記半導体チップ、各リードおよび金属ワイヤーを密
封するエポキシモールディングコンパウンドと、を備え
た半導体パッケージを構成する。
A solution for the] Therefore, in the invention according to claim 1, the package body made of tree butter, is embedded in the said package body, the upper and lower surfaces of the package body
A plurality of leads whose surfaces are exposed at the outer peripheral edge, a plate-shaped metallic heat-emitting portion embedded through the central portion of the package main body, and a predetermined central portion at the center of the upper surface of the package main body. A groove formed to have a depth, a semiconductor chip adhered to the surface of the heat emitting portion in the groove, and a plurality of electrodes provided on the upper surface of the semiconductor chip and a metal for connecting each of the leads. A semiconductor package includes a wire, and an epoxy molding compound that seals the semiconductor chip, each lead, and the metal wire disposed in the groove.

【0007】このような構成では、半導体チップが実装
される金属性熱放出部とリードとの位置関係は常に一定
に保たれ、動作中に発生する熱も金属性熱放出部を介し
て速やかに放散される。また、複数のリードが、前記パ
ッケージ本体の内部に埋設され、前記パッケージ本体の
上下両面および外周縁部に表面が露出される構成とすれ
ば、露出されたいずれの部位からでも信号の入出力がで
きる。このような半導体パッケージは、請求項に係る
発明のように、角柱状の金属性熱放出部材と、該金属性
熱放出部材の周囲に略平行に配設した複数の柱状リード
部材とを、該リード部材の側部が露出するように樹脂で
固めて一体とした柱状パッケージ材料を形成する第1工
程と、該形成された柱状パッケージ材料を所定厚さに切
断し、金属性熱放出部および複数のリードの埋設された
パッケージ本体を形成する第2工程と、該切断形成され
たパッケージ本体上面中央所定部位を切削して所定深さ
の溝部を形成する第3工程と、該溝部内に露出した金属
熱放出部上面に半導体チップを接着し、該半導体チッ
プ上面に設けられた複数の電極と各リードとを夫々金属
ワイヤーにより連結する第4工程と、前記半導体チッ
プ、各リード、および金属ワイヤーをエポキシモールデ
ィングコンパウンドにより密封する第5工程とを順次行
うことにより製造すれば、量産が容易である。
In such a configuration, the positional relationship between the metallic heat emitting portion on which the semiconductor chip is mounted and the leads is always kept constant, and the heat generated during operation is also quickly transmitted via the metallic heat emitting portion. Dissipated. Also, a plurality of leads are
Embedded in the package body,
The surface is exposed on both the upper and lower surfaces and the outer edge.
Signal input and output from any exposed part
Wear. Such a semiconductor package includes a prismatic metallic heat emitting member and a plurality of columnar lead members disposed substantially in parallel around the metallic heat emitting member, as in the invention according to claim 6 . A first step of forming an integrated columnar package material by solidifying with resin so that the side portions of the lead members are exposed; cutting the formed columnar package material to a predetermined thickness to form a metallic heat emitting portion; A second step of forming a package body in which a plurality of leads are embedded, a third step of cutting a predetermined portion of the cut upper surface of the package body upper surface to form a groove having a predetermined depth, and exposing the groove in the groove. Metal
Bonding the semiconductor chip to the sexual heat emitting portion upper surface, and a fourth step of connecting a plurality of electrodes and the lead and the respective metal wires provided on the semiconductor chip upper surface, said semiconductor chip, the leads, and the metallic wire If it is manufactured by sequentially performing the fifth step of sealing with an epoxy molding compound, mass production is easy.

【0008】また、請求項2に係る発明のように、蓋体
で前記パッケージ本体上面を覆い前記溝部を密封する構
成とすれば、半導体パッケージ上面の強度を向上でき
この場合、蓋体は、請求項3に係る発明のように、
前記パッケージ本体の厚さよりも薄く形成すれば、半導
体パッケージ上面からの熱の放散が容易になる。そし
て、このような蓋体を用いた半導体パッケージは、請求
に係る発明のように、角柱状の金属性熱放出部材
と、該金属性熱放出部材の周囲に略平行に配設した複数
の柱状リード部材とを、該リード部材の側部が露出する
ように樹脂で固めて一体とした柱状パッケージ材料を形
成する第1工程と、該形成された柱状パッケージ材料を
所定厚さに切断し、金属性熱放出部および複数のリード
の埋設されたパッケージ本体を形成する第2工程と、該
切断形成されたパッケージ本体上面中央所定部位を切削
して所定深さの溝部を形成する第3工程と、該溝部内に
露出した金属性熱放出部上面に半導体チップを接着し、
該半導体チップ上面に設けられた複数の電極と各リード
とを夫々金属ワイヤーにより連結する第4工程と、前記
パッケージ本体上面を蓋体で覆い前記溝部を密封する第
5工程とを順次行うことにより製造できる。
According to the second aspect of the present invention, the strength of the upper surface of the semiconductor package can be improved by covering the upper surface of the package body with a lid and sealing the groove . In this case, as in the invention according to claim 3,
If the thickness is smaller than the thickness of the package body, heat can be easily dissipated from the upper surface of the semiconductor package. The semiconductor package using such a lid is, as in the invention according to claim 7 , a prismatic metallic heat emitting member and a plurality of metal heat emitting members arranged substantially in parallel around the metallic heat emitting member. A first step of solidifying the columnar lead member with a resin so that the side portions of the lead member are exposed to form an integrated columnar package material; and cutting the formed columnar package material to a predetermined thickness. A second step of forming a package body in which a metallic heat emitting portion and a plurality of leads are embedded, and a third step of forming a groove having a predetermined depth by cutting a predetermined central portion of the cut upper surface of the package body. And, a semiconductor chip is bonded to the upper surface of the metallic heat emitting portion exposed in the groove,
By sequentially performing a fourth step of connecting a plurality of electrodes provided on the upper surface of the semiconductor chip and each lead by a metal wire, and a fifth step of covering the upper surface of the package body with a lid and sealing the groove. Can be manufactured.

【0009】このとき、前記蓋体は、請求項に係る発
明のように、前記柱状パッケージ材料を所定厚さに切断
して形成すれば、パッケージ本体の上面を過不足なく覆
うことのできるものを容易かつ安価に製造することがで
きる。前記パッケージ本体の形状は任意であるが、請求
項4に係る発明のように長方形の板状とするか、請求項
5に係る発明のように円板状とすれば、半導体チップ上
面に設けられた複数の電極と各リードとの間の金属ワイ
ヤーによる高密度な連結が容易になる。
At this time, if the lid is formed by cutting the columnar package material to a predetermined thickness as in the invention according to claim 8 , the lid can cover the upper surface of the package body without excess or shortage. Can be easily and inexpensively manufactured. The shape of the package body is arbitrary, but if it is a rectangular plate as in the invention according to claim 4 or a disk as in the invention according to claim 5, it is provided on the upper surface of the semiconductor chip. Further, high-density connection between the plurality of electrodes and each lead by a metal wire is facilitated.

【0010】[0010]

【発明の実施の形態】以下に、本発明の実施の形態につ
いて図面を用いて説明する。本発明に係る導体パッケ
ージにおいては、図3に示したように、樹脂製(例えば
エポキシ樹脂)のパッケージ本体11aと、該パッケー
ジ本体11aの内部に埋設され、前記パッケージ本体1
1aの上下両面および外周縁部に表面が露出された複数
のリード12と、前記パッケージ本体11a中央部位を
貫通させて埋設された板状の金属性熱放出部13と、前
記パッケージ本体11a上面中央所定部位に所定深さを
有して形成された溝部14と、該溝部14内の前記金属
熱放出部13表面に接着された半導体チップ15と、
該半導体チップ15上面に設けられた複数の電極と前記
各リード12とを夫々連結する金属ワイヤー16と、前
記溝部14内に配設された前記半導体チップ15、各リ
ード12および金属ワイヤー16を密封するエポキシモ
ールディングコンパウンド17とを備えている。
Embodiments of the present invention will be described below with reference to the drawings. In the semi-conductor package according to the present invention, as shown in FIG. 3, is embedded with the package body 11a made of resin (e.g., epoxy resin), the interior of the package body 11a, the package body 1
A plurality of leads 12 whose surfaces are exposed on both upper and lower surfaces and an outer peripheral edge of 1a; a plate-like metallic heat emitting portion 13 buried by penetrating a central portion of the package main body 11a; A groove 14 formed at a predetermined position with a predetermined depth, and the metal in the groove 14
A semiconductor chip 15 adhered to the surface of the conductive heat emitting portion 13;
A metal wire 16 for connecting a plurality of electrodes provided on the upper surface of the semiconductor chip 15 to the respective leads 12, and a semiconductor chip 15, each lead 12 and the metal wire 16 disposed in the groove 14 are sealed. And an epoxy molding compound 17 .

【0011】このような構成の半導体パッケージでは、
動作中に発生する熱も金属性熱放出部13を介して速や
かに放散されるため、パッケージ内の温度上昇も抑制す
ることができる。また、リード12はパッケージ本体1
1aの内部に埋設されているため、外部からの衝撃等で
変形することはない。また、リード12はパッケージ本
体11aの上下両面および側面の外周縁部に露出してい
るため、これらのいずれからでも信号の入出力が可能で
あり、印刷回路基板等へは、さまざまな形態で実装する
ことができる。
In the semiconductor package having such a configuration,
Since the heat generated during the operation is also quickly dissipated through the metallic heat emitting portion 13, a rise in the temperature inside the package can be suppressed. The lead 12 is the package body 1
Since it is buried inside 1a, it is not deformed by an external impact or the like. Further, since the leads 12 are exposed on the upper and lower surfaces and the outer peripheral edges of the side surfaces of the package body 11a, signals can be input / output from any of these, and the leads 12 can be mounted in various forms on a printed circuit board or the like. can do.

【0012】また、図3に示したように、前記エポキシ
モールディングコンパウンド17の代わりに、前記パッ
ケージ本体11a上面の前記溝部14上を覆う蓋体11
bを接着して使用することもできる。このようにすれ
ば、半導体パッケージの上面の強度が向上し、より高い
耐久性を得ることができる。次に、上述のような構成の
本発明に係る半導体パッケージの製造方法を説明する。
As shown in FIG. 3, instead of the epoxy molding compound 17, a lid 11 covering the groove 14 on the upper surface of the package body 11a.
b can also be used by bonding. With this configuration, the strength of the upper surface of the semiconductor package is improved, and higher durability can be obtained. Next, a method of manufacturing a semiconductor package having the above-described configuration according to the present invention will be described.

【0013】先ず、図1(A)に示したように、厚さd
(1〜2mm)、幅W、および長さLを有する複数の柱
状リード部材9を、角柱状の金属性熱放出部材8の周囲
に略平行に配設し、これらを柱状リード部材9の側部が
露出するように樹脂で固めて一体として、柱状パッケー
ジ材料10を形成する。ここで、柱状リード部材9およ
び金属性熱放出部材8は、Cu、Al等の導電性金属で
形成されたものである。
First, as shown in FIG.
A plurality of columnar lead members 9 having a width (1 to 2 mm), a width W, and a length L are arranged substantially in parallel around a prismatic metallic heat emitting member 8, and these are arranged on the side of the columnar lead member 9. The columnar package material 10 is formed integrally with a resin so that the portions are exposed. Here, the columnar lead member 9 and the metallic heat emitting member 8 are formed of a conductive metal such as Cu or Al.

【0014】その後、成形された柱状パッケージ材料1
0を、所定厚さを有するように順次切断し、図1(B)
に示したように、金属性熱放出部13および複数のリー
ド12が夫々埋設されたパッケージ本体11aを形成す
る。次いで、図1(C)に示したように、パッケージ本
体11aの上面中央部位を所定大きさおよび所定深さを
有するように研磨又はポリッシングを施して溝部14を
形成する。
Thereafter, the molded columnar package material 1
0 is sequentially cut so as to have a predetermined thickness, and FIG.
As shown in (1), the package body 11a in which the metallic heat emitting portion 13 and the plurality of leads 12 are respectively buried is formed. Next, as shown in FIG. 1C, a groove 14 is formed by polishing or polishing the central portion of the upper surface of the package body 11a so as to have a predetermined size and a predetermined depth.

【0015】その後、図1(D)に示したように、該溝
部14の中央に露出された金属性熱放出部13上面に半
導体チップ15を接着し、該半導体チップ15上面と各
リード12上面とを夫々金属ワイヤー16により連結す
る。次いで、図2に示したように、前記溝部14内に配
設された半導体チップ15、各リード12および金属ワ
イヤ16の上面をエポキシモールディングコンパウン
ド17により密封して、本発明に係る半導体パッケージ
の製造を終了する。
Thereafter, as shown in FIG. 1D, a semiconductor chip 15 is bonded to the upper surface of the metallic heat emitting portion 13 exposed at the center of the groove 14, and the upper surface of the semiconductor chip 15 and the upper surface of each lead 12 are bonded. Are connected by a metal wire 16 respectively. Then, as shown in FIG. 2, the semiconductor chips 15 disposed in the groove 14, the upper surface of each lead 12 and the metal follower <br/> ear over 16 sealed by epoxy molding compound 17, the present invention Of the semiconductor package according to the above is terminated.

【0016】このようにすれば、品質の一様な半導体パ
ッケージを安価に量産することができる。また、エポキ
シモールディングコンパウンド17による封止の際に、
その圧力で半導体チップ15や金属性熱放出部13の位
置がずれることはなく、半導体チップ15が実装される
金属性熱放出部13とリード12との位置関係は常に一
定に保たれるため、製造工程において金属ワイヤー16
の断線等が生じ難い。
In this manner, semiconductor packages of uniform quality can be mass-produced at low cost. Also, at the time of sealing with the epoxy molding compound 17,
The pressure does not cause the positions of the semiconductor chip 15 and the metallic heat emitting portion 13 to shift, and the positional relationship between the metallic heat emitting portion 13 on which the semiconductor chip 15 is mounted and the lead 12 is always kept constant. In the manufacturing process, the metal wire 16
Disconnection is unlikely to occur.

【0017】上述した製造方法のうち、エポキシモール
ディングコンパウンド17による封止工程の代わりに、
板状の蓋体で封止するようにしてもよい。例えば図3に
示したように、前記柱状パッケージ材料10を所定厚さ
に切断して蓋体11bを形成し、前記半導体チップ1
5、各リード12および金属ワイヤー16が配設された
溝部14を密封するように、パッケージ本体11a上面
を蓋体11bで覆って接着を施してもよい。このように
すれば、パッケージ本体11aの上面を過不足なく覆う
ことのできるものを容易かつ安価に製造することがで
、蓋体11bの外縁部に設けられたリードが、パッケ
ージ本体11aのリード12と導通するため、蓋体11
b上面からも信号の入出力が可能になり、印刷回路基板
等への実装方法の自由度が拡大する。
In the manufacturing method described above, instead of the sealing step using the epoxy molding compound 17,
You may make it seal with a plate-shaped lid. For example, as shown in FIG. 3, the columnar package material 10 is cut to a predetermined thickness to form a lid 11b, and the semiconductor chip 1
5. The top surface of the package body 11a may be covered with a lid 11b and sealed so as to seal the grooves 14 in which the leads 12 and the metal wires 16 are provided. In this way, it is possible to easily and inexpensively manufacture a package that can cover the upper surface of the package body 11a without excess or shortage.
The lead provided on the outer edge of the lid 11b is electrically connected to the lead 12 of the package body 11a.
(b) Signals can be input and output also from the upper surface, and the degree of freedom of the mounting method on a printed circuit board or the like is expanded.

【0018】また、蓋体11bを、パッケージ本体11
aよりも強度上問題ない程度に薄く形成すれば、動作中
の熱の放散を促進することができる。尚、パッケージ本
体の形状は特に限定されないが、長方形の板状や円板状
であれば、長方形板状の半導体チップ上面に形成された
電極とパッケージ本体周縁部に埋設されたリードとの間
のワイヤボンドを高密度に行うのに適している。
The lid 11b is attached to the package body 11
When formed to a thickness that is not problematic in strength than a, heat dissipation during operation can be promoted. Although the shape of the package body is not particularly limited, if the shape is a rectangular plate or a disk, the space between the electrode formed on the upper surface of the rectangular plate-shaped semiconductor chip and the lead embedded in the peripheral portion of the package body is provided. Suitable for performing high density wire bonding.

【0019】また、上述の例では、柱状パッケージ材料
10を直方体に製造したが、必要に応じて、円柱状又は
所望の形状に製造することで、意図した形状のパッケー
ジを容易に量産することができる。また、樹脂に代えて
セラミック等の絶縁物質でパッケージを形成してもよ
い。
Further, in the above-described example, the columnar package material 10 is manufactured in a rectangular parallelepiped. However, by manufacturing the columnar package material 10 into a columnar shape or a desired shape as needed, a package having an intended shape can be easily mass-produced. it can. Alternatively, the package may be formed of an insulating material such as ceramic instead of resin.

【0020】[0020]

【発明の効果】以上説明したように、請求項1に係る発
明によれば、外力等によるリードの変形がおき難く、高
い耐久性を有する半導体パッケージを得ることができる
という効果がある。また、複数のリードの表面が、半導
体パッケージ本体の上下両面および外周縁部に露出され
ているため、このうちのいずれからでも信号の入出力が
でき、印刷回路基板等への実装方法に広い自由度を与え
ることができるという効果がある。また、動作中の熱を
半導体パッケージから効率的に放散することができるた
め、動作エラーの発生を可及的に防止できるという効果
がある。
As described above, according to the first aspect of the present invention, there is an effect that a lead is hardly deformed by external force or the like, and a semiconductor package having high durability can be obtained. In addition, the surface of multiple leads
Exposed on both upper and lower surfaces and outer edge of body package body
Signal input and output from any of these
It gives a wide degree of freedom to the mounting method on printed circuit boards, etc.
There is an effect that can be. In addition, since heat during operation can be efficiently dissipated from the semiconductor package, an operation error can be prevented as much as possible.

【0021】また、請求項2に係る発明によれば、半導
体パッケージ上面の強度を向上させて、より高い耐久性
を得ることができるという効果がある。また、請求項3
に係る発明によれば、蓋体を薄く形成することにより半
導体パッケージ上面からの熱の放散を促進することがで
きるという効果がある。また、請求項4および請求項5
に係る発明によれば、導体チップ上面に設けられた複
数の電極と、パッケージ本体の周縁部に設けられた各リ
ードとの間の金属ワイヤーによる高密度な連結が容易に
なるという効果がある。
Further, according to the second aspect of the invention, there is an effect that the strength of the upper surface of the semiconductor package can be improved and higher durability can be obtained. Claim 3
According to the invention, heat dissipation from the upper surface of the semiconductor package can be promoted by forming the lid thin. Claims 4 and 5
According to the invention, there is an effect that a plurality of electrodes provided on a semi-conductor chip top surface, high density connection by metal wires between the leads provided on the peripheral portion of the package body is facilitated .

【0022】た、請求項および請求項に係る発明
によれば、製造工程が極めて簡単で量産が容易であるた
め、生産性が向上し原価が低廉になるという効果があ
る。また、製造工程において金属ワイヤーの断線等が生
じ難く、歩留まりが向上するという効果もある。
[0022] Also, the invention according to claim 6 and claim 7, since the manufacturing process is facilitated very simple and mass production, there is an effect that cost increase productivity becomes inexpensive. In addition, there is also an effect that the breaking of the metal wire hardly occurs in the manufacturing process, and the yield is improved.

【0023】また、請求項に係る発明によれば、パッ
ケージ本体を過不足なく覆う蓋体を安価かつ容易に製造
することができるという効果がある。また、この蓋体の
周縁部に設けられたリードからも信号の入出力ができる
という効果もある。
According to the eighth aspect of the present invention, there is an effect that a lid that covers the package body without excess or shortage can be manufactured at low cost and easily. In addition, there is an effect that signals can be input and output also from leads provided on the peripheral portion of the lid.

【図面の簡単な説明】[Brief description of the drawings]

【図1】 (A)〜(D)本発明に係る導体パッケー
ジおよびその製造方法を示した工程図
[1] (A) ~ (D) step view illustrating a semi-conductor package and a manufacturing method thereof according to the present invention

【図2】 本発明に係る導体パッケージの実施形態を
説明する斜視図
Perspective view illustrating the embodiment of a semi-conductor package according to the present invention; FIG

【図3】 本発明に係る導体パッケージの他の実施形
態を説明する斜視図
Figure 3 is a perspective view illustrating another embodiment of a semi-conductor package according to the present invention

【図4】 従来のQFP半導体パッケージの構造を説明
する断面図
FIG. 4 is a cross-sectional view illustrating the structure of a conventional QFP semiconductor package.

【符号の説明】[Explanation of symbols]

8 金属性熱放出部材 9 柱状リード部材 10 柱状パッケージ材料 11a パッケージ本体 11b 蓋体 12 リード 13 金属熱放出部 14 溝部 15 半導体チップ 16 金属ワイヤー8 metallic heat dissipation member 9 columnar lead member 10 columnar packaging material 11a package body 11b lid 12 leads 13 metal heat sink 14 groove 15 semiconductor chip 16 metal wires

───────────────────────────────────────────────────── フロントページの続き (58)調査した分野(Int.Cl.6,DB名) H01L 23/34 - 23/473 H01L 23/28 - 23/30 H01L 21/56 H01L 23/12──────────────────────────────────────────────────続 き Continued on the front page (58) Field surveyed (Int.Cl. 6 , DB name) H01L 23/34-23/473 H01L 23/28-23/30 H01L 21/56 H01L 23/12

Claims (8)

(57)【特許請求の範囲】(57) [Claims] 【請求項1】脂製のパッケージ本体(11a)と、 該パッケージ本体(11a)の内部に埋設され、前記パ
ッケージ本体(11a)の上下両面および外周縁部に
面が露出された複数のリード(12)と、 前記パッケージ本体(11a)中央部位を貫通させて埋
設された板状の金属性熱放出部(13)と、 前記パッケージ本体(11a)上面中央所定部位に所定
深さを有して形成された溝部(14)と、 該溝部(14)内の前記金属性熱放出部(13)表面に
接着された半導体チップ(15)と、 該半導体チップ(15)上面に設けられた複数の電極と
前記各リード(12)とを夫々連結する金属ワイヤー
(16)と、 前記溝部(14)内に配設された前記半導体チップ(1
5)、各リード(12)および金属ワイヤー(16)を
密封するエポキシモールディングコンパウンド(17)
と、 を備えた半導体パッケージ。
[Claim 1] A tree fat made of the package body (11a), embedded in the interior of the package body (11a), said path
A plurality of leads (12) having exposed surfaces on both upper and lower surfaces and an outer peripheral edge of the package body (11a); and a plate-like metal buried through a central portion of the package body (11a). A heat release portion (13), a groove (14) formed at a predetermined position in the center of the upper surface of the package body (11a) with a predetermined depth, and the metal heat release portion ( 13) a semiconductor chip (15) adhered to the surface, a metal wire (16) for connecting a plurality of electrodes provided on the upper surface of the semiconductor chip (15) with the leads (12), respectively; 14), the semiconductor chip (1)
5) Epoxy molding compound (17) for sealing each lead (12) and metal wire (16)
And a semiconductor package comprising:
【請求項2】脂製のパッケージ本体(11a)と、 該パッケージ本体(11a)の内部に埋設され、前記パ
ッケージ本体(11a)の上下両面および外周縁部に
面が露出された複数のリード(12)と、 前記パッケージ本体(11a)中央部位を貫通させて埋
設された板状の金属性熱放出部(13)と、 前記パッケージ本体(11a)上面中央所定部位に所定
深さを有して形成された溝部(14)と、 該溝部(14)内の前記金属性熱放出部(13)表面に
接着された半導体チップ(15)と、 該半導体チップ(15)上面に設けられた複数の電極と
前記各リード(12)とを夫々連結する金属ワイヤー
(16)と、 前記パッケージ本体(11a)上面を覆い前記溝部(1
4)を密封する蓋体(11b)と、 を備えた半導体パッケージ。
Wherein the tree fat made of the package body (11a), embedded in the interior of the package body (11a), said path
A plurality of leads (12) having exposed surfaces on both upper and lower surfaces and an outer peripheral edge of the package body (11a); and a plate-like metal buried through a central portion of the package body (11a). A heat release portion (13), a groove (14) formed at a predetermined position in the center of the upper surface of the package body (11a) with a predetermined depth, and the metal heat release portion ( 13) a semiconductor chip (15) adhered to the surface, a metal wire (16) for connecting a plurality of electrodes provided on the upper surface of the semiconductor chip (15) to the leads (12), respectively; (11a) The groove (1 ) covering the upper surface
4) A semiconductor package comprising: a lid (11b ) for sealing;
【請求項3】前記蓋体(11b)は、前記パッケージ本
体(11a)の厚さよりも薄く形成される請求項2に記
載の半導体パッケージ。
3. The semiconductor package according to claim 2, wherein said lid body (11b) is formed thinner than a thickness of said package body (11a).
【請求項4】前記パッケージ本体(11a)は、長方形
の板状である請求項1〜請求項3のいずれか1つに記載
の半導体パッケージ。
4. The semiconductor package according to claim 1, wherein said package body has a rectangular plate shape.
【請求項5】前記パッケージ本体(11a)は、円板状
である請求項1〜請求項3のいずれか1つに記載の半導
体パッケージ。
5. The semiconductor package according to claim 1, wherein said package body has a disk shape.
【請求項6】 角柱状の金属性熱放出部材(8)と、該金
属性熱放出部材(8)の周囲に略平行に配設した複数の
柱状リード部材(9)とを、該リード部材(9)の側部
が露出するように樹脂で固めて一体とした柱状パッケー
ジ材料(10)を形成する第1工程と、 該形成された柱状パッケージ材料(10)を所定厚さに
切断し、金属性熱放出部(13)および複数のリード
(12)の埋設されたパッケージ本体(11a)を形成
する第2工程と、 該切断形成されたパッケージ本体(11a)上面中央所
定部位を切削して所定深さの溝部(14)を形成する第
3工程と、 該溝部(14)内に露出した金属性熱放出部(13)上
面に半導体チップ(15)を接着し、該半導体チップ
(15)上面に設けられた複数の電極と各リード(1
2)とを夫々金属ワイヤー(16)により連結する第4
工程と、 前記半導体チップ(15)、各リード(12)、および
金属ワイヤー(16)をエポキシモールディングコンパ
ウンド(17)により密封する第5工程と、 を順次行う半導体パッケージの製造方法。
6. A prismatic metallic heat emitting member (8) and a plurality of columnar lead members (9) disposed substantially in parallel around the metallic heat emitting member (8). (1) a first step of forming an integrated columnar package material (10) by solidifying with resin so that the side portions are exposed; and cutting the formed columnar package material (10) to a predetermined thickness. A second step of forming a package body (11a) in which the metallic heat emitting portion (13) and the plurality of leads (12) are embedded, and cutting a predetermined portion at the center of the upper surface of the cut and formed package body (11a). A third step of forming a groove (14) having a predetermined depth; and bonding a semiconductor chip (15) to an upper surface of the metallic heat emitting portion (13) exposed in the groove (14). A plurality of electrodes and each lead (1
And 4) connecting each of them with a metal wire (16).
And a fifth step of sealing the semiconductor chip (15), each lead (12), and the metal wire (16) with an epoxy molding compound (17).
【請求項7】 角柱状の金属性熱放出部材(8)と、該金
属性熱放出部材(8)の周囲に略平行に配設した複数の
柱状リード部材(9)とを、該リード部材(9)の側部
が露出するように樹脂で固めて一体とした柱状パッケー
ジ材料(10)を形成する第1工程と、 該形成された柱状パッケージ材料(10)を所定厚さに
切断し、金属性熱放出部(13)および複数のリード
(12)の埋設されたパッケージ本体(11a)を形成
する第2工程と、 該切断形成されたパッケージ本体(11a)上面中央所
定部位を切削して所定深さの溝部(14)を形成する第
3工程と、 該溝部(14)内に露出した金属性熱放出部(13)上
面に半導体チップ(15)を接着し、該半導体チップ
(15)上面に設けられた複数の電極と各リード(1
2)とを夫々金属ワイヤー(16)により連結する第4
工程と、 前記パッケージ本体(11a)上面を蓋体(11b)で
覆い前記溝部(14)を密封する第5工程と、 を順次行う半導体パッケージの製造方法。
7. A lead-shaped metal heat-dissipating member (8) and a plurality of columnar lead members (9) disposed substantially in parallel around the metallic heat-dissipating member (8). (1) a first step of forming an integrated columnar package material (10) by solidifying with resin so that the side portions are exposed; and cutting the formed columnar package material (10) to a predetermined thickness. A second step of forming a package body (11a) in which the metallic heat emitting portion (13) and the plurality of leads (12) are embedded; A third step of forming a groove (14) having a predetermined depth; and bonding a semiconductor chip (15) to an upper surface of the metallic heat emitting portion (13) exposed in the groove (14). A plurality of electrodes and each lead (1
And 4) connecting each of them with a metal wire (16).
And a fifth step of covering the upper surface of the package body (11a) with a lid (11b) and sealing the groove (14).
【請求項8】 前記蓋体(11b)は、前記柱状パッケー
ジ材料(10)を所定厚さに切断して形成する請求項
に記載の半導体パッケージの製造方法。
Wherein said lid (11b) is claim is formed by cutting the columnar packaging material (10) to a predetermined thickness 7
5. The method for manufacturing a semiconductor package according to claim 1.
JP8342950A 1995-12-29 1996-12-24 Semiconductor package and manufacturing method thereof Expired - Fee Related JP2819282B2 (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
KR67332/1995 1995-12-29
KR1019950067332A KR100206880B1 (en) 1995-12-29 1995-12-29 Columnar package with heat sink

Publications (2)

Publication Number Publication Date
JPH09186273A JPH09186273A (en) 1997-07-15
JP2819282B2 true JP2819282B2 (en) 1998-10-30

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Country Link
JP (1) JP2819282B2 (en)
KR (1) KR100206880B1 (en)
CN (1) CN1065659C (en)

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CN100369241C (en) * 2003-10-13 2008-02-13 联华电子股份有限公司 Quad flat non-leaded chip package structure and process thereof
CN102437824B (en) * 2011-12-05 2015-03-11 北京大学 Direct-cooling type high integrated level charge sensitive pre-amplifier
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