JP2819938B2 - Method for manufacturing semiconductor device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, and more particularly to a method for manufacturing a semiconductor device using a laser irradiation method as a plating method.

[0002]

2. Description of the Related Art A conventional method of manufacturing a semiconductor device using a plating method will be described with reference to FIGS.

As shown in FIG. 6A, a diffusion layer 102 is formed on a semiconductor substrate 101 by using a known method.
A structure including a first insulating film 103 made of a silicon oxide film having a thickness of μm and an interlayer connection hole 104 having a diameter of 0.4 to 1.5 μm is formed. In this case, the diffusion layer is formed by an ion implantation method, the first insulating film is formed by a thermal CVD method, and the interlayer connection hole is opened by a reactive ion etching method using a resist as a mask.

[0006] Subsequently, as shown in FIG. 6 (b), a first conductive film layer 105 made of a titanium-tungsten alloy obtained by adding 10 wt% of titanium to tungsten is formed by D.C. C. Film formation power of 1.0 to 4.0 by magnetron sputtering
Under the conditions of KW and a film forming pressure of 1 to 10 mmTorr, the pressure is set to 0.
It is formed with a thickness of 1 μm. Further, the second conductive film layer 106 made of, for example, gold is formed on the first conductive film layer 105 by using the same method under the conditions of a film forming power of 0.2 to 2.0 kW and a film forming pressure of 1 to 10 mmTorr. , 0.02-0.0
It is formed with a thickness of 5 μm.

The first conductive film layer 105 is provided as a layer for preventing the constituent elements of the second low-resistance metal film and the second conductive film layer 106 formed in a later step from diffusing into the active region. It also functions as an adhesion layer between one insulating film. On the other hand, the second conductive film layer 106 supplies a plating current during the growth of the second low-resistance metal film, stably grows the plating film, secures adhesion between the low-resistance metal film and the first conductive film layer, and forms the first conductive film. It is configured for the purpose of protecting the film layer surface from the plating solution.

Subsequently, as shown in FIG. 6C, a photolithography method using a g-line or an i-line
A second mask film 111 made of a photoresist having a thickness of about 2.0 μm is formed on the second conductive film layer 106 and patterned.

Further, as shown in FIG. 6D, a second low-resistance metal film 112 made of gold is selectively formed on the exposed second conductive film layer 106 by electroplating, which is a known method, on the second conductive film layer 106. It is formed with a thickness of 0.5 to 1.5 μm. The electrolytic gold plating solution contains sulfuric acid, sodium gold sulfate or the like as a main component, to which a flattening agent, a pH stabilizer and the like are added. This solution is a non-cyanic solution which usually contains about 10 g of gold per liter and has a pH near neutral (6-8). Gold plating is performed at a plating temperature of 35 to 60 ° C. and a current density of 1 to 4 mA from the viewpoint of film quality and uniformity of the plating film.
/ Cm ² is preferably performed.

Next, as shown in FIG. 6E, when the second low-resistance metal film 112 is formed, when the interlayer connection hole is fine, when the aspect ratio is large, or when the hole shape is bad, the second low resistance metal film 112 is formed. Voids (cavities) 116 in the resistance metal film 112
This is not suitable for burying fine holes or holes having a high aspect ratio. Further, even when the interlayer connection hole has a reverse tapered shape, it is easy to form a void in the upper portion of the hole, so that care must be taken when opening the interlayer connection hole.

Subsequently, as shown in FIG. 7A, the second mask film 111 is removed by a wet stripping method using an organic solvent or an ashing method using oxygen plasma.

Further, as shown in FIG. 7B, the exposed second conductive film layer 106 is etched using the first low-resistance metal film 108 formed by electrolytic plating as an etching mask, and then the exposed first conductive film 106 is etched. The layer 105 is also etched to form a wiring pattern. For example, when the first conductive film layer 105 is made of a titanium-tungsten alloy and the second conductive film layer 106 is made of gold, and these are removed by a wet etching method, the gold is made of aqua regia having a concentration of 10 to 20 vol% and a temperature of 2%.
It is preferable that the etching is performed at 5 to 50 ° C., and that the titanium-tungsten alloy is etched with a hydrogen peroxide solution having a concentration of 50 to 100 vol% at a temperature of 25 to 45 ° C.

When the entire etching process is to be performed dry, an unnecessary portion of the second conductive film layer is removed by an ion milling method using Ar gas as a milling source, and the first conductive film layer is formed of CF ₄ , SF ₆ or the like. It can be removed by a reactive ion etching method using a fluorine-based gas. It is also possible to remove the second conductive film layer by wet etching and the first conductive film layer by dry etching.

Subsequently, as shown in FIG. 7C, a third insulating film 115 made of a silicon nitride film is formed on the metal wiring by a plasma CVD method using SiH ₄ and NH ₃ as reactive gases. It is formed with a thickness of 5 to 1.0 μm.

By the above steps, a metal wiring and an upper layer composed of a diffusion layer 102, a first insulating film 103, a first conductive film 105, a second conductive film 106, and a second low resistance metal film 112 are formed on a semiconductor substrate 101. Of the third insulating film 115 was formed.

Next, a conventional method for manufacturing a semiconductor device using a laser irradiation method will be described. FIG. 8 shows a conventional manufacturing method in the order of manufacturing steps.

As shown in FIG. 8A, a diffusion layer 102 is formed on a semiconductor substrate 101 by a silicon oxide film with a thickness of 0.50 to 1.50 μm in the same manner as in a conventional method of manufacturing a semiconductor device by a plating method. First insulating film 103, 0.60
A structure including an interlayer connection hole 104 having a diameter of about 1.50 μm is formed.

Further, as shown in FIG.
The second conductive film 105 made of titanium having a thickness of 0.05 to 0.05 μm and titanium nitride having a thickness of 0.05 to 0.10 μm
On the insulating film and the interlayer connection hole 104, D.P. C.
It is formed by a magnetron sputtering method or a reactive sputtering method. Further, a second low-resistance metal film 112 made of aluminum having a thickness of 0.50 to 1.00 μm is formed by D.I. C. It is formed by magnetron sputtering. At this time, if the step coverage of the aluminum is poor, voids will be generated when the interlayer connection holes are filled by laser reflow in a later process, so that the sputtering conditions also need to be carefully determined.

Subsequently, as shown in FIG. 8C, an excimer laser beam 109 having a wavelength of 308 nm using XeCl as a light source is irradiated with pulses to melt and flow the second low-resistance metal film 112 to fill the inside of the interlayer connection hole. . Irradiation pulse interval,
Irradiation conditions such as pulse energy density need to be changed depending on the reflectance, film thickness, burying depth and the like of the second low-resistance metal film. The pulse interval is several to several tens of nanoseconds, and the pulse energy density is 2 to 10 J /. It is preferable to set it to about cm ² . When irradiation is performed with excessive energy, care must be taken because the supplied heat may cause the destruction of the pn junction existing in the lower layer. In this method, since the amount of irradiation energy is particularly large, sufficient consideration is required. When an aluminum-based alloy in which silicon or copper is added to aluminum is used for the second low-resistance metal film, laser irradiation conditions are determined in consideration of segregation of added elements during melting to solidification.

Next, as shown in FIG. 8D, unnecessary portions of the second low-resistance metal film and the first conductive film layer are removed by using known techniques such as photolithography and dry etching to form a wiring pattern. I do.

At present, the flatness and smoothness of the surface of the second low-resistance metal film are lost due to melting of the entire surface by laser irradiation, and it is difficult to form a mask at the time of wiring patterning. Attention must be paid to the fact that the filling property of the second low-resistance metal film changes depending on the density and arrangement of the interlayer connection holes and becomes pattern dependent. As described above, in the conventional manufacturing method, the wiring including the first conductive film layer 105 and the second low-resistance metal film 112 is manufactured on the diffusion layer formed on the semiconductor substrate by using the above method. .

Another example of a conventional method of manufacturing a semiconductor device using a laser irradiation method is as follows. FIG. 9 shows another example of a conventional method of manufacturing a semiconductor device using a laser irradiation method in the order of manufacturing steps.

As shown in FIG. 9A, a diffusion layer 102 is formed on a semiconductor substrate 101, and a first insulating film 103 and a 0.60 to 1.50 μm thick silicon oxide film are formed.
A structure composed of interlayer connection holes 104 having a diameter of 1.50 μm is formed. Further, a first low-resistance metal film 108 made of aluminum having a thickness of 0.20 to 0.60 μm is formed on the first insulating film and the interlayer connection hole 104 by D.P. C. It is formed by magnetron sputtering.

Subsequently, as shown in FIG. 9B, an etching mask is used by using a tri-etching technique, which is a known technique, such that the first low-resistance metal film 108 remains only in and around the interlayer connection hole. Unnecessary portions of the first low-resistance metal film are removed.

Then, as shown in FIG.
Excimer laser light 10 with a wavelength of 308 nm
9 is irradiated with a pulse to melt and flow the first low-resistance metal film 108 existing in and around the interlayer connection hole to fill the inside of the interlayer connection hole. In this case, the pulse interval is several to several tens nsec, and the pulse energy density is 0.2 to
It is preferred to be about 1.0 J / cm ² . in this case,
Since the amount of irradiation energy is small, the possibility of destruction of the pn junction is reduced.

Further, as shown in FIG. 9D, a second low-resistance metal film 112 made of aluminum is formed on the first insulating film to a thickness of 0.50 to 1.00 μm by a sputtering method.
Formed on a low-resistance metal film, and patterned by photolithography and dry etching techniques to manufacture wiring composed of a first conductive film layer and a second low-resistance metal film on a diffusion layer on a semiconductor substrate Was.

The etching mask used at this time is formed for the purpose of connecting the circuits of the semiconductor device, and is different from the etching mask used for selectively growing the first low-resistance metal film. In the above process, the irradiation energy can be reduced and the pattern dependency of the filling property can be eliminated. However, the first insulating film exposed in the etching process of each of the first low-resistance metal film and the second low-resistance metal film has an overetch amount. The film will be reduced. Inevitably, two steps occur around the interlayer connection hole, and the uniformity of the thickness of the first insulating film on the wafer is reduced.

[0026]

The above-mentioned conventional method for manufacturing a semiconductor device has the following disadvantages.

(1) In the case where the diameter of the interlayer connection hole is increased or the aspect ratio is increased due to the high integration of the semiconductor device or the shape of the interlayer connection hole is poor, in the conventional electrolytic plating method, a low level is formed in the interlayer connection hole. When forming the resistance metal film, voids are formed in the interlayer connection holes, and it is difficult to obtain a high yield in the manufacturing process due to the influence of the residues in the voids.

(2) Even after completion as a product, the residue in the voids and the existence of the voids themselves tend to cause fluctuations in the characteristics of the semiconductor device due to aging, and cause electromigration and stress migration in the interlayer connection. The long-term reliability of the semiconductor device is deteriorated, for example, the disconnection at the interlayer connection is likely to occur due to the generation of the semiconductor device.

(3) The first low-resistance metal film formed by the sputtering method has poor step coverage compared to the film formed by the plating method, and the film thickness above the hole is large. Therefore, a void is easily formed when the first low-resistance metal film is filled in the interlayer connection hole by laser irradiation, and it is difficult to apply the method to a fine hole and a high aspect ratio hole.

(4) When the second low-resistance metal film formed by the whole surface sputtering method is to be reflowed, uniform filling cannot be performed because the filling pattern is dependent on the difference in the density distribution of the interlayer connection holes. . Further, the reflow reduces the smoothness of the entire surface of the second low-resistance metal film, and the pattern dimension controllability in the lithography process during wiring patterning decreases. Therefore, it is difficult to obtain uniform electric characteristics.

(5) When reflowing the first low-resistance metal film formed by the entire surface sputtering method, laser irradiation with high energy is required. Therefore, the influence on the pn junction becomes large, and application to a fine semiconductor device having a shallow pn junction is difficult.

(6) When a process of patterning the first low-resistance metal film before filling the first low-resistance metal film into the interlayer connection hole by laser irradiation is used, the energy can be reduced, and the energy can be reduced in a later step. (2) Since the low resistance metal film is formed and patterned, the above-mentioned problems (4) and (5) can be solved. However, the underlying first insulating film exposed during the patterning of the first low-resistance metal film is also etched for the time of the over-etching, and a step occurs in the first insulating film. Further, also at the time of forming the wiring pattern of the second low-resistance metal film, the exposed portion of the first insulating film is also etched for the time of the over-etching. As a result, two steps occur in the first insulating film thickness, so that the uniformity of the first insulating film thickness is reduced and the characteristics of the semiconductor device become unstable.

[0033]

The method of manufacturing a semiconductor device of the present invention According to an aspect of the diffusion layer formed on a semiconductor substrate, formed by either of the polycrystalline silicon layer or a metal silicide layer
Forming a structure comprising a conductive layer to be formed, a first insulating film provided thereon and an interlayer connection hole opened in the first insulating film, or a first insulating film formed on a semiconductor substrate, A lower wiring formed of a single layer or a plurality of conductive films formed on the first insulating film, a second insulating film formed on the lower wiring, and an interlayer connection hole opened in the second insulating film; Forming a structure comprising: forming on the conductive layer and the first insulating film, or forming the lower layer wiring and the second
A first layer composed of a single layer or a plurality of layers on an insulating film;
Forming a conductive film layer; and forming a second conductive film on the first conductive film layer.
Forming a conductive film layer, forming a first mask film that exposes only the second conductive film layer present inside and around the interlayer insulating hole, and plating the first mask film. Performing plating as a mask to selectively form a first low-resistance metal film on the exposed second conductive film layer;
Removing the mask film;
A step of melting and flowing the low-resistance metal film so as to fill the first low-resistance metal film inside the interlayer connection hole, and forming a third conductive film layer composed of the same element as the second conductive film layer thereon. A step of selectively forming a second mask film for forming a wiring on the third conductive film layer; and performing plating using the second mask film as a plating mask, and forming the second mask film on the exposed third conductive film layer. A step of selectively forming a second low-resistance metal film, a step of removing the second mask film, an unnecessary portion of the exposed third conductive film layer, an unnecessary portion of the second conductive film layer, and the first conductive film layer Are sequentially removed to form a first conductive film layer, a second conductive film layer,
Forming a metal wiring composed of a third conductive film layer and a second low-resistance metal film; and forming a third insulating film on the metal wiring.

According to the method of manufacturing a semiconductor device of the present invention, the step coverage is compared with the sputtering method only in the inner and peripheral portions of the interlayer connection hole formed on the diffusion layer, the polycrystalline silicon layer, the metal silicide layer or the lower wiring. The first low-resistance metal film is formed in a fine interlayer connection hole by melting and flowing the first low-resistance metal film formed by an excellent plating method by laser irradiation and filling the inside of the interlayer connection hole. No voids are formed when

As a result, voidless filling into interlayer connection holes that are finer and higher in aspect ratio than the conventional sputtering method can be performed. As a result, a low interlayer connection resistance is obtained, the flatness of the wiring directly above the connection hole is increased, and the wiring can be easily multilayered. Further, since the first low-resistance metal film is selectively grown only in a portion that needs to be filled, the total amount of laser melting is smaller than that of the whole surface sputtering method, and the amount of irradiation energy is small. Therefore, damage to the pn junction and the lower wiring can be reduced, and the present invention can be applied to a fine semiconductor device having a shallow junction and a thin wiring. In addition, the first low-resistance metal film is formed by selective growth, and does not cause a pattern dependency of the filling property due to a difference in the density distribution of interlayer connection holes, which has been a problem of the entire surface sputtering method. Further, since the second low-resistance metal film does not require reflow, there is no change in the flatness and smoothness of the surface, and the pattern dimension controllability in the lithography step of wiring patterning does not decrease. Since the first low-resistance metal film does not require a patterning step before reflow, the uniformity of the thickness of the underlying insulating film under the wiring formed of the second low-resistance metal film is not impaired. Further, since the wiring can be formed by one etching, the reduction of the thickness of the underlying insulating film at the time of overetching the second low-resistance metal film can be minimized. The decrease in film thickness uniformity is small. The formed metal wiring is gold,
The second one with small electric resistance represented by copper or aluminum
Since a laminated structure of a low resistance metal film and a first conductive film layer having a high melting point is used, a metal wiring having low resistance and high electromigration and stress migration resistance in both the wiring portion and the interlayer connection portion can be obtained. There is.

[0036]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, the present invention will be described with reference to the drawings. 1 to 3 show a first embodiment of the present invention in the order of manufacturing steps.

First, as shown in FIG. 1A, the diffusion layers 102, 0.5 to
A first silicon oxide film having a thickness of 1.5 μm;
Insulating film 103, interlayer connection hole 10 having a diameter of 0.3 to 1.5 μm
4 is formed. In this case, the diffusion layer is an ion implantation method, and the first insulating film is a thermal CVD of a SiH ₄ source.
The interlayer connection hole is formed by a reactive ion etching method using a resist as a mask.

In this case, the layer formed at the bottom of the interlayer connection hole does not necessarily need to be a diffusion layer, but may be a metal silicide represented by polycrystalline silicon, titanium silicide, tungsten silicide, or the like.

Subsequently, as shown in FIG. 1B, a first conductive film layer 105 made of a titanium-tungsten alloy in which titanium is added at 10 wt% to tungsten is formed by a known technique such as D.I. C. A film forming power of 1.0 to 4.0 KW and a film forming pressure of 1 to 10 mmTorr by magnetron sputtering.
It is formed on the first insulating film 103 with a thickness of 0.1 μm under the condition of r.

Further, a second conductive film layer 106 made of, for example, gold is formed on the first conductive film layer 105 by using the same method as described above with a film forming power of 0.2 to 2.0 KW and a film forming pressure of 1 to 10 m.
It is formed with a thickness of 0.02 to 0.05 μm under the condition of mTorr.

The first conductive film 105 is a diffusion prevention film (barrier metal) for constituent elements of a low resistance metal film formed in a later step,
It functions as an adhesion layer between the low-resistance metal film and the underlying insulating film.

Other refractory metals such as zirconium, niobium, hafnium, vanadium, molybdenum, etc.
Not limited to the above-mentioned materials, such as alloys, nitrides, silicides, carbides, borides or laminated films of titanium and titanium nitride and titanium and titanium boride, as long as they can secure the heat resistance and the base adhesion. You can do it.

The second conductive film layer 106 is used as a base for plating (plating current supply layer), for stable growth when forming a low-resistance metal film formed by plating, for ensuring adhesion of the low-resistance metal film, and for forming the first conductive film layer. It is formed for the purpose of protecting the surface of the conductive film layer 105 from a plating solution.

In addition to gold, palladium, platinum, rhodium,
Osmium, iridium, ruthenium, etc. can be used. Basically, as a base for film growth at the time of forming the first low-resistance metal film, if it is compatible from the viewpoint of heat resistance, adhesion, plating property, etc. It is not limited to the above elements,
For example, when the low-resistance metal film is made of copper or aluminum, there is no problem even if copper or aluminum is used as the second conductive film layer.

Subsequently, as shown in FIG. 1C, a first mask film made of a photoresist is formed on the second conductive film layer 106 by a photolithography method using a known g-line or i-line. 107 is selectively formed with a thickness of 1.0 to 2.0 μm. The first mask film has a pattern in which the second conductive film layer is exposed only in the interlayer connection hole and its peripheral portion, and is different from a mask pattern for forming a wiring pattern for connecting elements of a semiconductor device. Use something. The material is not limited to the photoresist alone, and may be a polyimide organic resin material or an inorganic material such as an oxide film, a nitride film, and an oxynitride film of silicon.

FIG. 1D shows a top view after the first mask film is formed (before plating). The cross section taken along the line AA in FIG.
This corresponds to the vertical section of (c).

The appropriate margin amount between the interlayer connection hole indicated by L in the figure and the first mask film is determined by the diameter of the interlayer connection hole, the aspect ratio, the film thickness of the first low-resistance metal film to be formed later, or irradiation later. Although it depends on the laser light irradiation conditions, it is basically preferable to use a value of 1/2 to 1/3 of the interlayer connection hole diameter.

Further, as shown in FIG. 1E, a first low resistance metal film 108 made of gold is formed on the second conductive film layer 106.
Of 0.1 to 0.1 by a known technique of electrolytic gold plating.
It is selectively formed with a thickness of 6 μm. At this time, the plating current is supplied through the first conductive film layer 105 and the second conductive film layer 106 that exist below. It is desirable that the film thickness of the first low-resistance metal film is about １ ／ to ／ of the diameter of the interlayer connection hole. If the film thickness is small or large, the supply amount of the first low-resistance metal film into the interlayer connection hole in the subsequent laser reflow process becomes inappropriate, and the flatness on the hole may be deteriorated. Because.

The electrolytic gold plating solution contains sulfuric acid, sodium gold sulfate or the like as a main component, and is used with a flattening agent, a pH stabilizer and the like added thereto. This plating solution is a non-cyan type plating solution usually containing about 10 g of gold per liter, and has a pH near neutral (6 to 8).

In actual plating, from the viewpoint of the quality and uniformity of the plating film, the plating temperature is 35 to 60 ° C., and the current density is 1 to 3.
It is preferable to carry out under the condition of 4 mA / cm ² . In the present embodiment, the first low-resistance metal film 108 is made of gold, but a metal that can be formed on the second conductive film layer 106 by a plating method.
It is not necessary to use gold as long as it is difficult to adhere to the upper and lower insulating films. For example, other low-resistance metals such as copper and aluminum may be used.

Further, as shown in FIG. 2A, after removing the first mask film 107 by an ashing method using oxygen plasma or a wet peeling method using an organic solvent, excimer laser light having a wavelength of 308 nm using XeCl as a light source. 109 is irradiated with a pulse.

Then, as shown in FIG. 2B, the first low-resistance metal film 108 is melted and fluidized to fill the inside of the interlayer connection hole. Irradiation conditions such as pulse intervals and pulse energy densities of the irradiation need to be changed depending on the reflectance, film thickness, burying depth and the like of the first low-resistance metal film. Is 0.2
It is preferable to set it to about 1.0 J / cm ² . Care must be taken when irradiating with excessive energy because the supplied heat may destroy the pn junction existing in the lower layer. However, in this embodiment, the first low-resistance metal film to be melted is localized and the total amount thereof is small, so that the amount of irradiation energy is small. Therefore, there is an advantage that it can be easily applied to a semiconductor device having a shallow pn junction. The first low-resistance metal film formed by plating has longer step coverage than that formed by sputtering.
Therefore, it has an advantage in filling voidless holes into minute holes.

Also, by filling the first low-resistance metal film with a mask film and using a mask film to localize its existence, the filling property is improved, and the pattern dependency at the time of filling and the smoothness of the surface at the time of reflow are improved. Changes can be suppressed. Melting of the first low resistance metal film
At the time of filling the interlayer connection hole by the flow, a reaction layer of the first low resistance metal film and the second conductive film layer is formed at the interface between the two, but there is no structural difference before and after laser irradiation.

Subsequently, as shown in FIG. 2C, the third conductive film layer 110 made of gold is formed to a thickness of 0.02 to 0.05 μm.
m on the second conductive film layer 106 with a thickness of m. C. It is formed by magnetron sputtering.

Although the thin second conductive film layer is melted during the irradiation with the laser beam, if the second conductive film layer is agglomerated after that, when the second low-resistance metal film is formed by an electrolytic plating method in a later step, the plating current becomes uneven. And the thickness of the second low-resistance metal film tends to be non-uniform. As a preventive measure, the third conductive film layer is formed, and the same material as the second conductive film layer can be used.

Further, as shown in FIG. 2D, a second mask film 111 made of a photoresist is selectively formed on the third conductive film layer 110 to a thickness of 1.0 to 2.0 μm.
Further, a second low-resistance metal film 112 made of gold is formed on the third conductive film layer 110 by electrolytic gold plating, which is a known technique, under the same conditions as when forming the first low-resistance metal film.
It is selectively formed with a thickness of 5 to 1.5 μm.

The second mask film is a mask pattern for forming a wiring pattern for connecting the elements of the semiconductor device, and has a different purpose from the first mask film. The material is not limited to only the photoresist, but a polyimide organic resin material, a silicon oxide film,
An inorganic material such as a nitride film or an oxynitride film may be used.

In this embodiment, the first low-resistance metal film and the second
Although the electrolytic plating method is used to form the low-resistance metal film, these metal films may be formed by an electroless plating method.

Subsequently, as shown in FIG. 2E, the second mask film 111 is removed by an ashing method using oxygen plasma or a peeling method using an organic solvent.

Then, as shown in FIG. 3A, the third conductive film layer and the second conductive film layer exposed by the wet etching method using the second low-resistance metal film as an etching mask are sequentially removed to form a wiring pattern. .

For example, the first conductive film layer is made of a titanium-tungsten alloy, the second conductive film layer and the third conductive film layer are made of gold,
When these are removed by the wet etching method, gold is 1
Etching is performed at 25 to 50 ° C. using aqua regia of 0 to 20 vol%, and 50 to 100 vol.
When etching is performed at 25 ° C. to 45 ° C. using 1% hydrogen peroxide solution, a favorable wiring shape with little side etch can be obtained. Since the second low-resistance metal film is slightly etched in this etching step, the thickness at the time of film formation needs to be determined in consideration of the film reduction.

The wet etching method has an advantage that damage to the surface can be suppressed as compared with the dry etching method because there is no attack of ions on the low-resistance metal film. On the other hand, application of the semiconductor device may be difficult depending on the design rule of the semiconductor device due to side etching. Needless to say, the unnecessary portions of both conductive film layers need not be removed only by the wet etching method, but as described above, the dry etching method or the method combining dry etching and wet etching depending on the type and wiring width of both conductive film layers. May be suitable.

For example, when the element having low chemical activity such as platinum or the like and difficult to remove by wet etching is the second conductive film layer or the third conductive film layer, the collision energy of ions such as ion milling is reduced. It is desirable to remove by the physical etching method used.

The removal of the first conductive film layer by dry etching can be performed by reactive ion etching. In many cases, the first conductive film layer is made of the above-mentioned fluorine-based gas or CCl ₄ , B
A chlorine-based gas represented by Cl ₃ or the like is used. Also in these removal steps, the second low-resistance metal film serving as a mask is etched to reduce the film thickness. Therefore, it is necessary to set the film thickness at the time of film formation in consideration of the reduction of the film.

Further, as shown in FIG. 3C, the third insulating film 115 made of a silicon oxide film is formed by a plasma CVD method using SiH ₄ gas and N ₂ O gas by 0.50 to 0.50.
It is formed on the first insulating film and the wiring pattern with a thickness of 1.00 μm. The third insulating film formed here does not necessarily need to be a silicon oxide film. For example, PS
An oxide film containing phosphorus or boron, such as G, BSG, or BPSG, a silicon nitride film, a silicon oxynitride film, a polyimide resin-based organic film, or a laminated structure of these may be used. The method of forming the film is not limited to the plasma CVD method, but may be another method such as SOG (spin on glass) or a spin coating method represented by a polyimide resin material.

Further, it is also effective to combine the flattening treatment of the insulating film typified by the etching back method of the insulating film using the reactive ion etching. In the above-described method of manufacturing a semiconductor device, the peripheral portion of the first low-resistance metal film having a small electric resistance selectively filled in the void connection into the interlayer connection hole is covered with the high-melting-point metal film layer. Since the refractory metal film layer also exists under the second low-resistance metal film, which is a material, a fine semiconductor device having high long-term reliability and good electrical characteristics as compared with the conventional manufacturing method is stable at a high yield. Is obtained.

The method of manufacturing a semiconductor device according to the present invention
It goes without saying that the present invention is applicable irrespective of the type of semiconductor device such as S, Bipolar, or Bi-CMOS.

Next, a second embodiment of the present invention will be described with reference to the drawings. 4 and 5 are longitudinal sectional views showing a second embodiment of the present invention in the order of manufacturing steps.

As shown in FIG. 4A, the semiconductor substrate 101
A first insulating film 103 having a thickness of 0.50 μm formed thereon by a thermal CVD method using SiH ₄ as a reaction gas;
0.1 μm thick titanium nitride, 0.02 to
A lower wiring 114 composed of a sputtered gold film of 0.05 μm and a gold plating film of 0.5 to 1.0 μm, and S
a second insulating film 113 composed of a silicon oxide film having a thickness of 0.5 to 1.0 μm formed by a plasma CVD method using iH ₄ gas and N ₂ O gas, and the second insulating film 11
3, a structure including an interlayer connection hole 104 having a diameter of 0.5 to 1.0 μm and formed by photolithography and reactive ion etching.

Titanium nitride is formed by a reactive sputtering method using titanium as a target and a mixed gas of nitrogen and argon as a sputtering gas.

The sputtered gold film was obtained from C. The film is formed by magnetron sputtering under the conditions of a film forming power of 0.5 to 2.0 KW and a pressure of 1 to 10 mmTorr.

The plated gold film is formed by electrolytic gold plating using a photoresist as shown in the first embodiment.
Wiring patterning also uses the etching technique shown in the first embodiment. The lower wiring is not particularly limited to gold, but may be another material such as an aluminum material or a copper material.

Next, as shown in FIG. 4B, the first conductive film 105 having a thickness of 0.05 μm and 0.1 μm, respectively, is formed of a two-layer film of titanium and titanium nitride.
3 is formed. Further, on the first conductive film layer 105, a second conductive film layer 106 made of, for example, copper is formed. C. It is formed with a thickness of 0.02 to 0.05 μm by magnetron sputtering.

The first conductive film layer 105 functions as an anti-diffusion film below the constituent elements of the low-resistance metal film formed in a later step and as an adhesion layer between the low-resistance metal film and the underlying insulating film. In addition, any material can be used as long as it can secure heat resistance and base adhesion, such as a high melting point metal film or a laminated film as shown in the first embodiment. The second conductive film layer 106 is for the purpose of providing a plating current supply layer at the time of plating, stable growth at the time of forming a low-resistance metal film, ensuring adhesion of the low-resistance metal film, and protecting the surface of the first conductive film layer 105 from a plating solution. Is formed as

In addition to copper, as a base for film growth during the formation of the first low-resistance metal film, it is basically compatible with copper from the viewpoint of heat resistance, adhesion, plating property, etc. Any material can be used as long as it can deposit a plating film and does not deteriorate the electrical properties of copper or the heat resistance of the first conductive film layer as a barrier metal by heat treatment.

Next, the second conductive film layer 1 is formed by a known technique of photolithography using g-line or i-line.
Mask film 1 composed of photoresist
07 is selectively formed with a thickness of 1.0 to 2.0 μm.
As in the first embodiment, this mask also has a pattern in which the interlayer connection hole and the second conductive film layer around the interlayer connection hole are exposed. The first mask film is not limited to a photoresist, but may be a polyimide-based organic resin material, a silicon oxide film, a nitride film, an oxynitride film, or the like. Further, the first low-resistance metal film 108 made of copper is selectively formed with a thickness of 0.2 to 0.4 μm only on the exposed second conductive film layer 106 by using an electrolytic plating method.

In the plating step, the uniformity of the copper film to be deposited is important. Therefore, it is easy to obtain high uniformity of the plating film thickness.
g / l (liter), 170-220 g / l sulfuric acid, and containing a small amount of chlorine and additives such as a flattening agent.

The actual plating operation is performed at a temperature of 20 to 30 ° C.
When performed under the conditions of a current density of 1 to 3 mA / cm ² , a flat and highly uniform copper film can be formed.

Further, as shown in FIG. 4C, the first mask film 107 is further removed by using oxygen plasma or an organic solvent, and then pulsed with an excimer laser beam 109 having a wavelength of 308 nm using XeCl as a light source.

Then, as shown in FIG. 4D, the first low-resistance metal film 108 melts and flows and fills the inside of the interlayer connection hole 104. Irradiation conditions such as pulse intervals and pulse energy densities of the irradiation need to be changed depending on the reflectance, film thickness, burying depth and the like of the first low-resistance metal film. Is 0.2
It is preferable to set it to about 1.0 J / cm ² . When irradiation is performed with excessive energy, phenomena such as melting of the lower wiring and cracking of the insulating film due to the supplied heat may occur. Therefore, the amount of irradiation energy is carefully determined.

The laser source is not limited to XeCl, but may use KrF or the like. However, in this case, the proper irradiation conditions are different from those for XeCl. Therefore, it is necessary to review the irradiation conditions. The second embodiment also has advantages over the conventional invention, such as improvement of the filling property, suppression of the pattern dependency of the filling property, and lowering of the irradiation energy, as described in the first embodiment. I have.

Subsequently, as shown in FIG. 5A, a third conductive film layer 110 made of copper is formed by sputtering to a thickness of 0.02 mm.
A second mask film 111 which is formed on the entire surface with a thickness of about 0.05 μm and is further used for forming a wiring formed of a resist by photolithography using g-line or i-line.
Is selectively formed with a thickness of 1.0 to 2.5 μm.
Then, a second low-resistance metal film 112 made of copper is selectively formed only on the exposed third conductive film layer with a thickness of 0.5 to 1.5 μm by electrolytic plating. The conditions for copper plating at this time are the same as those for forming the first low-resistance metal film.

Further, as shown in FIG. 5B, the second mask film is removed by using a known method such as oxygen plasma or an organic solvent.

Subsequently, as shown in FIG. 5C, the exposed second conductive film layer 106 is formed on the exposed second conductive film layer 106 by a reactive ion etching method using a chlorine-based gas such as CCl ₄ or BCl _3. The first conductive film layer 105 is etched and removed as an etching mask, and the exposed first conductive film layer 105 is also etched and removed by a reactive ion etching method using a chlorine-based gas to form a wiring pattern. In this etching step, the second low resistance metal film 112 is slightly etched. Therefore, the thickness of the second low-resistance metal film at the time of film formation needs to be determined in consideration of the reduction of the film. The method of etching both conductive film layers need not be performed only by dry etching, and a method combined with wet etching may be suitable depending on the type of both conductive film layers.

Further, as shown in FIG. 5D, a third insulating film 115 composed of a silicon oxide film is formed by a known technique such as plasma CVD using SiH ₄ and N ₂ O on the upper layer. It is formed with a thickness of 1.0 μm.

The third insulating film formed here does not necessarily have to be a silicon oxide film, and the same material as in the first embodiment can be used. The film formation method is also plasma CVD
It is not limited to law. It can be formed by other methods such as SOG (spin-on-glass) and a spin coating method represented by a polyimide resin material. Further, when a flattening process typified by an etch-back method is combined, the flatness is further improved, which is more advantageous in forming a multilayer wiring.

In the above-described method for manufacturing a semiconductor device, the peripheral portion of the first low-resistance metal film having a small electric resistance selectively filled in the void connection into the interlayer connection hole is covered with the high-melting-point metal film layer. Further, since a high-melting-point metal film layer also exists under the second low-resistance metal film serving as a main conductive material, a fine semiconductor device having high long-term reliability and good electric characteristics is more expensive than conventional manufacturing methods. It can be obtained in a stable yield. As in the first embodiment, the present invention is applicable regardless of the type of the semiconductor device such as MOS, Bipolar, and Bi-CMOS.

[0088]

As described above, in the method of manufacturing a semiconductor device according to the present invention, the peripheral portion of the first low-resistance metal film having a small electric resistance selectively filled by laser melting in the interlayer connection hole has a high melting point. A structure is obtained in which the high-melting-point metal film layer is also covered under the second low-resistance metal film, which is covered with the metal film layer and has a low electric resistance as a main conductive material, and is low in electric resistance.

Therefore, even a small interlayer connection hole can be buried in a voidless manner, and a structure having low wiring resistance and high electromigration and stress migration resistance in both the wiring portion and the interlayer connection portion can be obtained. Therefore, a fine semiconductor device having high long-term reliability and good electrical characteristics as compared with a conventional structure can be stably obtained at a high yield. Also in the manufacturing process, there is an effect that contributes to an improvement in yield, such as lowering the energy of laser light irradiation and eliminating pattern dependence when filling interlayer vias.

[Brief description of the drawings]

FIG. 1 is a diagram showing a first embodiment of the present invention in the order of manufacturing steps.

FIG. 2 is a diagram showing a first embodiment of the present invention in the order of manufacturing steps.

FIG. 3 is a diagram showing a first embodiment of the present invention in the order of manufacturing steps.

FIG. 4 is a diagram showing a second embodiment of the present invention in the order of manufacturing steps.

FIG. 5 is a view showing a second embodiment of the present invention in the order of manufacturing steps.

FIG. 6 is a diagram showing a conventional semiconductor device structure and a manufacturing method in the order of manufacturing steps.

FIG. 7 is a diagram showing a conventional semiconductor device structure and a manufacturing method in the order of manufacturing steps.

FIG. 8 is a diagram showing a conventional semiconductor device structure and a manufacturing method in the order of manufacturing steps.

FIG. 9 is a diagram showing a conventional semiconductor device structure and a manufacturing method in the order of manufacturing steps.

[Explanation of symbols]

 Reference Signs List 101 semiconductor substrate 102 diffusion layer 103 first insulating film 104 interlayer connection hole 105 first conductive film layer 106 second conductive film layer 107 first mask film 108 first low-resistance metal film 109 excimer laser beam 110 third conductive film layer 111 2nd mask film 112 2nd low resistance metal film 113 2nd insulating film 114 lower layer wiring 115 3rd insulating film 116 void

Continuation of the front page (58) Field surveyed (Int.Cl. ⁶ , DB name) H01L 21/28-21/288 H01L 21/3205 H01L 21/3213 H01L 21/768

Claims (9)

(57) [Claims] 1. A diffusion layer provided on a semiconductor substrate, by any of the polycrystalline silicon layer or a metal silicide layer
Forming a structure comprising a conductive layer to be formed, a first insulating film provided thereover and an interlayer connection hole opened in the first insulating film, or a first insulating film formed on a semiconductor substrate, A lower wiring formed of a single layer or a plurality of conductive films formed on the first insulating film, a second insulating film formed on the lower wiring, and an interlayer connection hole opened in the second insulating film; forming a composed structure, the conductive
Forming a first conductive film layer composed of a single layer or a plurality of layers on the first layer and the first insulating film, or on the lower wiring and the second insulating film; A step of forming a second conductive film layer, a step of forming a first mask film exposing only the second conductive film layer present inside and around the interlayer insulating hole, Plating as a plating mask to selectively form a first low-resistance metal film on the exposed second conductive film layer; removing the first mask film; The first resistance metal film is melted and flown into the inside of the interlayer connection hole.
Filling a low resistance metal film, forming a third conductive film layer composed of the same element as the second conductive film layer thereon, and selectively forming a wiring on the third conductive film layer Forming a second low-resistance metal film on the exposed third conductive film layer by performing plating using the second mask film as a plating mask; 2
The step of removing the mask film, and sequentially removing the unnecessary portion of the exposed third conductive film layer, the unnecessary portion of the second conductive film layer, and the unnecessary portion of the first conductive film layer, A method for manufacturing a semiconductor device, comprising: a step of forming a metal wiring composed of a conductive film layer, a third conductive film layer, and a second low-resistance metal film; and a step of forming a third insulating film on the metal wiring. 2. The method according to claim 1, wherein the first conductive film layer is made of titanium (Ti), vanadium (V), zirconium (Zr), niobium (Nb),
Molybdenum (Mo), hafnium (Hf), tantalum (Ta), tungsten (W), an alloy mainly containing these metals, silicides of these metals, nitrogen compounds, boron compounds, or to any carbon compound The method for manufacturing a semiconductor device according to claim 1, wherein the single-layer film is formed as a single-layer film. 3. The semiconductor device according to claim 1, wherein the first conductive film layer is a two-layer film composed of titanium and titanium nitride or a two-layer film composed of titanium and titanium boride. Manufacturing method. 4. The second conductive film layer or the third conductive film layer is made of gold (Au), palladium (Pd), platinum (Pt), osmium (Os), iridium (Ir), rhodium (R).
h), ruthenium (Ru), rhenium (Re), aluminum (Al), copper (Cu), or an alloy mainly composed of these elements. 13. The method for manufacturing a semiconductor device according to item 5. 5. The method according to claim 1, wherein the first mask film and the second mask film are formed of a photoresist, a polyimide organic resin, a silicon oxide film,
2. The method according to claim 1, wherein the semiconductor device is formed of one of a silicon nitride film and a silicon oxynitride film. 6. The method according to claim 1, wherein the first low-resistance metal film and the second low-resistance film mainly contain one of gold, copper, aluminum and silver. 7. The method for manufacturing a semiconductor device according to claim 1, wherein the light source of the laser to be irradiated is XeCl or KrF. 8. The method according to claim 1, further comprising the step of irradiating the first low-resistance metal film with a laser beam by a pulse irradiation method. 9. The method according to claim 1, wherein the first insulating film, the second insulating film, and the third insulating film are silicon oxide films, silicon oxide films containing at least phosphorus (P) or boron (B), silicon nitride films, silicon oxynitride films, 2. The method for manufacturing a semiconductor device according to claim 1, wherein the semiconductor device is formed of one of a polyimide resin-based organic film and a laminated structure film of these.