JP2820152B2 - Method for manufacturing semiconductor memory device - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit device, and more particularly to a semiconductor integrated circuit device applied to writing information to a memory cell of a mask ROM (Read Only Memory) as a semiconductor memory device. It is about effective technology. [Prior Art] In a mask ROM, usually, a memory cell is configured by MISFET, and writing of information to this memory cell is performed by:
This is performed by controlling the threshold voltage of the MISFET. As one type of the mask ROM, a vertical ROM is known (for example, JP-A-52-30388). In this vertical ROM, a memory cell made of MISFET is provided at each intersection of a data line and a word line, a plurality of these memory cells are connected in series, and a plurality of memory cell columns are arranged to form a memory cell array. It is configured. The inventor has studied a method of writing information into the memory cells of the vertical ROM. The following is not a known technique, but is a technique studied by the present inventor, and its outline is as follows. That is, the writing of information into the memory cells of the vertical ROM is performed by the following steps. For example, by performing channel doping of boron after forming the gate insulating film, all the MISFETs constituting each memory cell are configured in advance as an enhancement type. And an enhancement type MI selected from among the enhancement type MISFETs.
Information is written by performing channel doping of phosphorus in a channel portion of the SFET and depleting the selected MISFET. in this case,
For example, an enhancement type MISFET corresponds to information "1",
The depletion type MISFET is made to correspond to the information “0”. [Problems to be Solved by the Invention] However, since the process of writing information by the channel doping of phosphorus is relatively early in the manufacturing process of the vertical ROM, the time required to complete the vertical ROM in which desired information is written is , That is, turn around time (Turn Aro
und Time). This turnaround time can be reduced if the channel doping of phosphorus can be performed after forming an Al wiring on an interlayer insulating film such as a phosphorus silicate glass (PSG) film. Is large (mass number 31), it is difficult to perform channel doping of phosphorus through the interlayer insulating film with practical ion implantation energy. Further, in writing information to the memory cells of the vertical ROM, all MISFETs constituting the memory cells are configured in advance in an enhancement type, and the enhancement type MISFETs are subjected to phosphorus (P) channel doping based on the information to be written. In the case of the depletion type, due to misalignment of the mask used at the time of the channel doping of the phosphorus (P), phosphorus (P) may also be part of the channel of the MISFET which must be kept in the enhancement type. There is a problem that is introduced and causes information errors. If the channel doping of phosphorus (P) is performed after the formation of the source / drain regions of the MISFET, the field insulating film (LOCOS oxide film) is doped because phosphorus (P) is doped at high energy and high concentration. In the bird's beak portion, the phosphorus (P) is deeply doped, which causes a problem that punch-through occurs with a data line of an adjacent memory. An object of the present invention is to provide a technique capable of reducing the turnaround time of a semiconductor memory device in which desired information is written in a memory cell. Another object of the present invention is to improve the reliability of writing information in a semiconductor memory device. The above and other objects and novel features of the present invention are as follows.
It will become apparent from the description of the present specification and the accompanying drawings. [Means for Solving the Problems] Of the inventions disclosed in the present application, typical ones will be outlined as follows. That is, all the MISFETs constituting the memory cell are configured in advance in a depletion type, and
An impurity having a smaller mass than phosphorus (P) is introduced into the channel portion of the depletion type MISFET selected from the MISFETs from above the interlayer insulating film by channel doping, and the depletion type MISFET is enhanced. Information is written to a memory cell by making the memory cell weak or weak depletion type. [Operation] According to the above-described means, since impurities having a small mass have a high permeability, by performing channel doping through an interlayer insulating film after or before wiring formation, the enhancement type of the depletion type MISFET is improved. Information can be written by the weakening or weak depletion type.
Therefore, it is possible to reduce the turnaround time of the semiconductor memory device in which desired information is written in the memory cell. In addition, since the MISFET constituting the memory cell is previously formed into a depletion type, and then is made to be an enhancement type or a weak depletion type by impurity channel doping, the impurity has to be originally left in a depletion type. Even if it is introduced into a part of the channel of the MISFET which has to be introduced, if it is not introduced into most of the channel, an error of information is unlikely to occur. Further, by enhancing the MISFET by the channel doping, the MISFET can also serve as a channel stopper with an adjacent data line. Another feature is that
As shown in FIG. 8, the threshold (Vth) of the MISFET (EEMOS) enhanced by channel doping with boron (B ⁺⁺ ) as compared with the active NMOS has less short channel effect, There is an advantage that it can be used positively for miniaturization of memory cells. For the above reason, it is possible to improve the reliability of writing information in the ROM and to increase a margin in device design. Embodiment Hereinafter, a configuration of the present invention will be described based on an embodiment with reference to the drawings. In all the drawings, components having the same functions are denoted by the same reference numerals, and repeated description thereof will be omitted. FIG. 1 is a circuit diagram showing a circuit configuration of a vertical ROM according to one embodiment of the present invention. As shown in FIG. 1, the vertical ROM according to the present embodiment is provided with a row address decoder XDCR1.2, a decoder DCR, and a column address decoder YDCR. This row address decoder XDCR1.2 has many word lines W ₁ , W
₂ are connected, _{one of} these word lines W ₁ , W _2, etc. is set to low level (L) and the other word line is set to high level (H) based on the address signals A ₁ -An. ). Further, the decoder DCR includes MISFETT ₁ provided for each of a large number of data lines D ₁ , D _2, etc.
It is connected to the gates of T ₁ ′, T ₂ , T ₂ ′, etc. Address signal
One of the data lines D ₁ , D _2, etc. is selected by turning on any one of the MISFETs T ₁ , T _2, etc. based on An + ₁ to Am, and the selected one is selected. The data line and the common data line CD are connected.
One end of each of these data lines D ₁ and D ₂ is connected to the ground potential Vss.
Is set to At the intersections of the word lines W ₁ , W ₂ etc. and the data lines D ₁ , D ₂ etc., MISFETs Q ₁ , Q ₂ ,
Q ₃ , Q ₁ ′, Q ₂ ′, Q ₃ ′, etc. are provided, and a memory cell array M-ARY is constituted by the memory cells composed of the MISFETs. In this memory cell array M-ARY,
A plurality of MISFETs in which different word lines are coupled to respective gates are connected in series to one data line, and the MISFET column is arranged for each data line. Then, a memory cell from which information is to be read is selected by the row address decoder XDCR and the decoder DCR, and a signal corresponding to the read information is output through the common data line CD. Although only one memory cell array M-ARY is shown in FIG. 1 in the vertical ROM according to the present embodiment, a plurality of memory cell arrays M-ARY are actually provided. The MISFET configuring the memory cell array M-ARY includes:
As will be described later, first of all, a depletion type (for example, corresponding to information "0") is formed by channel doping by ion implantation of phosphorus, for example. Through the film or after the formation of the source / drain regions, the channel formed by ion implantation of boron into the channel portion of the depletion type MISFET corresponding to the memory cell into which information “1” is to be written without the interlayer insulating film. By performing doping, an enhancement type or a weak depletion type (the absolute value of the threshold voltage is small) is obtained, whereby desired information is written. As a result, the turnaround time of the vertical ROM in which desired information is written can be reduced as described later. The common data line output from the CD ₁ ~CDn is input to the sense amplifier SA through the column switch MISFETM ₁ ~Mn.
The gate electrode of each of said column switch MISFETM ₁ ~Mn is coupled to the column decoder YDCR, Al _H 1 single column switch MISFET among them in accordance with signals ~Ak is selected. In this case, a separate dummy data line Dd is provided to obtain a reference for the sense amplifier SA. In each of the dummy data lines Dd, for example, a plurality of enhancement-type MISFETs Qd ₁ and Qd ₂ are connected in series.
One end of the dummy data line Dd is set to the ground potential Vss, the other end is connected to a sense amplifier SAd having the same configuration as the sense amplifier SA, and an output from the dummy data line Dd is supplied to the sense amplifier SAd. It has become.
The output of the sense amplifier SA and the sense amplifier SA
The output of d is compared with, for example, a one-stage or two-stage differential amplification base DA. The output Dout of the differential amplifier DA is the final read result of the memory cell from which information is to be read. On the other hand, the enhancement-type or weak-depletion-type MI in the memory cell array M-ARY is used.
Since the SFET cannot cut off the DC path as in the case of the complete enhancement type MISFET, the common data line CD is used during standby to reduce power consumption.
It is preferable to lower the power supply potential Vcc 'to the ground potential Vss.
At the time of standby, it is desirable to cut the DC paths of the sense amplifier and the differential amplifier by a CE signal (chip-enable signal). As a result, current consumption during standby is reduced, and power consumption can be reduced. Next, a method of writing information to the memory cells of the vertical ROM according to the present embodiment will be described. First, as shown in FIG. 2, after a surface of a semiconductor substrate 1 such as a p-type Si substrate is selectively thermally oxidized to form a field insulating film 2 made of, for example, an SiO ₂ film, and then a device isolation is performed. By thermally oxidizing the surface of the active region surrounded by the field insulating film, a gate insulating film 3 such as a SiO ₂ film is formed. Next, channel doping by ion implantation of, for example, arsenic (As) is performed on the entire surface of the active region of the semiconductor substrate 1 through the gate insulating film 3 to obtain N ^−.
A type impurity layer 4 is formed. As a result, information “0” is written to all the memory cells of the memory cell array M-ARY. The implantation energy of this ion implantation is, for example, about 100 KeV, and the implantation dose is, for example, 2.
It should be about 4 × 10 ¹² / cm ² . Next, as shown in FIG. 3, for example, the CVD method (chemical va
For example, after a polycrystalline Si film is formed on the entire surface by a per deposition method, the polycrystalline Si film is patterned into a predetermined shape to form word lines W ₁ , W ₂ , and W ₃ constituting a gate electrode.
Etc. are formed. Next, an n-type impurity such as phosphorus (P) is ion-implanted into the semiconductor substrate 1 using these word lines W ₁ , W ₂ , W _3, etc. as a mask, and further, for example, over the entire surface of the semiconductor substrate 1. After forming a SiO ₂ film by the CVD method, RIE (Reactive Ion Etching) is performed to form a sidewall SW beside the word line. Further, by using the sidewall SW as a mask, an n-type impurity such as arsenic (As) is doped into the surface of the semiconductor substrate 1 to form, for example, an n ⁺ -type semiconductor region 5 constituting a source region and a drain region of the MISFET. Are formed respectively. The semiconductor region 5 constituting the source / drain region includes an n ⁺ type region and an n ⁻ type region,
Lightly Doped Drain structure is formed. As a result, MISFETs composed of the gate electrodes W ₁ , W ₂ , W ₃ and the n ⁺ type semiconductor region 5 are respectively formed, and the MISFETs are all formed in a depletion type by the channel doping of arsenic (As). You. The depletion-type MISFET exhibits characteristics as shown in FIG. That is, as shown by a curve 6A in FIG. 6, the first operating potential (0 V)
Turns on the transistor. In the figure, _VGS is a gate-source voltage, and _IDS is a drain current. Although only three MISFETs Q ₁ , Q ₂ and Q ₃ are shown here, the MISFET of the memory cell is represented,
The ET is formed in a matrix. Next, an interlayer insulating film 6 such as a PSG film is formed on the entire surface by, for example, CVD. Next, after a predetermined portion of the interlayer insulating film 6 is removed by etching to form a predetermined contact hole, for example, an Al film is formed on the entire surface by a sputtering method, an evaporation method, or the like, and then the Al film is patterned into a predetermined shape. Then, an Al wiring 7 serving as a data line is formed through the contact hole. Next, as shown in FIG. 5, to form MISFET constituting the memory cell to be written, for example, information "1", the photoresist 8 part has openings corresponding example to MISFET Q ₂ on the surface of the interlayer insulating film 6 . Thereafter, the interlayer insulating film 6 by using the photoresist 5 as a mask, the gate electrode W _2, a small mass a p-type impurity, for example, implantation energy than via the gate insulating film 3, for example, phosphorus, such as boron
180 KeV, of the MISFET Q ₂ by ion implantation at Tozu of 1 × 10 ¹³ / cm ² implant by performing channel doping in the channel region, the MISFET Q n has been introduced into the channel portion of the ₂ ^- type impurity layer 4 The n-type of phosphorus (P), which is an impurity, is negated, and the MISFET is enhanced or weakly depleted to form a p-type impurity layer 9, thereby forming, for example, information "1".
Write. The enhancement type MISFETQ
₂ shows the characteristics shown in FIG. That is, as shown by a curve 6B in FIG. 6, at the first operating potential (0 V), the MISFET
Q ₂ does not operate, and operates in the second operating potential (5 V),
The threshold value of MISFETQ ₂ has changed. Further, even if the p-type impurity due to mask misalignment during the channel doping of the p-type impurity is introduced for example into a channel section of the MISFET Q _1, there is no effect on the depletion characteristics of the MISFET Q ₁ if a part. FIG. 7 is a plan view corresponding to FIG. 5, and shows a memory cell array of the present invention. In the figure, MIFETs Q ₁ and Q ₂ are formed in a depletion type, and their MISFETs are connected in series.
As described above, the Al wiring 7 which is the final process of the vertical ROM manufacturing process is used.
Since information can be written after the formation, the turnaround time can be reduced, and
Its reliability can be improved. The ion implantation of boron for writing information can be performed immediately after the formation of the interlayer insulating film 6 or after the formation of the source / drain regions. As described above, the invention made by the inventor has been specifically described based on the embodiment. However, the present invention is not limited to the embodiment, and may be variously modified without departing from the gist of the invention. Of course. For example, the present invention can be applied to various semiconductor integrated circuit devices such as a one-chip microcomputer having a vertical ROM. Also, for example, it has not only a gate electrode made of polycrystalline silicon but also a silicide or polycide gate electrode.
It is also applicable to vertical ROM made of MISFET. [Effects of the Invention] Of the inventions disclosed in the present application, effects obtained by typical ones will be briefly described as follows. That is, it is possible to reduce the turnaround time of a semiconductor memory device in which desired information is written in a memory cell and improve the reliability of writing information.

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a circuit diagram showing a circuit configuration of a vertical ROM according to an embodiment of the present invention. FIGS. 2 to 5 show information stored in memory cells of the vertical ROM shown in FIG. FIG. 6 is a cross-sectional view for explaining a method of writing data in the order of steps, FIG. 6 is a graph showing characteristics of a MISFET constituting a ROM of the present invention, FIG. 7 is a plan view of a memory cell corresponding to FIG. FIG. 8 shows the gate length (L) of the MISFET constituting the ROM of the present invention.
FIG. 9 is a graph showing characteristics of g) and a threshold voltage (Vth). In the drawing, 1 ... semiconductor substrate, 2 ... field insulating film, 3
...... Gate insulating film, 4 ... impurity layer, 5 ... semiconductor region, 6 ... interlayer insulating film, 7 ... aluminum wiring, 8 ... photoresist, XDCR ... row address decoder, DCR ...
Decoder, YDCR ...... column address decoder, W _1, W _2, etc. ...... word lines, D _1, D _2, etc. ...... data lines, Q _1, Q ₂ etc. ...... MISF
ET, M-ARY... Memory cell array, SA, SAd... Sense amplifier, SW... Sidewall, DUMMY-M-ARY... Dummy memory cell array.

   ────────────────────────────────────────────────── ─── Continuation of front page       (56) References JP-A-56-150860 (JP, A)                 JP-A-60-20562 (JP, A)                 JP-A-62-46556 (JP, A)                 JP-A-62-20367 (JP, A)                 JP-A-58-111364 (JP, A)                 JP-A-58-56468 (JP, A)

Claims (1)

(57) [Claims] A method of manufacturing a semiconductor memory device constituting a vertical ROM includes a step of preparing a semiconductor substrate having a first conductivity type main surface, and a step of preparing a semiconductor cell having the main surface of the first conductivity type. Forming a plurality of depletion-type MISFETs having a first threshold value lower than a first operating potential of the semiconductor memory device; forming an interlayer insulating film covering the plurality of MISFETs; At least one selected from MISFET
The threshold voltage of the MISFET is changed from the first threshold voltage to the second operating potential of the semiconductor memory device, which is higher than the first operating potential, and a second threshold voltage different from the first threshold is changed. In order to set the threshold voltage, through the interlayer insulating film and the gate electrode of the at least one selected MISFET, to the channel portion of the at least one selected MISFET,
A step of introducing boron to enhance the channel portion, and suppressing the short channel effect by the enhancement, thereby forming a memory cell.
Is formed shorter than the gate length of the other MISFETs. 2. A method of manufacturing a semiconductor memory device forming a vertical ROM includes a step of preparing a semiconductor substrate having at least a main surface having a first conductivity type, and an step of forming an n-type impurity in a region of the main surface where a memory cell is to be formed. Introducing and depleting; forming a plurality of n-type MISFETs in the region; forming an interlayer insulating film covering the plurality of MISFETs; and at least one selected from the plurality of MISFETs. One MI
A step of introducing boron from above the interlayer insulating film into the channel portion of the SFET to enhance the channel portion, and by suppressing the short channel effect by the enhancement, the MISFET constituting the memory cell
Is formed shorter than the gate length of the other MISFETs. 3. 3. The method according to claim 2, wherein the step of enhancing is performed to make a threshold voltage of the at least one selected MISFET higher than a threshold voltage of another MISFET. A method for manufacturing a semiconductor storage device. 4. The impurity introduced in the depletion process is arsenic, is introduced at an implantation energy of about 100 KeV, and its dose is about 2.4 × 10 ¹² atoms / cm ^2. 3. A method for manufacturing a semiconductor memory device according to claim 2. 5. 3. The method according to claim 2, wherein in the step of enhancing, boron is introduced at a driving energy of about 180 KeV.