JP2820701B2 - Conversion method to binary - Google Patents

Description

The present invention relates to a method for converting a decimal number into a binary number for processing in an information processing apparatus.

[Conventional technology]

FIG. 3 is a block diagram of a main part of a conventional information processing apparatus. In FIG. 3, 1 is an arithmetic unit (ALU), 2 is a multiplication unit (MPY), 3 is a register file, and 4 is an X-
Bus (X-Bus), 5 is Y bus (Y-Bus), 6 is Z bus (Z-Bus)
Bus).

Next, the operation of the firmware of the information processing apparatus will be described. If a 10-digit decimal number is converted to a binary number, the result is a 32-bit binary number.

For example, it is assumed that conversion of 4,294,967,296 (decimal number) → 111... 11 (binary number) is performed.

4,294,967,296 = 4 × 10 ⁹ + 2 × 10 ⁸ + 9 × 10 ⁷ + 4 × 10 ⁶ + 9 × 10 ⁵ + 6 × 10 ⁴ + 7 × 10 ³ + 2 × 10 ² + 9 × 10 ¹ + 6 × 10 ⁰ (upper digit → lower digit) = 6 × 10 ⁰ + 9 × 10 ¹ + 2 × 10 ² + 7 × 10 ³ + 6 × 10 ⁴ + 9 × 10 ⁵ + 4 × 10 ⁶ + 9 × 10 ⁷ + 2 × 10 ⁸ + 4 × 10 ⁹ (lower digit → higher digit) ... .. (1), each coefficient is represented by a 4-bit binary number, and the number of digits is represented by a required bit binary number. The product of these is obtained for each digit, and the sum of the binary numbers is calculated. Take decimal number 2
Convert to a decimal number.

When the above is expressed by a general formula, a 10-digit decimal number is a ₉ a ₈ a ₇ a
_When expressed by ₆ a ₅ a ₄ a ₃ a ₂ a ₁ a ₀ S (where S: sign), the arithmetic unit 1 extracts a _i → A _i . Where i = 0
At 9, A is a 4-bit binary number.

Next, the multiplication unit 2 multiplies A _i by B _i . B _i
This is a binary number corresponding to decimal 10 ⁱ (i = 0 to 9). This calculation is performed 10 times for each digit, each product A _i × B _i is stored in the register unit 3, and then 演算 A _i × B _i is calculated by the arithmetic unit 1, that is,
A ₀ × B ₀ (10 decimal 10 ⁰ phase etc.) + A ₁ × B ₁ (10 decimal 10 ¹ equality) + ......
+ A ₉ × B ₉ (10 ⁹ decimal)

After that, exception processing is performed by the arithmetic unit 1 and 2
At the time of base conversion, if the sign is negative, it is converted to complement.

[Problems to be solved by the invention]

The conventional firmware has a problem that the processing time is long to convert a decimal number into a binary number.

The present invention has been made in order to solve the above-mentioned problems, and speeds up the conversion from decimal numbers to binary numbers.
It is an object of the present invention to provide a method of converting a decimal packed data whose binary data exceeds 32 bits into a binary number which can be easily processed.

[Means for solving the problem]

In the present invention, as shown in FIG. 2, in decimal given n digit _{a n a n-1 ... a} i a i-1 ... arithmetic unit 1 a ₁ a ₀ for each i digits 10 Base numbers (a _n × 10 ⁿ + ...), (… + a _2i × 10 ²ⁱ ),
(A _2i-1 × 10 ^2i-1 + ... + a _i × 10 ⁱ ) and (a _i-1 × 10 ^i-1 + ... + a ₁ × 10 ¹ + a ₀ × 10 ⁰ ) 3 are sequentially stored in the register unit 3, and the binary numbers (A _n +...), (. … A _3i ), (A _3i-1 + …… A _2i ),
(A _2i-1 + A _i ) and (A _i-1 +... A ₁ + A ₀ ) are sequentially batch-converted and stored in the register unit 3. Next, each decimal number previously stored in the register unit 3...
10 ^3i, 10 ^2i, 10 ⁱ each binary number corresponds ......, B _3i, B _2i, the B _i respectively taken out, sequentially multiplies in binary and multiplication unit 2 for each i digits, ..., (A _{4i -1} + _A3i ) x _B3i , ( _A3i-1 + ... _A2i ) x
B _2i , (A _2i-1 +... + A _{i + 1} + A _i ) B _i are obtained and stored in the register unit 3 sequentially, and all these binary numbers and the binary numbers (A _{i− 1} +... A _i + A ₀ ) is taken out from the register unit 3 and the arithmetic unit 3 sums them up... + (A _4i-1 × B _3i +... + A _3i × B _3i ) + (A _3i-1 × _{B 2i + ... + A 2i ×} B 2i) + (A i-1 + ... + A 1 +
A ₀ ) was obtained to obtain a binary number.

[Action]

A dedicated i-digit binary conversion unit 8 is provided, and the higher-order i-digit number (a _2i-1 × 10 ^2i-1 +... + A _i × 10 ⁱ ) is converted into a binary number, and (A _{2i -1} +... A _i ) This (A _2i + ...
When + A _i) in are multiplied by 10 ⁱ corresponding binary B _i by the multiplier unit 2, the lower i digits in binary conversion unit 8 in parallel ^{_{(a i-1 × 10 i}} -1 + ... + a 1 10 ¹ + a ₀ 10 ⁰ ) is converted to a binary number. Thus, since parallel processing is performed n / i times, when a decimal number having a large number of digits n is converted into a binary number, the processing speed is increased, and processing can be performed in a short time.

〔Example〕

 Hereinafter, the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram of a main part of an information processing apparatus in which the present invention is executed. In FIG.
U), 2 is a multiplier unit (MPY), 3 is a register file, 4 is an X bus (X-Bus), 5 is a Y bus (Y-Bus), 6 is a Z bus (Z-Bus), and 8 is 2 It is a radix conversion unit. 2
The decimal conversion unit 8 is a functional integrated circuit (Format Convert LSI) that converts a decimal number into a binary number for every five digits of a decimal number.

Each input side of the arithmetic unit 1, the multiplication unit 2 and the binary number conversion unit 8 is connected to the X bus 4 and the Y bus 5, and the output side thereof is connected to the Z bus 6. The operation results of the operation unit 1, the multiplication unit 2 and the binary conversion unit 8 are applied to the register unit 3 via the Z bus 6 and stored there. The output side of the register unit 3 is connected to the X bus 4 and the Y bus 5, and the arithmetic unit 1, the multiplication unit 2 and the binary number conversion unit 8 receive necessary data from the register unit 3.

Next, the operation of the firmware in this apparatus will be described with reference to FIG.

Now 10-digit decimal number a ₉ a ₈ a ₇ a ₆ a ₅ a ₄ a ₃ a ₂ a ₁ a ₀ S (where S: sign) is 3
It shall be converted to a 2-bit binary number.

In step S ₁ , the upper five digits of data a ₉ a ₈ a ₇ a ₆ a ₅ of the decimal number are extracted from the register unit 3, and the binary number conversion unit 8 performs the binary conversion in a lump. That is, A ₉ × B ₄ + A ₈ × B ₃ + A ₇ × B ₂ + A ₆ × B ₁ + A ₅ × B ₀ are obtained. Here, A _i (i = 5 to 9) is a corresponding binary number of a _i (i = 5 to 9), and B _i (i = 0 to 4) is a corresponding binary number of 10 ⁱ (i = 0 to 4). It is. In step S ₂ stores the _{A 9 × B 4 + A 8} × B 3 + ... + A 5 × B 0 of register unit 3 to the work register (WR10).

Here, at the same time, the 32-bit code performs a binary arithmetic overflow check. In the overflow check, the binary number conversion unit 8 automatically checks and outputs a judgment signal. If there is an overflow, the sequencer jumps to error processing.

In step S _3, since the binary B ₅ corresponding to decimal 10 ⁵ in advance register unit 3 of the work register (WR0) are recorded, A ₉ × from WR10 register unit 3
B ₄ + A ₈ × B ₃ + ... A ₅ × B ₀ and B ₅ (corresponding to 10 ⁵ ) are extracted from WR0 and input to the multiplication unit 2 for multiplication (A ₉ × B ₄ + A ₈ × B ₃ + ... + A ₅ × B ₀ ) × B ₅ = A ₉ × B ₄ × B ₅ + A ₈ × B ₃ × B ₅ + …… + A ₅ × B ₀ × B ₅ = A ₉ × B ₉ + A ₈ × B ₈ +… ... + A ₅ × B ₅ is performed. This is obtained by converting a decimal number a ₉ × 10 ⁹ + a ₈ × 10 ⁸ +... + A ₅ × 10 ⁵ into a binary number. At this time, as the parallel processing, the binary number conversion unit 8 extracts the lower five digits of the decimal number data a ₄ a ₃ a ₂ a ₁ a ₀ from the register unit 3,
Performs radix conversion. That is, A ₄ × B ₄ + A ₃ × B ₃ + A ₂ × B ₂ + A ₁ × B ₁ + A ₀ × B ₀ are obtained. Here in A _{i (i} = 0~4) corresponding binary _{a i (i = 0~4),} B i (i = 0~4) corresponding binary 10 ^{i (i} = 0~4) It is. Here, at the same time, a check for a decimal data exception is also automatically made in the binary conversion unit 8, and if there is an exception, the sequencer jumps to error processing.

In step S _4, and stores the _{A 4 × B 4 + A 3} × B 3 + ...... + A 0 × B 0 of register unit to work register WR10.

In step S _5, the results of the top five digits of the first half of the step S ₃
Store A ₉ × B ₉ + A ₈ × B ₈ +... + A ₅ × B ₅ in the work register WR7 of the register unit.

In step _{S 6, A 9 × B 9} + A 8 × B in Step S ₅ from the work register WR7 of register units _{3 8 + ...... + A 5 ×} B 5
WR of A ₄ × B ₄ + A ₃ × B ₃ +... + A ₀ × B ₀ of step S ₄
Each of them is taken out from 10 and input to the arithmetic unit 1 to add them. That is, A ₉ × B ₉ +... + A ₅ × B ₅ + A ₄ × B ₄ +
... A ₀ × B ₀ is obtained, a target binary number which is a sum of upper 5 digits and lower 5 digits is obtained, and a work register of the register unit 3 is obtained.
Store in WR10. As a result, a 10-digit decimal number is converted into a 32-bit binary number in a short time with a small number of executions.

Note that when converting a 20-digit decimal number to a 64-bit binary number,
In advance, the decimal 10
By recording the binary numbers B ₁₀ and B ₂₀ corresponding to ¹⁰ and 10 ²⁰ , respectively, it is possible to obtain a product in the same manner as described above and convert the decimal number into a binary number in high-speed processing.

〔The invention's effect〕

As described above, according to the present invention, decimal given n digit _{a n a n-1 ... a} i a i-1 ... a 10 in decimal arithmetic unit every the ₁ a ₀ i digits (A _n × 10 ⁿ + ……), ……, (… + a _2i × 1
0 ²ⁱ ), (a _2i-1 × 10 ^2i-1 + ... + a _i × 10 ⁱ ), (a _i-1 × 10
^i-1 +... + a ₁ × 10 ¹ + a ₀ × 10 ⁰ ), store them in the register unit, and sequentially take out the decimal numbers for each i-digit number from the register unit, and convert them into binary number conversion units. , A binary number (A _n +...) For each corresponding i-digit number,
(… A _3i ), (A _3i-1 +… A _2i ), (A _2i-1 +… A _i ), (A
_i-1 +... A ₁ + A ₀ ) are sequentially and collectively converted and stored in the register unit. Next, each of the decimal numbers stored in the register unit in advance,..., 10 ³ⁱ , 10 ²ⁱ , and 2 corresponding to 10 ⁱ
Decimal ^{......, B 3i, B 2i,} B respectively taken out, 2 for each i digits
.., (A _4i-1 +... A _3i ) × B _3i , (A _3i-1 +... + A _2i )
× B _2i , (A _2i-1 +... + A _{i + 1} + A _i ) × B _i are obtained, and sequentially stored in the register unit. All of these binary numbers and the binary numbers (A _{i -1} +... A ₁ + A ₀ ) is taken out from the register unit, and the sum is calculated by the arithmetic unit... + (A _4i-1 × B _3i +... + A _3i × B _3i ) + (A _3i-1 × B _2i
+ ... + A _2i × B _2i ) + (A _i-1 + ... + A ₁ + A ₀ )
Since a decimal number is obtained, even a decimal number having a large number of digits can be rapidly converted to a binary number in a short time.

[Brief description of the drawings]

FIG. 1 is a block diagram of an information processing apparatus in which the present invention is implemented, FIG. 2 is a flowchart for explaining the operation of the present invention, and FIG. 3 is a block diagram of a conventional apparatus. 1 arithmetic unit, 2 multiplication unit, 3 register unit, 4, 5, 6 bus, 8 binary conversion unit.

Claims (1)

(57) [Claims] 1. A decimal given n digit _{a n a n-1 ... a} i a i-1 ... 1 in the arithmetic unit of a ₁ a ₀ for each i digits
(A _n × 10 ⁿ + ...), ..., (... + a _2i × 10 ²ⁱ ), (a
_2i-1 × 10 ^2i-1 + ... + a _i × 10 ⁱ ), (a _i-1 × 10 ^i-1 + ... + a _i
× 10 ¹ + a ₀ × 10 ⁰ ) and storing them in the register unit respectively. Then, these decimal numbers for each i-digit number are sequentially taken out from the register unit, and are respectively handled by the binary number conversion unit. Binary numbers (A _n + ...), (... A _3i ), (A
_3i-1 +... A _2i ), (A _2i-1 + A _i ), (A _i-1 +... A ₁ + A ₀ ), and sequentially and collectively convert them into the register unit. Each 10 stored in the register unit
Binary numbers ……, 10 ³ⁱ , 10 ²ⁱ , and binary numbers corresponding to 10 ⁱ ……, B _3i ,
B _2i and B _i are respectively taken out and sequentially multiplied by a binary number for each of the i-digit numbers by a multiplication unit,..., (A _4i-1 +... + A _3i ) × B
_3i , (A _3i-1 + ... + A _2i ) × B _2i , (A _2i-1 + ... + A _{i + 1} +
A _i ) × B _i , and sequentially storing them in the register unit. Then, all these binary numbers and the binary numbers (A _i-1 +... A _i + A ₀ ) of the least significant i digits are obtained by: It is taken out from the register unit and summed up by the arithmetic unit... + (A _4i-1 × B _3i
+… + A _3i × B _3i ) + (A _3i-1 × B _2i +… + A _2i × B _2i ) +
(A _i-1 +... + A ₁ + A ₀ ) to obtain a binary number.