JP2822376B2 - Digital filter - Google Patents

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a digital filter used for thinning / interpolating digital video signals. SUMMARY OF THE INVENTION The present invention relates to a digital filter, in which a washing machine is provided on the input side of a coefficient multiplier to wash input signals having different time phases, so that an efficient filter device can be configured. is there. [Related Art] For example, when processing a digital video signal, it is necessary to perform data thinning / interpolation for changing a sampling rate. A digital filter is used to perform such thinning / interpolation satisfactorily. That is, for example, when obtaining an output digital signal interpolated 3: 4 as shown in FIG. 7B from an input digital signal as shown in FIG. 7A, an impulse response of 27 taps as shown in FIG. By performing the convolution, a good interpolation can be performed. Actually, the input signal is A
And the required output signal only needs to be obtained at the phase B, so that the convolution operation is performed only for the impulse responses shown in FIGS. D to G according to the phase of the output signal. Good. Therefore, an apparatus as shown in FIG. 8 can be considered. In the figure, a digital signal supplied to an input terminal (80) is supplied to a sampling rate conversion circuit (81), and as shown in FIG. The signal is converted into a signal in which a blank (□) is inserted, and this signal is supplied to adders (83a) to (83j) through multipliers (82a) to (82j). This adder (83a) ~
The output of (83j) is one sample period D of the output signal.
Through the delay circuits (84a) to (84j) of the next stage.
b) to (83j), the output of the adder (83j) is taken out to the output terminal (85) through the delay circuit (84j). And further with respect to the above-described multiplier (82a) ~ (82j), for example, read only memory (ROM) (86) the impulse coefficients a ₀ ~a ₁₃ as shown in FIG every sample period of the output signal from the Supplied in a circuit. As a result, the above-described D to G are sequentially applied to the output terminal (85).
An output signal obtained by convoluting the impulse response is obtained. That is, in the above-described apparatus, signals □, X ₀ , X ₁ , X ₂ , □, X ₃ ... (□ indicates a blank) are output from the conversion circuit (81) as shown in FIG. 10A. In the case, the multipliers (82a) to (8
2j) outputs a multiplied value as shown in FIG. These values are supplied to a pipeline adder composed of adders (83a) to (83j) and delay circuits (84a) to (84j), so that the output terminal (85) is indicated by a broken line in the drawing. The addition signals Y ₀ , Y ₁ , Y ₂ ... Of the multiplication values in the oblique directions are extracted. This makes it possible to perform the convolution calculation of the impulse coefficients a ₀ ~a ₁₃ described above. However, in the above-described apparatus, since the signal from the conversion circuit (81) outputs a blank (“0”) every four samples, each arithmetic circuit (multiplier, adder) performs one period every four sample periods ( (1/4 of the entire period) is wasted. However, the conventional device could not eliminate this waste. For example, when obtaining an output digital signal decimated 5: 4 as shown in FIG. 11B from an input digital signal as shown in FIG. 11A, an impulse response of 35 taps as shown in FIG. Can be satisfactorily thinned out. In this case, the convolution operation may be performed only for the impulse responses shown in FIGS. D to G according to the phase of the output signal, as in the case of the above-described interpolation. However, in this case, if the convolution operation for such thinning is to be performed with the same configuration as the above-described interpolation filter, a signal as shown in FIG. 12 needs to be output from each multiplier. . Therefore, in order to obtain such an output signal, not all signals are given at the same timing as shown in FIG. It has to be supplied in a different pattern, and supply of such an input signal has not been easily realized. [Problems to be Solved by the Invention] As described above, in the conventional technology, there are problems that a useless operation period occurs and input signals cannot be easily supplied. [Means for Solving the Problems] According to the present invention, input signals (terminals (1) and (11)) are supplied to multipliers (5b) to (5j) (15a) to (15i) in each stage, respectively. Multiplied by a predetermined coefficient (ROM (9) (19)), and the multiplied value is sequentially delayed by the delay means (circuits (7b) to (7j) (17a) to
Add via (17i) (6b)-(6j) (16a)-(16i)
In the digital filter configured to perform interpolation or thinning of the input signal (output terminals (8) and (18)), the input signal is arbitrarily delayed in advance (circuits (3) and (3a)).
To (3c)) are supplied by a plurality of signal systems A and B having different time phases, and selectors (4b) to (4j) (14a) to (14j) are provided on the input side of the multiplier. By selecting the signals having different time phases, each of which is obtained by arbitrarily delaying the input signal by the selector, the timing when the multiplier is not used is aligned with the predetermined time phase, and the multiplier is not used. A digital filter provided with only the delay means at the position to perform the sequential addition. [Operation] According to this, it is possible to arbitrarily modify the circuit configuration by sequentially selecting input signals having different time phases at a predetermined timing, thereby achieving a good digital operation without wasting the operation of the arithmetic circuit. A filter can be formed. Embodiment FIG. 1 shows a case where a 3: 4 interpolation filter is configured, for example. In this figure, a digital signal supplied to an input terminal (1) is supplied to the above-mentioned sampling rate conversion circuit (2) to be a signal in which a blank of one data is inserted for every three data, and this signal is output signal. Is supplied to the delay circuit (3) of one sample period D. The signal A from the delay circuit (3) and the signal B from the conversion circuit (2) are respectively used as selectors (4b) to (4d) and (4f).
To (4h) and (4j), and the selectors (4b) to (4j)
The signal selected in j) is a multiplier (5b) to (5d), (5f)
Adders (6b) through (6d) through (5j) through (5j)
f) to (6h) and (6j). This adder (6b)
To (6h) are each one sample period D of the input signal.
Next stage adder (6c) through delay circuits (7b) to (7j)
(6j), and the output of the adder (6j) is taken out to the output terminal (8) through the delay circuit (7j). Then, for the multipliers (5b) to (5j) described above,
For example, with a read-only memory (ROM) (9) Impulse coefficients a ₀ ~a ₁₃ and 0 as shown in FIG every sample period of the output signal from is supplied cyclically, ROM
The signal from (9) is supplied to the selectors (4b) to (4j) and switched to the signal A side and the signal B side, respectively. Therefore, in this device, a multiplier (5b) ~ multiplied value as respectively shown in FIG. 2 C from (5j) is outputted each sample period t _0, t ₁ ... each, these values adder (6b )
To (6j) and a pipeline adder composed of delay circuits (7a) to (7j), an output terminal (8) takes out a sum signal of a multiplication value indicated by a broken line in the figure. That is, in the above-described device, the input signal X is
The output signal Y passed through the circuit shown in FIG.
This is equivalent to the case where a signal delayed by the sample period is used to pass through the circuit shown in FIG. B, whereby an arithmetic circuit such as a multiplier can be shifted by one stage. Therefore, in FIG. 10 described in the prior art, for example, the multiplier time _{t 3 (82a) ~ (82c} ) calculates the one sample period of time t ₄ by using the delaying signal A multiplier (82b) ~ can be shifted in the calculation of (82d), can be shifted to the operation of the same way of the multiplier time t ₂ by (82a) of the multiplier time t ₃ the operation of (82b) (82b) (82c ) ,
Furthermore it is possible to shift the operation of the multiplier time t ₂ the operation (82b) of the time t ₁ of the multiplier (82a). Thus, the operation shown in FIG. 2C can be realized by the above-described device, and convolution operation of impulse coefficients a _{0 to} a ₁₃ equivalent to the conventional one can be performed. In this case, as is clear from the figure, the signals corresponding to the conventional multipliers (82a), (82e), and (82i) are all blank (□), and therefore, the circuit for performing these operations is deleted. Thus, useless operation of the arithmetic circuit can be eliminated. In this way, according to this device, the circuit configuration and the like can be arbitrarily modified by sequentially selecting input signals having different time phases at a predetermined timing, thereby achieving a good digital operation without wasting the operation of the arithmetic circuit. A filter can be formed. FIG. 4 shows a case where a 5: 4 thinning filter is formed, for example. In this figure, digital signals supplied to an input terminal (11) are supplied to delay circuits (13a) to (13c) each having one sample period D of an output signal. The input / output signals are supplied to the sampling rate conversion circuits (12a) to (12c), respectively. In the conversion circuit (12), as shown in FIG. 5, five data of the input signal are converted into two signals A and B of four data during the same elapsed time τ. The signals A and B from the conversion circuit (12a) are supplied to selectors (14a) to (14d), respectively, and the signals A and B from the conversion circuit (12b) are supplied to selectors (14e) to (14h), respectively. The signals A and B from the conversion circuit (12c) are supplied to the selector (14i), and the signals selected by the selectors (14a) to (14i) are multiplied by the multipliers (15a) to (15i). ) Are supplied to adders (16a) to (16i). This adder (16a) ~
The output of (16h) is one sample period D of the input signal.
Adders (16b) through delay circuits (17a) through (17h)
(16i), the output of the adder (16i) is taken out to the output terminal (18) through the delay circuit (17i). And further with respect to the above-described multiplier (15a) ~ (15i), for example, read only memory (ROM) (19) the impulse coefficients b _0, as shown in FIG every sample period of the output signal from the ~b ₁₇ and 0 is supplied cyclically and R
The signal from the OM (19) is supplied to the selectors (14a) to (14i) and switched to the signal A and the signal B, respectively. This makes it very easy to supply an input signal or the like corresponding to the output signal shown in FIG. That is, in the above-described apparatus, for example, a basic circuit configuration as shown in FIGS. 6A to 6F is newly created, and a digital filter such as an interpolation / thinning filter is extremely efficiently and simply configured by combining them. Can be realized. Note that the above example describes the case of performing 3: 4 and 5: 4 interpolation / decimation, but these can be applied to other ratios and also to digital filters for other uses. Can also. Also, the order of the filter is not limited to the above example, and can be arbitrarily determined. Further, in the above example, the case where the impulse coefficients of the filters are symmetric has been described, but this can be similarly applied to other types of filters. [Effects of the Invention] According to the present invention, the circuit configuration and the like can be arbitrarily modified by sequentially selecting input signals having different time phases at a predetermined timing, so that the operation of the arithmetic circuit is not wasted. Thus, a good digital filter can be formed.

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a block diagram of an example of the present invention, FIGS. 2 and 3 are diagrams for explaining the same, and FIGS. 4 to 6 are diagrams for explaining other examples. FIGS. 7 to 12 are views for explaining the prior art. (1) is an input terminal, (2) is a sampling rate conversion circuit, (3) and (7a) to (7j) are delay circuits, and (4b) to (4)
j) is a selector, (5b) to (5j) are multipliers, and (6b) to (6)
j) is an adder, (8) is an output terminal, and (9) is a read-only memory.

Claims (1)

(57) [Claims] An input signal is supplied to a multiplier at each stage and multiplied by a predetermined coefficient, and the multiplied values are sequentially added through delay means to perform interpolation or thinning of the input signal. The input signal is supplied in advance in a plurality of signal systems having different time phases which are arbitrarily delayed in advance, and a selector is provided on an input side of the multiplier, and the input signal is arbitrarily delayed in each of the time phases. When different signals are selected by the selector, the timing when the multiplier is not used is aligned with a predetermined time phase, and only the delay unit is provided at a position where the multiplier is not used, and the sequential operation is performed. Digital filter that performs addition.