JP2822577B2 - Square root arithmetic unit - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a square root computing device that can quickly obtain an approximate value of a square root.

2. Description of the Related Art Conventionally, as a device for performing a square root operation, a device that calculates a square root by a combination of arithmetic and logical operations, a ROM,
(Read-only memory) has been developed in which a data table is provided to calculate a square root. As an example of these, Japanese Patent Application Laid-Open No. 62-138828 corresponding to the above-mentioned item discloses an apparatus which calculates a square root approximation value by binary integer calculation combining bit extraction, addition, subtraction, and bit shift. ing. Also, in Japanese Patent Application No. 62-182841, corresponding to the above-mentioned item, an approximate value corresponding to input data is indexed from a data table in which a provisional square root value is stored, and the approximate value is converged by a recurrence formula. In this case, the true square root is calculated.

[Problems to be Solved by the Invention] The above-described apparatus has a drawback that high-speed operation cannot be performed because various combinations of binary integer calculations are performed. Further, the apparatus described in the above-mentioned section must have a data table for storing the approximate value, and therefore, has a disadvantage that the circuit scale becomes large and disadvantageous when implementing the LSI.

SUMMARY OF THE INVENTION The present invention has been made in view of the above circumstances, and has as its object to provide a square root arithmetic device capable of performing a high-speed operation while having a small circuit scale.

[Means for Solving the Problems] The present invention relates to a square root operation device for square rooting binary input data composed of an exponent part and a mantissa part and outputting the squared data as square root data. To
First conversion means for converting the first converted data a ₁ taking a value less than 0.25 or more, the data a ₁ of the first is 0.25 ≦ a ₁ <
If 0.5, the first data a ₁ And No. by substituting the equation, and outputs the calculation result as a second conversion data, and the first data a ₁ is
When 0.5 ≦ a ₁ <1, the first data a ₁ is And square root by substituting into the formula of (1) and outputting the calculation result as the second conversion data; and converting the exponent part of the input data into the exponent part of the square root data, Second conversion means for forming the square root data by combining the significand with the mantissa part of the conversion data.

According to the present invention, the exponent part and the mantissa part of the input data are individually converted into data, and these are combined again to obtain an approximate square root value. Thereby, a high-speed square root operation is realized.

Hereinafter, embodiments of the present invention will be described with reference to the drawings. FIG. 1 is a block diagram showing a configuration of a square root operation device according to an embodiment of the present invention. In this figure, 1
Is a register file composed of registers R1 to R4. Register R1 is the input data used for the square root calculation
a ₀ is temporarily stored. 2 is the input data a ₀ converted to the first conversion data
a1 is a _first converter that converts the data to ₁ and outputs it. The first converter 2 is for the contents of the input data a ₀ to convert the data a ₀ so as not to fall bit 0.25 ≦ a ₁ <1 comprising first conversion data a ₁ range. Register R2 is temporarily stores the first converted data a _1. Reference numeral 3 denotes an adder / subtractor / divider. The addition, subtraction, multiplication, and division adder 3 is obtained by approximating the first square value of the converted data a ₁ calculation (described later), and outputs the result as intermediate data a _2. Register R3 is for temporarily storing intermediate data a _2. 4 is a second converter. The second transducer 4 receives the input data a ₀ and the intermediate data a ₂ performs data conversion will be described later, thereby outputting a square root data a ₃ obtained.
Register R4 temporarily stores the square root data a _3. The operations of the above-described units are controlled by a timing clock supplied from a control circuit (not shown).

It will now be described with reference to Figure 2 the data format of the input data a _0. The input data a ₀ is the exponent in binary, that format is specified in floating point format shown in Figure 2. The example of the format shown in this figure is a 32-bit single-precision data format of the ANSI / IEEE specification. In this figure, s is the input data
a code indicating the polarities of a _0, represents the positive "0" represents a negative "1". e ₀ is the exponent part (30- to 23-bit 8-bit length), f ₀
Is a mantissa (23 bits of 22 to 0 bits). The value of the input data a ₀ to be expressed in such a data format is defined by the following general formula (1).

That is, a ₀ = (− 1) ^s 2 ^e-127 (1 · f) (1) where e is the value of the exponent part (0 <e <255), and f is the binary number below the decimal point. This is the mantissa of the bit string.

In this floating point format, for example, if the input data a ₀ is "13.5" (decimal), when displayed by the equation (1) is expressed as follows.

a ₀ = (− 1) ⁰ 2 ³ (1 · 1011) = 1101.1... binary representation Next, the square root method of the input data a ₀ described above will be described. Now, since the square root is defined for a positive value, the data in which the above-mentioned code s is "0" is handled. Further, when the equation (1) is modified separately for a case where the exponent part e ₀ of the input data a ₀ is an even number and a case where the exponent part e ₀ is an odd number, the square root in each case is expressed by the following equations (2) and (3). be able to.

Here, m = (e ₀ +126) / 2, n = (e ₀ +127) / 2,
f ′ and f ″ are mantissas representing the values of the respective square roots.

By the way, the least significant bit of e ₀ +126 is always “0” if e ₀ is even, and (e ₀ +126) / 2 is equivalent to ignoring the least significant bit of (e ₀ +127) / 2 It is. Therefore, if the exponent part n is obtained, it can be handled as a common exponent part. Thus, in order to determine the square root of the input data a _0, a exponent n, No. mantissa part f 'or f "and it is sufficient to bind.

Next, the configuration of the first converter 2 will be described with reference to FIG. In this figure, 2a is a selector. The selector 2a is 23 bit of input data a _0, i.e.,
When the least significant bit of the exponent part e ₀ is “0”, the preset value “126” is output. When the least significant bit is “1”, the preset value “1” is output.
25 "is output. That is, the first converter 2 is exponent e ₀ of the input data a ₀ if an even number, sets the exponent e ₁ of the first conversion data a ₁ to "126". Moreover, the exponent e ₀ of the input data a ₀ if odd, sets the exponent e ₁ of the first conversion data a ₁ to "125". First conversion data a ₁ obtained by this conversion, the following (4) is expressed by equation (5).

Exponent part e ₀ is even: a ₁ = 2 ^-1 (1 · f ₀ ) (4) where 0.5 ≦ a ₁ <1 Exponent part e ₀ is odd: a ₁ = 2 ^-2 (1 · f ₀₎ ) (5) where 0.25 ≦ a ₁ <0.5 According to such a conversion, the mantissa of the first conversion data a ₁
Since f ₀ ( _{0 to} 22 bits) remains as it is in the mantissa part f ₀ of the input data a ₀ , no bit loss occurs in the mantissa part.

Next, FIG. 4 is a diagram for explaining the function of the adder / subtractor / multiplier / divider 3. Square root addition, subtraction, multiplication, and division adder 3 performs floating-point operations by substituting the first transformed data a ₁ to an approximate equation that is given in advance, thereby obtained shown in FIG. And outputs as the intermediate data a _2. This operation, for example, the value is 0.5 ≦ a ₁ of the first conversion data a ₁ described above
When it is within the range of <1, the calculation is performed using the equation (6).

(However, 0.5 ≦ a ₁ <1) When the value of the first conversion data a _{1 is in} the range of 0.25 ≦ a ₁ <0.5, the conversion is performed using the equation (7).

(However, 0.25 ≦ a ₁ <0.5) Each of the constants in the above equations (6) and (7) is a finite decimal number that can be expressed by a binary number, and furthermore, it is considered that the operation of multiplying the constant can be easily performed. ing. Therefore, the adder / subtractor / multiplier / divider 3 is configured such that these constants are set in advance in advance, and calculate the approximation extremely quickly.

Next, the configuration of the second converter 4 will be described with reference to FIG. In this figure, 4a is an adder, adding and outputting the preset value "127" and the exponent e ₀ of the input data a _0. A shifter 4b shifts the data output from the adder 4a by one bit toward the LSB and outputs the data. According to such a configuration, the exponent part e ₀ of the input data a ₀ is set to (e ₀ +
127) into / 2, and outputs the square root data a ₃ conjugated with and the mantissa f ₁ of the intermediate data a ₂ this.

The square root operation device having the above configuration firstly operates in the register R1.
The input data a ₀ is set to. Then, the input data a _0, which is temporarily stored in the register R1 is read out and supplied to the first transducer 2 and second transducer 4. The input data a ₀ supplied to the first converter 2 is converted into first converted data a ₁ in the range of 0.25 ≦ a ₁ <1 and set in the register R2. Next, the first converted data a ₁ read from register R2 are supplied to addition, subtraction, multiplication, and division adder 3. The first conversion data a ₁ input to the addition, subtraction, multiplication, and division adder 3 is set is decorated with operations described above intermediate data a ₂ next to the register R3. Then, the intermediate data a ₂ read from the register R3 is supplied to the second transducer 4. Second transducer 4 receives the input data a ₀ and the intermediate data a _2, the square root data a ₃ obtained by the data conversion described above register
Set to R4. The square root data a ₃ to obtain from the register R4 finally read.

Incidentally, by using the square root data a ₃ as described above as the seed of Newton-Raphson approximation (starting value), it also becomes possible to determine more accurate square root approximation.

[Effects of the Invention] As described above, according to the present invention, the first variable means for converting the exponent part of the input data to the first variable data having a value of 0.25 or more and less than 1; Data a ₁ is 0.
When 25 ≦ a ₁ <0.5, the first data a ₁ And No. by substituting the equation, and outputs the calculation result as a second conversion data, and the first data a ₁ is
When 0.5 ≦ a ₁ <1, the first data a ₁ is And square root by substituting into the formula of (1) and outputting the calculation result as the second conversion data; and converting the exponent part of the input data into the exponent part of the square root data, Since the second conversion means for forming the square root data by combining with the mantissa part of the conversion data is provided, it is possible to perform a high-speed square root calculation with a simple configuration with a small circuit size.

[Brief description of the drawings]

Block diagram showing the configuration of a square root arithmetic unit according to an embodiment of FIG. 1 is the present invention, FIG. 2 is a diagram showing a structure of input data a ₀ in the same embodiment, FIG. 3 is the first in the same embodiment
FIG. 4 is a diagram for explaining the configuration of the converter 2, FIG. 4 is a diagram for explaining the function of the addition / subtraction multiplication / division unit 3 in the embodiment, and FIG. 5 is a configuration of the second converter 4 in the embodiment. It is a figure for explaining. 2... First converter, 3... Addition, subtraction, multiplication and division, 4.

Claims (1)

(57) [Claims] [Claim 1] and Hei input data a ₁ binary composed of the exponent and the mantissa, which in square root arithmetic unit for outputting as the square root data, the exponent portion of the input data is less than 1 0.25 or more first conversion means for converting the first converted data a ₁ takes a value, when the data a ₁ of the first is a 0.25 ≦ a ₁ <0.5, the first data a ₁ If you for Laid by substituting in the formula, and outputs the calculation result as a second conversion data, and the first data a ₁ is 0.5 ≦ a ₁ <1,
The first data a ₁ And square root by substituting into the calculation formula, and outputting the calculation result as second converted data; and converting the exponent part of the input data into the exponent part of the square root data, A second conversion means for forming the square root data by being combined with a mantissa part of the conversion data.