JP2825486B2 - Videotex image display circuit - Google Patents

Description

Description: TECHNICAL FIELD The present invention relates to a display circuit in an image information system of Videotex. [Summary of the Invention] In an image display circuit of Videotex, a memory for storing character / graphic data has a two-part configuration of a logical buffer and an image buffer. As a result, the data stored in the image buffer can be constantly rewritten according to the data stored in the logical buffer, and functions such as flushing and double height (character enlargement) can be added without adding special hardware. [Prior Art] JP-A-60-75874 will be described with reference to FIG. 3 as an example of the prior art. The flushing control circuit 1 shown here
A basic pulse generating circuit 2 for outputting a plurality of basic pulse signals for controlling flushing, a code memory 4 for storing a plurality of types of logic function codes, and a flushing circuit 3 for outputting a flushing signal. Of the plurality of types of logic functions, and a logic function corresponding to the logic function designation signal among the plurality of types of logic functions. [Problems to be Solved by the Present Invention] As shown in FIG. 3, in the case of the flushing control circuit of Japanese Patent Application Laid-Open No. 60-75874, hardware for flushing is added. Further, this flushing is not possible to change the color periodically only by blinking in terms of phenomenon. [Means for Solving the Problems] In order to solve the above-mentioned problems, a videotex image display circuit according to the present invention employs a character string comprising a code representing a character graphic and a control code for performing control according to the attribute of the character graphic. A raster scan type videotex image display circuit receives graphic data, generates image information from a code representing a character graphic and a control code, exchanges data with a color look-up table, and displays the character graphic on an image display screen. A reception buffer for holding the received character / graphic data, a character / graphic data including the reception buffer, the character / graphic data being taken out from the reception buffer, and a control code. A logical buffer in which a 1-bit write flag is written for each character and a 1-bit write flag are written. After the image information is generated by the character or pattern generator from the code representing the character graphic corresponding to the lag and the control code,
An image buffer which stores image information in which the control code is fetched as needed and can be read out at a predetermined cycle. [Operation] The character / graphic data sent from the information center through the communication line is temporarily stored in the logical buffer. Next, the code information in the logical buffer is read and sent to a character generator or a pattern generator, where the converted information is stored in the image buffer. The image information stored in the image buffer is read at a predetermined cycle and displayed on the image display screen. When data is sent from the logical buffer to the image buffer, the data is referred to the character generator or the pattern generator as described above, and the data of the 2-byte screen display flag memory stored in the logical buffer is used. The image buffer is rewritten. Embodiment An embodiment of the present invention will be described below with reference to the drawings. FIG. 1 is a block diagram of a videotex image display circuit showing an example of the present invention. In the figure, 7 is a display memory, 8
Denotes an image buffer, and 9 denotes a DRAM. 10 is a display controller, 11 is a character or pattern generator, and 12 is a color lookup table. FIG. 2 conceptually shows the internal configuration of the DRAM 9 of FIG. Reference numeral 19 denotes a character / graphic plane, reference numeral 20 denotes a dependent information plane, reference numeral 24 denotes a double height (character enlargement) control memory zone, and these are collectively referred to as a logical buffer 23. Reference numeral 21 denotes a reception buffer, and 22 denotes a temporary flag memory. Regarding the signal flow, a portion relevant to the present invention will be described. In FIG. 2, the signal from the center (7 bits or 8 bits)
The bit code is temporarily stored in the reception buffer 21 and then transferred to the logical buffer 23 including a double-hide control memory zone and a two-layered character / graphic plane 19 and subordinate information plane 20, and stored in the character / graphic plane 19. At this time, one bit of a write flag is written into the dependent information plane 20 for each character. The character / graphic plane 19 stores a character code representing control in addition to a code representing a character / graphic, and a control code (for example, an ESC code) is also stored in the corresponding location of the subordinate information plane 20. . The character / graphic plane 19 and the dependent information plane 20 are each 1
The character is assigned n bits (for example, 8 bits in the case of the present invention). The double height control memory zone allocates m bits per row (for example, 8 bits in the present invention). Next, a process in which the logical code information of the logical buffer 23 is converted into image information in the image buffer 8, transferred, and stored will be described. The transfer is done character by character. When a flag of a control code (for example, an ESC code) is set on the subordinate information plane 20, the control code stored in the character / graphic plane 19 corresponding to the position of the flag is transferred by the CPU 16. With reference to the program ROM 18, the temporary flag memory 22 is rewritten. Then,
Moving to the next character area, the code information of the character / graphic plane 19 is again converted to the corresponding image information stored in the pattern generator 11 by the mediation of the CPU 16 and the information of the temporary flag memory 22 is taken in to the image buffer 8. Is stored in At this time, the image information is n per dot.
It is stored in bits (for example, n = 4 in the case of the present invention).
At the end of the transfer, the rewrite flag at that location in the dependent information plane 20 is cleared. Once the code information of the temporary flag memory 22 is set, it remains unchanged until the next time a control code (for example, an ESC code) is written in the dependent information plane 20. Next, the color lookup table of FIG. 1 will be described. This color look-up table 12 is a RAM having a memory capacity of 3 × 16 = 48 bits and stores data from the image buffer 8 into R,
It is converted into G and B digital signals. The 3 × 8 = 24 bit area of the memory area of the color look-up table 12 is fixed to data, but the other half of the 24-bit area is transmitted through the CPU 16 at a predetermined cycle (for example, 0.5 second). The circuit is configured so as to be able to change. The operation of the flushing function, which is one of the functions of the video tex display circuit of the present invention, will be described based on the above description of the signal flow and the like. When one character is flashing-displayed, the control information code is first sent from the center, and is stored in the area of one character of the logical buffer 23 via the reception buffer 21. This code includes a flushing instruction code. Next, the character / graphic code is sent and stored in the next one character area of the logical buffer 23. Next, this logical buffer 23
When the character / graphics code is sent to the image buffer 8, the control code stored in the subordinate information plane 20 and the code of the character / graphics plane 19 are sent to the temporary flag memory 22, and a flushing instruction flag is set. When the next character / graphic code to be displayed for flushing is transferred, reference is made to the temporary flag memory 22 via the mediation of the CPU 16, and the character / graphic image information having the data of the flushing instruction captured is stored in the flashing address of the image buffer 8. Is stored in Next, the data of the image buffer 8 is sent to the address bus of the color look-up table 12. At this time, a color look-up table is
The data in 12 is sent as the address of a periodically changing area, and the output data is displayed in a flashing manner. Next, the double height function, which is another function of the videotex display circuit of the present invention, will be described. The double height means that a character or graphic is enlarged twice in the vertical direction. Now, when displaying one character in double height, first, a control code of a double height instruction is sent from the center, and a flag is set at a predetermined position of the double height control memory zone 24 in the logical buffer 23, and at the same time, The control code is also stored in the character / graphic plane 19 and the dependent information plane 20. Next, the character / graphic code is sent and stored in the character / graphic area next to the control code information in the logical buffer 23. When the character / graphic code instructed to be double-height is transferred from the logical buffer 23 to the image buffer 8, the code information is stored in the temporary flag memory 22 as in the case of the flashing display.
The data is referred to by the mediation of U16 and also to the double height control memory zone 24, and the data of the next character / graphic line in the image buffer 8 is deleted. Next, a 2-bit line is allocated to a 1-bit line of the character and stored in the image buffer 8, and the character is displayed in double height. [Effects of the Invention] As described above, according to the present invention, by providing a logical buffer in addition to an image buffer as a display memory, functions such as flushing and double height can be provided without adding special hardware. it can.

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a block diagram of a circuit of the present invention, FIG. 2 is a conceptual diagram showing an internal configuration of a DRAM, and FIG. 3 is a block diagram of a conventional image display circuit with a flushing function. . 1 Flashing control circuit 2 Basic pulse generation circuit 3 Flashing circuit 4 Code memory 5 Pattern memory 6 Shift register 7 Display memory 13 Parallel series conversion 14 D / A Conversion 15 CRT 16 CPU 17 Interface

Claims (1)

(57) [Claims] Receiving character / graphic data including a code representing the character / graphic and a control code for performing control according to the attribute of the character / graphic,
In a raster scan videotex image display circuit for generating image information from the code representing the character / graphic and the control code, exchanging data with a color look-up table and displaying the character / graphic on an image display screen, A reception buffer for holding character / graphic data, a code representing the character / graphic of the character / graphic data, including the reception buffer, extracting the character / graphic data from the reception buffer, and the control code A logical buffer in which a 1-bit write flag is written for each character, a code representing the character / graphic corresponding to the 1-bit write flag, and the control code, After the image information is generated, the image information incorporating the control code Stored at any time,
A videotex image display circuit, comprising: an image buffer that can be read at a predetermined cycle.