JP2826466B2 - Performance measurement method of parallel computer system - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for measuring the performance of a parallel computer system, and more particularly, to a method for measuring the performance of a parallel computer system in which a memory access conflict occurs in the parallel computer system.

[0002]

2. Description of the Related Art First, a configuration of a parallel computer system will be described with reference to FIG.

[0003] The parallel computer system shown in FIG.
An arithmetic processing unit 1 comprising arithmetic processing units 1-0 to 1-31 capable of performing arithmetic processing at the same time;
And a network 2-0 to 2-31, which connects a memory access request issued by the processing unit to the requested memory port.
And a memory unit 4 comprising a plurality of memory units 4-0 to 4-31 each having a plurality of memory banks which can be accessed simultaneously, and respective subordinate memory units 4-0 to 4-4. And a memory unit side network 3 comprising memory unit side networks 3-0 to 3-31 for connecting a memory access system request to a corresponding memory bank of -31.

In FIG. 4, each of the arithmetic processing unit 1, the network 2 for the arithmetic processing unit, the network 3 for the memory unit, and the memory unit 4 is shown as having 32 units. However, in practice, 2 ⁿ units can be used. The following description is based on a 32-unit configuration.

FIG. 4 shows only an interface for a memory of a memory access system, but actually there is an interface from the memory unit 4 to the arithmetic processing unit 1.

Next, the operation of the parallel computer system shown in FIG. 4 will be described.

When an instruction for a memory access system is issued from the arithmetic processing unit 1, a request is first issued to the subordinate operation processing unit side network 2.

When the request is received by the arithmetic processing unit side network 2, any one of the memory units (3
Recognize whether it is access to (of the two). here,
A plurality of pipelines exist in one arithmetic processing unit in the arithmetic processing unit 1, and instructions are issued at the same time.
Competition arbitration of requests for accessing the same memory unit is performed simultaneously in each operation processing unit side network of the operation processing unit side network 2. Here, as a result of competitive arbitration,
The request for which access is permitted is issued to the memory unit side network 3.

In each of the memory side networks of the memory side network 3, requests from different arithmetic processing units may be received simultaneously. When requests for the same memory bank of the same memory unit are issued simultaneously from different arithmetic processing units, contention arbitration is performed in each memory unit network in the same manner as the arithmetic processing unit network. Here, the request permitted to access as a result of the contention arbitration accesses the designated bank in the memory unit.

FIG. 5 is a block diagram of one of the processing units 1-0 to 1-31 belonging to the processing unit 1 in FIG.

The arithmetic processing unit shown in FIG. 5 includes vector processors 10 to 17 for simultaneously executing vector instructions, and a scalar processor 18 for prefetching, issuing, and executing scalar instructions.

Although FIG. 5 shows a configuration in which one arithmetic processing unit has eight vector processors, a configuration with 2 ⁿ units is actually possible. Below are all 8 vector processors
A description will be given of the configuration of the stand.

First, the scalar processor 18 executes instruction prefetching. If the prefetched instruction is a scalar instruction, the request is issued to the memory as it is. Actually, a request is issued to the network on the operation processing unit side under the operation processing unit. When the prefetched instruction is a vector instruction, it instructs each vector processor to execute the instruction.

FIG. 6 is a diagram showing the operation processing unit side networks 2-0 to 2--2 belonging to the operation processing unit side network 2 in FIG.
31 is a block diagram illustrating a conventional configuration of one arithmetic processing unit side network among 31. FIG.

The arithmetic processing unit side network shown in FIG. 6 determines a request reception buffer 21 for receiving a request from each processor and a memory port to which the request received by the request reception buffer 21 is directed. If there is a conflict, the contention arbitration unit 22 determines the priority of the access, and the crossbar unit 24 selects an output port of a request permitted to access the memory by the contention arbitration unit 22. ing.

A memory access request issued from each processor is first received by a request reception buffer 2.
Received at 1. Here, when a preceding request is not stored in the request reception buffer 21, the request is sent to the contention arbitration unit 22.

The condition for suspending a request in the request receiving buffer 21 is when a conflict between requests occurs in the conflict arbitration unit 22 and the subsequent request cannot be processed.

The request receiving buffer 21 holds the request under the above-mentioned conditions, but the amount of the request is limited. When the limit is reached, a hold signal indicating that the request cannot be received is transferred to the processor. I do. Next, the request receiving buffer 21
The request is transferred to the contention arbitration unit 22 from.

The operation of the contention arbitration unit 22 determines to which memory port a request from each processor accesses. In practice, it is determined which one of the plurality of memory unit networks 3-0 to 3-31 is to be accessed. This can be recognized by some bits of the address of the request.

Here, when there is only one request for a certain memory port, the request is issued to the crossbar unit 24 as it is. However, when a request from a certain processor is issued to the same memory port as a request from another processor, contention arbitration is performed here.

In the contention arbitration, a request is issued serially to a memory port according to a determined priority. While the request is issued serially, the request reception buffer 21 is not allowed to issue the subsequent request.

FIG. 7 shows the memory unit side networks 4-0 to 4-3 belonging to the memory unit side network 4 in FIG.
FIG. 2 is a block diagram of one memory unit side network in FIG.

The memory unit side network in FIG. 7 includes request buffer units 300 to 33 which receive requests from the arithmetic processing unit side networks 2-0 to 2-31, respectively.
1 and a contention arbitration unit 332 that receives requests from the request buffer units 300 to 331 and performs contention arbitration for each memory bank of the memory units 4-0 to 4-31.
And a crossbar unit 333 for selecting an output port of a request whose access to the memory bank is permitted by the contention arbitration unit 332.

Each network 2-0 to 2-
The request transferred from 31 is received by the corresponding request buffer units 300 to 331. Since this buffer is compatible with the arithmetic processing unit side networks 2-0 to 2-31, the hold due to contention is performed on a port basis.
The request received here is sent to the contention arbitration unit 332.

The contention arbitration unit 332 first determines to which memory port the received request is. Here, if there is no conflicting request from the other processing unit side network, the request is output to the crossbar unit 333 as it is. When a request from another operation processing unit side network attempts to access the same memory port, the contention arbitration unit 3
Reference numeral 32 serially outputs a request issuance permission according to the determined priority. The request permitted to issue the request is output to the crossbar unit 333. The crossbar unit 333 receives the request issued by the contention arbitration unit 332 and issues the request to the memory port specified by the request.

FIG. 8 is a block diagram of one of the memory units 4-0 to 4-31 belonging to the memory unit 4 in FIG.

The memory section shown in FIG. 8 comprises a plurality of memories 400 to 431 which can be accessed simultaneously.

When a request output from the memory unit side network 3 arrives at one specified memory among the memories 400 to 431 belonging to the memory unit, the memory access is started as it is. This is because no conflict with other requests occurs.

As described above, in the parallel computer system, contention for memory access occurs.
It is a measure of system and software performance evaluation.

In the performance measurement method of the parallel computer system for competing for memory access in the parallel computer system having the above-described configuration, in order to measure the waiting time due to the competition between different processors of the same processing unit, the network of the processing unit side network is used. Each of the networks on the memory unit side has a waiting time measurement function for measuring the waiting time due to competition between requests from different arithmetic processing units.

Referring to FIG. 9, a performance measuring method of a conventional parallel computer system for measuring a waiting time due to competition between different processors of the same arithmetic processing unit will be described.

FIG. 9 is a block diagram of the request receiving buffer 21 of FIG.

The request receiving buffer 21 shown in FIG.
Holds registers 2100 to 2108 that receive requests for each processor, an input buffer 2119 that can hold waiting requests of the number of processors in one word with an accommodation word number of W, and a write address of the input buffer 2119. A write address register (WAR) 2117 including a +1 circuit, and a read address register (RAR) 2 including a +1 circuit holding a read address of the input buffer 2119
118, a comparator 2120 for comparing the values of the WAR 2117 and the RAR 2118, a register 2121 for holding the output of the comparator 2120, and one of the outputs of the processor corresponding request reception registers 2100 to 2108 and the output of the input buffer 2119. It comprises a selector 2122 and a register 2123 for receiving the output of the selector 2122.

Requests output from the processor are received by registers 2100 to 2108. At this time, all requests from other processors output at the same timing are also received. Here, when there is no preceding request or when the preceding request has passed through the contention arbitration unit 22, the input buffer 2119 is bypassed and the request is set in the register 2123. Thereafter, the request is transferred to the contention arbitration unit 22. However, if the preceding request is jammed, the request is held in the input buffer 2119.
At this time, WAR2117 is incremented by one.

When the contention arbitration of the preceding request is completed while the requests are accumulated in the input buffer 2119, the next request is read from the input buffer 2119 and the request is transferred to the contention arbitration unit 22. At that time, RAR2118 is incremented by one. The request read from the input buffer 2119 is selected by the selector 2122 and
23 and transferred to the contention arbitration unit 22. Here, the comparator 2120 is (WAR2117-RAR
2118) is equal to the maximum number of words W accommodated in the input buffer 2119, "1" is output. In this state, the input buffer 2119 is in an input buffer busy state in which no more requests can be accommodated, and the signal of the output “1” of the comparator 2120 is input to the corresponding processing unit as an input buffer busy signal. It is sent and stops issuing requests from it.

The performance measuring circuit (not shown) is connected to the register 21
21 measures the time during which the output “1” of the comparator 2120 is held, and uses this time as the time that the arithmetic processing unit side network 2 waits due to competition with another processor or the like.

The latency measurement of the memory side network for measuring the latency due to competition between requests from different arithmetic processing units measures the latency due to competition between different processors of the same arithmetic processing unit. In this case, the same write and read operations as those provided in the input buffer 2119 of FIG. 9 are performed for each of the request buffers 300 to 331 of FIG. 7 in this case. WAR2117 and RAR2118, a comparator 2120, and a register 2121 are provided, and the performance is measured by a performance measuring circuit (not shown).

In the above system configuration, the processor from which the request is issued, and in the case of a vector instruction, the value of the vector register of the return destination is sent to the memory unit side network as the accompanying information at the same time as the request. . When data is returned in the case of a load-type instruction, the accompanying information is also returned from the memory-side network at the same time. The arithmetic processing unit side network returns the load data based on the accompanying information.

However, in this case, the amount of transfer data increases, the number of interface lines between networks increases, and wiring becomes congested.
0, the arithmetic processing unit side networks 2-0 to 2
-31, an ID issuance management unit 23 is provided for each of the memory units, without sending accompanying information to the memory unit side network. The accompanying information is written and registered, and the write address is sent to the memory side network as an ID number. Then, when the ID number returns from the network on the memory unit side in both the load and store instructions, the contents of the ID buffer are read using the ID number as a read address, and the accompanying information of the instruction is obtained to reduce the congestion of the wiring. ing.

[0040]

In the above-described conventional performance measurement method for a parallel computer system, if the ID issue management unit 23 is provided to avoid wiring congestion, the request receiving buffer 21 As a condition for suspending, the contention arbitration unit 22 considered above
In addition to the case where a request conflict occurs and the subsequent request cannot be processed, a request suspension condition also occurs in the ID issuance management unit 23.

The reason is that a request from which a reply from the network on the memory unit side does not return is sent to the I / O corresponding to each memory unit.
This is because a new request may remain in the D buffer and a new request cannot be registered in the ID buffer corresponding to each memory unit. In such a case, in the performance measurement method of the conventional parallel computer system, the delay in the memory unit side network is measured as the delay of the ID issue management unit 23, and the influence of at least a part of the memory unit side network is reduced. There is a problem that it is not possible to accurately measure the delay of the arithmetic processing unit side network by excluding it.

An object of the present invention is to measure the performance of a parallel computer system provided with an ID issue management unit by eliminating the influence of at least a part of the memory unit side network, even in a parallel computer system in which wiring congestion is avoided. It is an object of the present invention to provide a method for measuring the performance of a parallel computer system that can contribute to the improvement analysis of a user program.

[0043]

According to the performance measuring method of the parallel computer system of the first invention, n (natural number) arithmetic processing units each including m (natural number) processors and n simultaneous processing units can be simultaneously accessed. N memory sections each including a memory section, and n arithmetic processing section side networks which are provided corresponding to the respective arithmetic processing sections and connect outputs from respective processors of the corresponding arithmetic processing sections to the corresponding memory sections; In a performance measurement method for a parallel computer system comprising n memory unit-side networks provided for each of the memory units and connecting an output from each arithmetic processing unit-side network to a corresponding memory of the memory unit, Each of the arithmetic processing unit side networks simultaneously receives the same memory unit from two or more processors of the corresponding arithmetic processing unit. When the memory access request is issued, the input buffer for holding the subsequent memory access request for contention arbitration and the accompanying information of the issued memory access request provided for the memory unit are registered and registered. I instead of
An input buffer for generating an input buffer busy signal when the input buffer becomes full when the input buffer is full. A busy signal generating means for generating an ID buffer busy signal when registration of the ID buffer section is full;
A buffer busy signal generating means for receiving the input buffer busy signal and the ID buffer busy signal, and when the input buffer is full and all of the n I
And a time measuring means for measuring a time when the registration of the D buffer is not full.

The performance measurement method of the parallel computer system according to the second aspect of the present invention is characterized in that n (natural number) arithmetic processing units each having m (natural number) processors and n (n) natural memory units each having n simultaneously accessible memories. For each of the n processing unit side networks and the memory unit, which are provided corresponding to the memory unit and the respective processing units and connect the output from each processor of the corresponding processing unit to the corresponding memory unit. The performance of a parallel computer system comprising an n number of memory unit side networks connected to outputs corresponding to the respective memory units in the memory unit. The network is simultaneously accessed by two or more processors of the corresponding arithmetic processing unit for the same memory unit. When a request is issued, an input buffer for holding a subsequent memory access request for contention arbitration and accompanying information of the issued memory access request provided for the memory unit are registered and replaced. Issue an ID number and invalidate this registration when there is a response to it.
Input buffer busy signal generating means for generating an input buffer busy signal when the input buffer is full;
When the ID buffer section registration is full, the ID
An ID buffer busy signal generating means for generating a buffer busy signal, one of the IDs selected from among the n when the input buffer is full and the input buffer busy signal and the ID buffer busy signal are supplied;
And time measuring means for measuring the time when the registration of the buffer section is not full.

[0045]

Next, embodiments of the present invention will be described with reference to the drawings.

Prior to this, the configuration and operation of the ID issuance management unit 23 provided as shown in FIG. 10 in the arithmetic processing unit side network to reduce the congestion of wiring will be described.

FIG. 3 is a block diagram of the ID issue management section 23.

The ID issuance management unit 23 shown in FIG. 3 is a crossbar unit 230 for distributing the request accompanying information from each processor sent from the contention arbitration unit 22 according to the memory unit.
ID buffer units 2300 to 2331 which are respectively provided corresponding to the memory units, register accompanying information of the issued requests in the memory units, issue ID numbers instead of the registered information, and control and manage the issuance of requests. And a logical sum circuit 231 for generating a logical sum signal of the busy signals from the buffer units 2300 to 2331.

The configuration of the ID buffer units 2300 to 2331 is the same, and a decoder (WADEC) 23200 for decoding the write address of the ID buffer 23000 is used.
A decoder (RADEC) 23300 for decoding the read address of the ID buffer 23000; and a v-bit indicating whether valid request accompanying information having the number of bits corresponding to the number of words of the ID buffer 23000 is written for each word. , A ALL1 detection circuit 23500 that detects that all bits of the v-bit register 23400 are all 1, and a bit that is 0 among the bits of the v-bit register 23400. An encoder (ENC) 23600 for detecting and creating a write address of the ID buffer 23000 corresponding thereto, a register 23700 for receiving accompanying information output from the crossbar unit 230,
A register (IDWAR) 23800 for holding the write address of the D buffer 23000, and an ID buffer 230
00 to hold a read address (IDRA
R) 23900, an ID buffer 23000 having the value of the register 23700 as input data, the value of the register 23800 as a write address, and the value of the register 23900 as a read address, and a register 23100 for holding data read from the ID buffer 23000. It is configured.

Next, the operation of the ID issue management section 23 will be described.

The request accompanying information of the request permitted to be issued by the contention arbitration unit 22 is input to the crossbar unit 230 and set in the register 23700 of the ID buffer unit corresponding to the destination memory unit.
If there is a free word in 000 (a word storing invalid data), it is stored there.

Since the storage state of valid data in ID buffer 23000 is indicated by each v-bit stored in v-bit register 23400, ID buffer 23
000 is empty and is ready to receive new request accompanying information, the v-bit register 2
The write address corresponding to the empty word is created by encoding by the encoder 23600 based on the output of 3400, and is set in the register 23800. The data of the register 23700 is stored in the word corresponding to the address indicated by the register 23800 of the ID buffer 23000. Is done.

At the same time, the write address output from the register 23800 is output to the memory unit together with the request data as an ID number.

Further, the write address is stored in the encoder 236.
From 00, the data is sent to the decoder 23200, decoded, and the v bit of the v-bit register 23400 corresponding to the word in which the data is now stored is set to 1, indicating that valid data has been stored.

This v bit is set to 1 until the reply to the request returns from the network on the memory unit side.

When the reply to the request returns from the network on the memory unit side, the ID number also returns via the RYID terminal in FIG. In the case of a memory load instruction, the ID number is returned together with the load data. For memory store instructions, the reply is I
Only the D number returns from the network on the memory unit side.
When a valid reply returns from the memory side network, it is received by the register 23900. Using this value as a read address, data is read from the ID buffer 23000 and set in the register 23100, and at the same time, the ID number is decoded by the decoder 23300, and the v-bit register corresponding to the word from which the data has just been read is read. Reset the v bit of 23100 to 0,
Indicates that the word has become an empty word.

As described above, the ID buffer 230
If there is an empty word at 00, the request accompanying information is registered in the ID buffer 23000 and an ID number is issued instead. If there is no empty word, the ID number cannot be issued and the subsequent Since the request accompanying information cannot be received, in this case, the contention arbitration unit 2
2 and sends a busy signal to the input buffer 21 to stop the supply of request accompanying information from them. The logical sum circuit 231 outputs a busy signal of each ID buffer unit, that is, each of the ID buffer management units busy signals, so that any of the ID buffer units 2300 to 2331 in the ID issuance management unit 23 can transmit the busy signal. The logical sum signal of the output of the ALL1 detection circuit 23500 is created.

As described above, the input buffer busy also occurs due to the ID buffer busy caused by the network on the memory unit side. Therefore, in order to measure the performance of the arithmetic processing unit side, the input buffer busy is caused by the network on the memory unit side. Factors need to be removed.

Therefore, in the present invention, the time when the input buffer is busy and the time when the ID buffer is not busy is measured.

FIG. 1 is a block diagram of a first embodiment of a performance measuring method for a parallel computer system according to the present invention (in the following description, the input buffer busy signal generating means and the ID buffer busy signal generating means described above). The repeated description of the creation means is omitted, and the same applies to the second embodiment.)

The performance measurement method of the parallel computer system of FIG. 1 inverts the first signal (1 if the binary signal is busy and 0 otherwise) supplied by the ID issue management section busy signal line. An inverter 232, a register 233 for temporarily storing the inverted first signal, and a second signal supplied by the input buffer busy signal line (1 if the binary signal is busy, otherwise 0)
234 for temporarily storing the data and a logical product circuit 235
And a time measuring circuit 236 for measuring the time when the output of the AND circuit 235 becomes 1.

The time measuring circuit 236 includes a logical product circuit 235
Is a counter circuit that counts up the output 1 of the above as a count-up signal and outputs the count value.

With this configuration, measuring the time when the output of the AND circuit 235 is 1 means that the data stored in the registers 234 and 233 is 1 each, that is, the input buffer. This means that the time is busy and the ID issuance management unit 23 is not busy.

As described above, in the first embodiment, the delay time due to contention occurring in the same arithmetic processing unit can be measured.
Tune up the user program based on this measurement result and minimize the contention time that occurs in the same processing unit to maximize the data transfer capability of the processing unit side network of the parallel computer system. It has the effect that it can be done.

FIG. 2 is a block diagram of a second embodiment of the performance measuring method of the parallel computer system according to the present invention.

The performance measurement method of the parallel computer system shown in FIG. 2 includes a selection circuit 237 for selecting any one busy signal line from the busy signal lines of each ID buffer unit in the ID issue management unit 23. 232 that inverts the third signal (1 if the binary signal is busy and 0 otherwise) supplied by the busy signal line
And a register 23 for temporarily storing the inverted third signal.
3, a register 234 for temporarily storing a fourth signal (1 if the binary signal is busy and 0 otherwise) supplied by the input buffer busy signal line, a logical product circuit 235, and a logical product And a time measuring circuit 236 for measuring the time when the output of the circuit 235 becomes 1.

The time measuring circuit 236 has a logical product circuit 235
Is a counter circuit that counts up the output 1 of the above as a count-up signal and outputs the count value.

With this configuration, measuring the time when the output of the AND circuit 235 is 1 means that the data stored in the registers 234 and 233 is 1 each, that is, the input buffer. This means that the time when the ID buffer unit is busy and the ID buffer unit corresponding to the selected busy signal line is not busy is measured.

As described above, in the second embodiment, the contention time other than the contention time by the arithmetic processing units in the memory side network corresponding to the ID buffer unit selected by the selection circuit 237, that is, the contention time, Measuring the delay time caused by the competition between the arithmetic processing units in the other memory network other than the memory network corresponding to the ID buffer selected by the selection circuit 237 and the competition generated in the same arithmetic processing unit. Can be.

The difference between the measurement time according to the first embodiment and the measurement time according to the second embodiment is the delay time caused by the competition between the arithmetic processing units in the memory side network corresponding to the selected ID buffer unit. And this is
By measuring the D-buffer section, it is possible to contribute to the improvement analysis of the user program for the throughput of the entire system.

[0071]

As described above, the performance measurement method of the parallel computer system according to the present invention measures at least a part of the memory unit side by measuring the time when the input buffer is busy and the time when the ID buffer is not busy. Performance can be measured without network impact,
This has the effect of contributing to improvement analysis of the user program.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a first embodiment of a performance measurement method for a parallel computer system according to the present invention.

FIG. 2 is a block diagram showing a second embodiment of the performance measuring method of the parallel computer system of the present invention.

FIG. 3 is a block diagram of an ID issuance management unit that generates an ID buffer busy of the performance measurement method of the parallel computer system of the present invention.

FIG. 4 is a block diagram showing a configuration of a parallel computer system to which the performance measurement method of the parallel computer system of the present invention is applied.

FIG. 5 is a block diagram illustrating a configuration of an arithmetic processing unit of the parallel computer system of FIG. 4;

6 is a block diagram showing a configuration of a conventional arithmetic processing unit side network of the parallel computer system of FIG. 4;

FIG. 7 is a block diagram illustrating a configuration of a memory-side network of the parallel computer system of FIG. 4;

FIG. 8 is a block diagram illustrating a configuration of a memory unit of the parallel computer system of FIG. 4;

9 is a block diagram showing a configuration of a request receiving buffer for generating an input buffer busy of the performance measurement method of the parallel computer system of the present invention, which is located in the network of the processing unit in FIGS. 6 and 10. FIG.

FIG. 10 is a block diagram illustrating a configuration of an arithmetic processing unit side network including an ID issue management unit of the parallel computer system of FIG. 4;

[Explanation of symbols]

 1, 1-0 to 1-31 Arithmetic processing unit 2, 2-0 to 2-31 Network for arithmetic processing unit 3, 3-0 to 3-31 Network for memory unit 4, 4-0 to 4-31 Memory unit 10-17 Vector processor 18 Scalar processor 21 Request receiving buffer 22, 332 Competition arbitration unit 23 ID issue management unit 24, 230, 333 Crossbar unit 231 Logical OR circuit 232 Inverter 233, 234, 2100-2108 Register 235 Logical product circuit 236 hours Measurement circuit 237 Selection circuit 300 to 331 Request buffer 400 to 431 Memory 2117 Register (WAR) 2118 Register (RAR) 2119 Input buffer 2120, 23400 to 23131 Comparator 2122 Selector 2300 to 2331 ID buffer 23000 ID Baffua 23200 decoder (WADEC) 23300 decoder (RADEC) 23400 v- bit register (IDBV) 23500 ALL1 detection circuit 23600 encoder (ENC) 23800 register (IDWAR) 23900 register (IDRAR)

Claims (2)

(57) [Claims] 1. An n (natural number) arithmetic processing unit including m (natural number) processors and an n memory unit including n simultaneously accessible memories, respectively, and a corresponding one of the arithmetic processing units. N processing unit side networks for connecting the outputs from the respective processors of the provided corresponding processing units to the corresponding memory units, and outputs from the respective processing unit side networks provided for each of the memory units Are connected to the corresponding memories of the memory unit, and the network of the n memory units is connected to the corresponding memory of the memory unit.
When a memory access request to the same memory unit is issued simultaneously from the above processor, an input buffer for holding a subsequent memory access request for contention arbitration and a memory provided corresponding to the memory unit It has n ID buffer units for registering the accompanying information of the access request, issuing an ID number in place of this, and invalidating the registration when there is a response to the ID number, so that the input buffer becomes full. Input buffer busy signal generating means for generating an input buffer busy signal when the input buffer is busy, ID buffer busy signal generating means for generating an ID buffer busy signal when the registration of the ID buffer section is full, and the input buffer busy signal. And said I
A time measuring means for measuring the time when the input buffer is full and the registration of all the n ID buffer units is not full when supplied with the D buffer busy signal. . 2. Corresponding to n (natural number) arithmetic processing units each including m (natural number) processors, n memory units each including n simultaneously accessible memories, and the arithmetic processing units. N processing unit side networks for connecting the outputs from the respective processors of the provided corresponding processing units to the corresponding memory units, and outputs from the respective processing unit side networks provided for each of the memory units Are connected to the corresponding memories of the memory unit, and the network of the n memory units is connected to the corresponding memory of the memory unit.
When a memory access request to the same memory unit is issued simultaneously from the above processor, an input buffer for holding a subsequent memory access request for contention arbitration and a memory provided corresponding to the memory unit It has n ID buffer units for registering the accompanying information of the access request, issuing an ID number in place of this, and invalidating the registration when there is a response to the ID number, so that the input buffer becomes full. Input buffer busy signal generating means for generating an input buffer busy signal when the input buffer is busy, ID buffer busy signal generating means for generating an ID buffer busy signal when the registration of the ID buffer section is full, and the input buffer busy signal. And said I
Parallel computer having a D buffer busy signal and a time measuring means for measuring a time when the input buffer is full and the registration of one of the n ID buffer units is not full. System performance measurement method.