JP2827331B2 - Bus control device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Industrial Application Field] The present invention is used for bus control between a common bus and transmission-side and reception-side agents connected to the common bus. The present invention relates to control of request transmission and reply response in bus transmission between a transmitting agent and a receiving agent.

〔Overview〕

The present invention relates to a bus control device that performs a bus control between a transmitting side agent and a receiving side agent connected to a common bus, and performs an error check on a bus transmission request requested from within the transmitting side agent, and when an error occurs. Outputs a no-operation code for the transfer type line on the bus,
By outputting the normal reception code to the response status line on the bus when the receiving side receives the no-operation code, extra time and labor are saved, and the bus throughput is improved.

[Conventional technology]

Conventionally, this type of bus control operates as shown in the timing chart of FIG. First, transmission request information such as a request code and a request address is sent from the upper unit in the transmission-side agent to the transmission-side bus control device, and is set in an internal buffer. Here, it is checked whether or not the transmission request information has an error such as a parity error or an undefined code. If an error occurs, the bus arbitration device does not issue a bus use right request.If no error occurs, the bus arbitration device outputs a bus use right request.When a bus use permission signal returns, transmission information is output on the common bus. ing.

[Problems to be solved by the invention]

The above-mentioned bus transfer control performs an error check on transmission request information, confirms that there is no error, and then spends extra time to output a bus use right request, thereby failing to improve the bus throughput. There is.

An object of the present invention is to eliminate such disadvantages and to provide an apparatus capable of improving the bus throughput without requiring extra time.

[Means for solving the problem]

The present invention provides a bus control device which is provided in a transmission side and a reception side agent connected to a common bus and performs bus control, wherein the transmission side performs an error check on a bus transmission request requested from an upper unit, Request transmission means for issuing a bus use right request before the completion of the error check and outputting a no-operation code to a transfer type line on the common bus when an error occurrence is detected. Reply response means for outputting a normal reception code to a response status line on the common bus when a no-operation code is received from the upper transfer type line is provided.

[Action]

The bus use right request is output to the bus arbitration device before the error check for the bus transmission request from the upper unit is completed, and the bus use right is acquired. In most cases, there is no error and operation continues. If an error is detected after outputting the bus use right request, non-operational transmission is performed on the common bus, and the bus control device that has received this non-operational transmission always returns normal reception as a reply status.

As a result, the throughput can be improved, extra time and labor can be saved, and the same processing as when no error occurs on the bus can be performed.

〔Example〕

Next, embodiments of the present invention will be described with reference to the drawings. First
FIG. 2 is a block diagram showing the configuration of the embodiment of the present invention.

In the embodiment of the present invention, the transmission side of the bus control device provided in each of the transmission side and reception side agents 1 and 2 connected to the common bus 100 performs an error check on the bus transmission request requested by the upper unit. Request transmission means 20 for issuing a bus use right request before the completion of the error check, and outputting a no-operation code to the transfer type line on the common bus 100 when an error occurrence is detected. When a no-operation code is received from the transfer type line on the common bus 100,
Reply response means 22 for outputting a normal reception code to the response status line on 0 is provided.

The common bus 100 has an address line 50, a channel line 5
1, a transfer type line 52, a response status line 53, a bus use right request signal line 54, and a bus use permission signal line 55. The common agent 100 includes a transmitting agent 1, a receiving agent 2, and a bus arbitration device 3. Connected.

The transmitting agent 1 includes a transmitting bus controller 10 and a transmitting upper unit 11, and the receiving agent 2 includes a receiving bus controller 12. In the transmission-side bus control device 10, an address buffer 30, a channel generation circuit 31,
The request transmission means 20 including the code generation circuit 33 and the transmission control circuit 32 and the reply determination means 21 for checking the reply status output to the response status line 53
The reception-side bus control device 12 includes a reception buffer 40, a destination detection circuit 42, a code determination circuit 43, and a reply response unit 22 including a reception control circuit 44 for generating a reply status.

When a bus transfer is performed from the transmitting agent 1 to the receiving agent 2, the transmitting bus control device 10 in the transmitting agent 1 performs bus transmission using the request transmitting means 20 provided inside. Further, the receiving-side bus control device 12 in the receiving-side agent 2 receives the bus transmission from the transmitting-side agent 1 by using the internal reply-response means 22, and notifies the transmitting-side agent 1 of the receiving state in a reply status. . The transmission-side bus control device 10 includes a reply determination unit 21.
Checks the content of this reply status to determine whether or not the bus transmission has been executed normally.

Next, the request transmitting means 20 will be described. The request transmitting unit 20 receives the request code 69 from the transmitting upper unit 11 as described above, detects an error, and generates a code to be output to the transfer type line 52 on the common bus 100. An address buffer 30 that takes in a request address 68 from the upper host unit 11 and detects an error, and an address buffer 30
The channel generation circuit 31 that generates channel information to be output to the channel line 61 on the common bus 100 from the contents of the buffer 30, the channel generation circuit 31, and the error information from the code generation circuit 33 using lines 64, 65, and 66. And a transmission control circuit 32 instructing the code generation circuit 33 to generate a no-operation code.

FIG. 2 is a timing chart of the operation of the embodiment of the present invention,
Table 1 shows the contents of the transfer type code and the transfer type. As soon as the request address 68 and the request code 69 output from the transmission-side upper unit 11 are taken into the address buffer 30 and the code generation circuit 33, an error is detected. At this time, at the same time, the bus arbitration device 3 is
Is output to increase the bus throughput for one machine cycle. When the bus arbitration device 3 returns the bus use permission signal line 55, necessary information is output to the address line 50, the channel line 51, and the transfer type line 52 on the common bus 100. When an error such as a parity error or an undefined code occurs in the request address 68 and the request code 69, the transmission control circuit 32 uses the line 67 to detect an error using a code generation circuit.
The transfer type code is switched to the no-operation code to notify the transfer type code to the transfer type line 52.

Next, the reply response means 22 on the receiving side will be described. As described above, the reply response means 22 constantly checks the channel line 71 on the common bus 100 and detects that it is a bus cycle addressed to its own agent, and a bus cycle based on the contents of the transfer type line 52. , A reception buffer 40 for latching the contents of the address line 50, a reception request signal 75, a reception type error signal 76
And a reception control circuit 44 for generating and outputting a reply status for transmission from the reception buffer state signal 74.

When the destination detection circuit 42 detects a bus cycle addressed to its own agent, it notifies the reception control circuit 44 of this via a signal line 75. The reception control circuit 44 performs error detection and busy detection of the reception buffer 40 through the signal lines 74 and 76. When it is determined that reception is possible, the reception control circuit 44 causes the reception buffer 40 to perform a holding operation through the signal line 77 and also performs normal reception as a reply status ( ACK) to the common bus 1 via the signal line 73.
Output to the response status line on 00. A list of reply status codes is as shown in Table 2.

The reception control circuit 44 receives, as a reply status, an error reply indicating that an error was detected at the time of another reception of normal reception (ACK), a buffer busy indicating that the reception buffer 40 is still busy and the reception is not possible, and an interrupt request. Then, any one of interrupt rejection indicating that it is in the reception impossible state is generated.

When a bus cycle occurs when the transfer type code is the no-operation code (NOP), the bus cycle is originally invalid, so that it is better for the transmitting agent 1 to look as if no bus cycle has occurred. In particular, it is desirable not to report this error from the receiving agent 2 with respect to an error occurring during a bus cycle.

Therefore, the code judgment circuit 43 notifies the reception control circuit 44 of the reception of the bus cycle of the no-operation code using the signal line 78, and the reception control circuit 44 always receives this bus cycle in any state. The normal reception is notified to the transmitting agent 1 as a reply status. However, the signal line 77 is not made valid for the reception buffer 40, so as to prepare for the next reception request.

The reception control circuit 44 outputs the reply status to the response status line 53 on the common bus 100 at a certain timing, checks this by the reply determination means 21 in the transmission-side bus control device 10, and checks the normal reception (ACK If the code is other than (), an error report is made to the transmission-side upper unit 11 using the signal line 80.

[Effects of the Invention] As described above, the present invention has the following effects.

1. The bus throughput can be improved by outputting the bus use right request to the bus arbitration device before the error check for the bus transmission request from the upper unit is completed.

2. Even if an error is detected after outputting the bus use right request, no operation (NOP) transmission is performed on the bus, so that no extra time or effort is required for recovery.

3. Since the bus controller that has received no operation transmission always returns normal reception as the reply status, even if an error occurs on the bus, it can be ignored and treated as if no bus cycle occurred be able to.

[Brief description of the drawings]

FIG. 1 is a block diagram showing the configuration of an embodiment of the present invention. FIG. 2 is a timing chart of the embodiment of the present invention. FIG. 3 is a timing chart of a conventional example. 1 ... Sending agent, 2 ... Receiving agent, 3 ... Bus arbitration device, 10 ... Sending bus control device,
11: upper unit on the transmitting side, 12: bus controller on the receiving side, 20: request transmitting means, 21: reply determining means, 22: reply responding means, 30: address buffer, 31: channel generating circuit , 32 ... Transmission control circuit, 33
…… Code generation circuit, 40 …… Reception buffer, 42 …… Destination detection circuit, 43 …… Code determination circuit, 44 …… Reception control circuit, 50 …… Address line, 51 …… Channel line, 52
…… Transfer type line, 53 …… Response status line, 54
… Bus request signal line, 55… Bus permission signal line.

Claims (1)

(57) [Claims] 1. A bus control device provided in a transmitting agent and a receiving agent connected to a common bus and performing bus control, wherein the transmitting side performs an error check on a bus transmission request requested from an upper unit. Request transmission means for issuing a bus use right request before the completion of the error check, and outputting a no-operation code to a transfer type line on the common bus when an error occurrence is detected. A bus control device comprising: reply response means for outputting a normal reception code to a response status line on the common bus when a no-operation code is received from a transfer type line on the bus.