JP2827979B2 - Assembler processing apparatus and assembler processing method - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an assembler processing apparatus and an assembler processing method for converting an input source file into an object file and outputting the converted object file, and more particularly to an assembler processing apparatus and an assembler processing method in an operating environment without virtual memory management. .

[0002]

2. Description of the Related Art Conventionally, an assembler processing device which inputs a source file, converts the source file into an object file, and outputs the converted object file is constructed, for example, as shown in a block diagram of FIG.
The conventional assembler processing device shown in FIG. 1 is a one-pass assembler that operates in an operating environment without virtual memory management and allows forward reference of symbols. Then, the parse tree is stored in the virtual memory space in order to later resolve the expression described in the operand that has not been resolved in the first pass.

In an assembler processing apparatus 90 shown in the figure, a source file input unit 91 first reads a source file.
Next, the syntax analysis section 92 analyzes the syntax of the read source file, and obtains the reference information table 93 and the expression information table 9.
4 and outputs the analyzed content as an intermediate code 95.

[0004] The reference information table 93 is a table of reference information created when a forward reference is made. The expression information table 94 is a table of expressions described in operands when a forward reference is made. The intermediate code 95 is a code obtained by converting a source program into a machine language code. Further, the syntax analysis unit 92 generates an expression information node using the expression generation processing unit 96, and evaluates the generated expression using the expression evaluation processing unit 97.

After completion of the syntax analysis by the syntax analysis unit 92, the operand determination processing unit 98 resolves the operand of the intermediate code 95 that has not been determined by the forward reference, using the reference information table 93 and the expression information table 94. Create object code. The object file created in this way is output to the object file output unit 9.
9 is output. Further, the operand determination processing unit 98
Evaluates the generated expression using the expression evaluation process 97.

Reference information table 93, expression information table 9
FIG. 10 shows the relationship between No. 4 and the intermediate code 95. When n forward references are described in the input source file, the reference information table 93
a to 93n are created. In the formula information table 94, formula information entries 94a to 94n are created. The reference information of the reference information entries 93a to 93n is the virtual address of the referenced expression information and the intermediate code 9 at the reference position.
5 positions.

Formula information entry 94h (h: a ≦ h ≦ n)
FIG. 11 shows an example of the detailed configuration of FIG. Suppose an operand has k terms. The expression information entry 94h is composed of a parse tree. Each node 941 constituting the parse tree
Each of a to 941k indicates another node by a virtual address.

The operation of the syntax analysis unit 92 in the conventional assembler processing device 90 will be described with reference to the flowchart of FIG. First, the syntax of the input source file is analyzed (step 1201). Here, the syntax analysis unit 92 generates an expression node in the expression information table 94 using the expression generation processing unit 96, and analyzes the syntax.

Next, the generated expression is evaluated using the expression evaluation processing section 97 (step 1202). If the evaluation result is unresolved, reference information generation processing is performed (step 120).
3). In the reference information generation processing, a reference information entry is generated in the reference information table 93. After the reference information generation processing is completed, or when the evaluation result by the expression evaluation processing unit 97 is not unresolved, an end determination processing is performed (step 120).
4). In the end determination processing, it is determined whether or not there is an unprocessed syntax. If there is an unprocessed syntax, the process returns to step 1201. If the syntax analysis has been completed for all the input source files, the syntax analysis ends.

Next, the operation of the operand determination processing section 98 will be described with reference to the flowchart of FIG. Operand determination processing section 98 is configured to refer to reference information table 9
3 is processed one by one from the top.
First, reference information end determination processing is performed (step 130).
1). In the reference information end determination processing, it is determined whether or not reference information still exists at the reference position. If there is still reference information, expression evaluation processing is performed (step 1302). When the processing has been completed for all pieces of reference information, the processing by the operand determination processing unit 98 ends.

In the expression evaluation processing, the expression information pointed to by the reference information being referred to is evaluated. If the evaluation result is unresolved, an error is determined (step 1303). If the evaluation result is not unresolved, reference information resolution processing is performed (step 1).
304). In the reference information resolution processing, the evaluation result of the expression information is embedded in the address value of the expression information at the position of the intermediate code pointed to by the reference information. Then, a reference position changing process is performed (step 1305). In the reference position change processing, the reference position of the reference information is changed to the position of the next reference information, and step 13
It returns to the reference information end determination processing of 01.

As described above, the expression evaluation processing unit 96 is called by both the syntax analysis unit 92 and the operand determination processing unit 98. Next, the operation of the expression evaluation processing by the expression evaluation processing unit 97 will be described with reference to the flowchart in FIG.

First, it is checked whether the node given by the virtual address exists in the memory (step 14).
01). If not, the node is loaded from the file to the memory (step 1402). Next, the virtual address is converted into a pointer (step 14).
03), the type of the node is checked (step 1404). Then, processing corresponding to the type of the node is performed (steps 1405 to 1411).

Expression evaluation processing unit 97 for performing such processing
Is called recursively. In this case, if the expression written in the operand in the assembler source has j terms, it will be called j times. Then, each time the expression evaluation processing unit 97 is called, it is necessary to check whether the node is on the memory and change the virtual address to a pointer.

That is, in the conventional assembler processing apparatus, the time required to check whether the node given by the virtual address is in the memory is T1,
The time required to change a virtual address to a pointer is T
2, the time taken when a given node is not in the memory and is loaded from a file is T3, and the number of times the given memory is not in the memory and loaded from a file is i
Time, the time required for the virtual memory processing of the expression processing is T
j was Tj = j × (T1 + T2) + i × T3.

[0016]

As described above, according to the conventional assembler processing apparatus, if the number of expressions in the operands in the source file is j, the expression evaluation processing unit j
Will be called twice. Therefore, the process of checking whether the node given by the virtual address exists in the memory and the process of changing the virtual address to a pointer are each performed j times, and there is a disadvantage that a great deal of processing time is required.

An object of the present invention is to provide an assembler processing apparatus and an assembler processing method which solve the above-mentioned conventional drawbacks, shorten the processing time and have high processing efficiency.

[0018]

In order to achieve the above object, the present invention provides an assembler processing apparatus in an operating environment without virtual memory management, an input means for reading a source file, and a syntax analysis of the read source file. Syntax analysis means, expression generation processing means for generating an expression of a parse tree in the syntax analysis processing, a temporary file for storing the generated expression as needed, and expression evaluation processing means for evaluating the generated expression, An operand determination processing unit for determining an operand when there is a forward reference; and an output unit for outputting a generated object file, wherein the expression generation processing unit overflows a memory buffer for storing a parse tree. In this case, insert a read instruction node at the root of the expression of the parse tree being generated, and And outputs it to the down temporary file, the expression evaluation processing means, performs a read from the temporary file in accordance with the contents of the node for the reading instruction,
The data is stored in the memory buffer.

In another aspect, the read instruction node has at least a position of a file to be read, the number of nodes to be read, a position to be read into a memory buffer, and a pointer to a root of an analysis tree.

In another aspect, the expression evaluation processing means reads all nodes designated by the read instruction node from the temporary file and stores the nodes in the memory buffer.

[0021] In another aspect, the read instruction node is stored in the memory buffer.

According to the assembler processing method of the present invention which achieves the above object, in an operating environment without virtual memory management, a step of reading a source file, a step of parsing the read source file, and a step of In the assembler processing method for performing assembler processing including the step of determining an operand when there is a forward reference and the step of determining an operand and outputting a generated object file, the step of performing the syntax analysis includes: Generating a parse tree and storing it in a memory buffer; inserting a read instruction node at the root of the parse tree formula being generated when the memory buffer overflows; and storing the contents of the memory buffer in a temporary file And the step of evaluating the generated expression, the step of evaluating the expression, Performs reading from the temporary file in accordance with the contents of the node for the serial reading instruction has a configuration including a step of storing in the memory buffer.

In another aspect, the step of determining the operand comprises the step of evaluating a generated expression.
The step of evaluating the expression includes a step of reading from the temporary file in accordance with the contents of the read instruction node and storing the read in the memory buffer.

[0024]

According to the present invention, the expression generation processing means inserts a read instruction node into the root of an expression of a parse tree being generated when the memory buffer for storing the parse tree overflows, and The contents of the memory buffer are output to the temporary file, and the expression evaluation processing means reads from the temporary file in accordance with the contents of the read instruction node, and reads the node for storing in the memory buffer. After that, it is guaranteed that the expression of the parse tree is read from the temporary file and stored in the circular node buffer. Each time a node is read, the virtual memory is referred to and the virtual address is converted into a pointer. No action is required.

In addition, since the temporary file is read in the designated unit according to the read instruction node, the number of times of access to the file is reduced as compared with the case where the read from the file is performed for each node.

[0026]

Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is a block diagram showing a configuration of an assembler processing apparatus according to one embodiment of the present invention.

As shown in the figure, the assembler processing apparatus 10 of the present embodiment includes a source file input unit 11 for reading a source file, a syntax analysis unit 12 for parsing the read source file, and a parsing tree in the syntax analysis processing. An expression generation processing unit 16 for generating an expression, a temporary file 17 for storing the generated expression as needed, an expression evaluation processing unit 18 for evaluating the generated expression, and an operand Operand determination processing unit 19 for determining
And an object file output unit 20 for outputting the generated object file.

The syntax analysis section 12 analyzes the syntax of the source file read by the source file input section 11, generates a reference information table 13 and an expression information table 14, and outputs the analyzed contents as an intermediate code 15. Here, the reference information table 13 is a table of reference information created when a forward reference is made. The expression information table 14 is
It is a table of the expression described in the operand when there is a forward reference. The intermediate code 15 is a code obtained by converting a source program into a machine language code. Further, the syntax analysis unit 12 generates a node of the expression information using the expression generation processing unit 16, and evaluates the generated expression using the expression evaluation processing unit 18.

FIG. 2 shows the relationship among the reference information table 13, the expression information table 14, and the intermediate code 15. When n forward references are described in the input source file, the reference information table 13
1a to 131n are created. Expression information table 1
4, expression information entries 141a to 141n are created. The created reference information has a pointer to the expression information being referred to and the position of the intermediate code 15 at the reference position.

Reference information table 13 and expression information table 1
4 shows a detailed configuration example of FIG. As illustrated, the expression information entry 141 is formed of a parse tree, and each node 1
Reference numeral 43 indicates another node by a pointer.
The read instruction node 142 has the position of the file to be read, the number of nodes to be read, the position to be read into the memory buffer, and a pointer to the root of the analysis tree. FIG.
As shown in the figure, the read instruction node 141 is generated in the read instruction buffer on the memory, and the node is generated in the circular node buffer. The read instruction buffer and the ring node buffer are, in principle, both arranged on the memory.

The expression generation processing unit 16 buffers the expression of the analysis tree generated under the control of the syntax analysis unit 12 in the read instruction buffer and the circular node buffer. In the buffering, when the memory buffer for generating the analysis tree becomes full, a read instruction node is inserted at the root of the expression of the analysis tree being generated, and the contents of the memory buffer are output to the temporary file 17.

The expression evaluation processing section 18 reads and evaluates the expressions buffered in the memory buffer. Also,
When the expression is stored in the temporary file 17, reading from the temporary file is performed by a read instruction node analysis process.

After completion of the syntax analysis by the syntax analysis unit 12, the operand determination processing unit 19 resolves the operand of the intermediate code 15 which has not been determined by the forward reference using the reference information table 13 and the expression information table 14. , Create object code. Then, an object file is generated and output from the object file output unit 20. The operand determination processing unit 19 evaluates the generated expression using the expression evaluation processing unit 18.

Next, the operation of this embodiment will be described with reference to the flowcharts of FIGS. FIG. 5 is a flowchart showing the operation of the syntax analysis processing by the syntax analysis unit 12. First, the syntax of the input source file is analyzed (step 501). Here, the parsing unit 9
2 generates an expression tree expression node using the expression generation processing unit 96 and analyzes the syntax. The node of the generated formula is inserted into the formula information table 14 by a buffering process.

Next, the generated expression is evaluated using the expression evaluation processing section 18 (step 502). If the evaluation result is unresolved, reference information generation processing is performed (step 503).
In the reference information generation processing, a reference information entry is generated in the reference information table 13. After the reference information generation processing ends, or when the evaluation result by the expression evaluation processing unit 18 is not unresolved, an end determination processing is performed (step 504). In the end determination processing, it is determined whether or not there is an unprocessed syntax. And if there are any unprocessed syntaxes, step 5
Returning to 01, if all the input source files have been analyzed, the analysis is terminated.

FIG. 6 is a flowchart showing the operation of buffering processing by the expression generation processing unit 16. First,
In order to store the nodes of the generated analytic tree equation in the memory buffer, an overflow check of the circular node buffer is performed (step 601). If overflow has not occurred, the node insertion processing for storing the node in the circular node buffer as it is is performed (step 604).

On the other hand, if the ring node buffer overflows, a read instruction node 142 is generated (step 602). In the read instruction node generation process, the reference position of the temporary file 17 is set as the position of the file to read the read instruction node 142, and the number of nodes in the ring node buffer excluding the parse tree being generated is set as the number of nodes to be read. The position of the first node in the ring node buffer is set as the position to be read into the memory buffer, and is generated in the read instruction buffer.

Next, all the nodes in the circular node buffer are output to the temporary file 17 except for the parse tree being generated (step 603). Then, the nodes after the overflow given by the expression generation processing unit 16 are added to the circular node buffer (step 604), and the processing is terminated.

FIG. 7 is a flowchart showing the operation of the operand determination processing by the operand determination processing unit 19. Operand determination processing section 19 refers to reference information table 1
3 is processed one by one from the top.
First, reference information end determination processing is performed (step 701).
In the reference information end determination processing, it is determined whether or not reference information still exists at the reference position. Then, if there is still reference information, expression evaluation processing is performed (step 702). When the processing has been completed for all pieces of reference information, the processing by the operand determination processing unit 19 ends.

In the expression evaluation processing, the expression information pointed to by the reference information being referred to is evaluated. If the evaluation result is unresolved, it is determined that an error has occurred (step 703). If the evaluation result is not unresolved, reference information resolution processing is performed (step 70).
4). In the reference information resolution processing, the evaluation result of the expression information is embedded in the address value of the expression information at the position of the intermediate code pointed to by the reference information. Then, a reference position changing process is performed (step 705). In the reference position change processing, the reference position of the reference information is changed to the position of the next reference information, and the process returns to the reference information end determination processing of step 701.

Next, referring to the flowchart of FIG.
The operation of the expression evaluation processing by the expression evaluation processing unit 18 will be described.
As shown in the figure, the expression evaluation processing unit 18 first checks which type the node is (step 801). Then, processing corresponding to the type of the node is performed (steps 802 to 810).

The contents of the processing in the expression evaluation processing unit 18 are as follows.
In principle, it is the same as the conventional one, but a read instruction node analysis process is added as a process not in the conventional expression evaluation process. In this processing, according to the content described in the read instruction node, the circular node buffer of the read position designated by the number of designated nodes from the position of the designated file to be read on the temporary file 17. To read.

Therefore, after the node is read by this processing, it is guaranteed that the expression of the parse tree is read from the temporary file 17 and stored in the circular node buffer. It is not necessary to refer to the virtual memory every time the data is read, and perform the process of converting the virtual address into a pointer.

In addition, since the temporary file 17 is read in the specified unit in accordance with the read instruction node, the number of times of access to the file is reduced as compared with the case where the read from the file is performed for each node. . That is, in the conventional assembler processing apparatus, the time taken when a given node is not in the memory and loaded from a file is T3, and the number of times the given memory is not in the memory and loaded from a file is i The total time required to access the file is i × T3. On the other hand, in the present embodiment, the read instruction node analysis process is called, and the number of times of accessing the file is smaller than i. Therefore, if the time required for the read instruction node analysis process is Tn, then Tn <j × T3 Holds.

Although the present invention has been described with reference to the preferred embodiments, the present invention is not necessarily limited to the above embodiments.

[0046]

As described above, according to the present invention,
Since it is not necessary to refer to the virtual memory every time a node is read and to convert the virtual address into a pointer, specifically, in the conventional assembler processing, the term of the expression written in the operand of the source file is replaced by j If the time required to check whether the node given by the virtual address is in the memory is T1 and the time required to change the virtual address to a pointer is T2, J × (T1
+ T2) can be shortened.

Further, by reading from the temporary file in designated units in accordance with the read instruction node, the number of times of access to the file is reduced as compared with the case of reading from the file for each node. Therefore, the assembler processing time can be further reduced. Specifically, in the conventional assembler processing apparatus, the time required when a given node is not in the memory and is loaded from a file is T3, and the number of times the given memory is not in the memory and loaded from a file is i times. In this case, the total time required for accessing the file is i × T3. On the other hand, in the present embodiment, the read instruction node analysis process is called, and the number of times of accessing the file is smaller than i. Therefore, assuming that the time required for the read instruction node analysis process is Tn, Tn <j × T3 holds. Therefore, since the total processing time in the conventional assembler processing is Tj = j × (T1 + T2) + j × T3, it is possible to reduce the time represented by Tj−Tn> j × (T1 + T2).

[Brief description of the drawings]

FIG. 1 is a block diagram showing a configuration of an assembler processing apparatus according to one embodiment of the present invention.

FIG. 2 is a diagram showing a relationship among a reference information table, an expression information table, and an intermediate code according to the embodiment.

FIG. 3 is a block diagram illustrating a configuration of a reference information table and a formula information table according to the present embodiment.

FIG. 4 is a block diagram illustrating a configuration of a memory buffer according to the present embodiment.

FIG. 5 is a flowchart illustrating an operation of a syntax analysis unit according to the embodiment.

FIG. 6 is a flowchart illustrating an operation of a buffering process according to the present embodiment.

FIG. 7 is a flowchart illustrating an operation of an operand determination processing unit according to the embodiment;

FIG. 8 is a flowchart illustrating the operation of the expression evaluation processing unit according to the present embodiment.

FIG. 9 is a block diagram illustrating a configuration of a conventional assembler processing device.

FIG. 10 is a diagram showing a relationship among a reference information table, an expression information table, and an intermediate code in a conventional assembler processing apparatus.

FIG. 11 is a block diagram showing a configuration of a reference information table and a formula information table in a conventional assembler processing apparatus.

FIG. 12 is a flowchart illustrating an operation of a syntax analysis unit of a conventional assembler processing device.

FIG. 13 is a flowchart illustrating an operation of an operand determination processing unit of a conventional assembler processing device.

FIG. 14 is a flowchart showing the operation of a formula evaluation processing unit of a conventional assembler processing device.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 10 Assembler processing apparatus 11 Source file input part 12 Syntax analysis part 13 Reference information table 14 Expression information table 15 Intermediate code 16 Expression generation processing part 17 Temporary file 18 Expression evaluation processing part 19 Operand determination processing part 20 Object file output part

Claims (6)

(57) [Claims] In an assembler processing apparatus in an operating environment without virtual memory management, input means for reading a source file, syntax analysis means for parsing the read source file, and generating an expression of a parse tree in the syntax analysis processing Expression generation processing means, a temporary file for storing the generated expressions as needed, expression evaluation processing means for evaluating the generated expressions, and operand determination processing means for determining the operand when there is a forward reference And an output unit for outputting the generated object file, wherein the expression generation processing unit includes a read instruction for reading at the root of the expression of the analytic tree being generated when the memory buffer for storing the analytic tree overflows. Inserting a node, and outputting the contents of the memory buffer to the temporary file; An assembler processing apparatus for reading from a temporary file according to the contents of the read instruction node and storing the read data in the memory buffer. 2. The read instruction node includes at least a position of a file to be read, the number of nodes to be read,
2. The assembler processing apparatus according to claim 1, wherein the assembler processing apparatus has a position to be read into a memory buffer and a pointer to a root of an analysis tree. 3. The assembler process according to claim 2, wherein said expression evaluation processing means reads all nodes specified by said read instruction node from said temporary file and stores them in said memory buffer. apparatus. 4. The assembler processing apparatus according to claim 1, wherein said read instruction node is stored in said memory buffer. 5. A step of reading a source file in an operating environment without virtual memory management, a step of parsing the read source file, and a step of determining an operand when a forward reference is made to a result of the parsing. Performing the steps;
Determining an operand and outputting a generated object file.In the assembler processing method for performing assembler processing, the step of performing the syntax analysis includes the steps of: generating a parse tree and storing the parse tree in a memory buffer; When the memory buffer overflows, insert a read instruction node at the root of the expression of the parse tree being generated,
And outputting the contents of the memory buffer to a temporary file; and evaluating the generated expression. The step of evaluating the expression includes reading from the temporary file according to the contents of the read instruction node. And storing the result in the memory buffer. 6. The step of determining the operands includes the step of evaluating a generated expression, wherein the step of evaluating the expression includes reading from the temporary file according to contents of the read instruction node. 6. The assembler processing method according to claim 5, further comprising the step of: storing the data in the memory buffer.