JP2828264B2 - Method for manufacturing semiconductor device - Google Patents

Description

Description: TECHNICAL FIELD The present invention relates to a method for manufacturing a semiconductor device.
P on the semiconductor substrate in Bi CMOS type semiconductor integrated circuits, etc.
The present invention relates to a method for forming a type buried layer and an N type buried layer.

(Prior Art) As a conventional method of forming a P-type buried layer and an N-type buried layer in a semiconductor substrate, a conventional method of manufacturing a BiCMOS type semiconductor integrated circuit will be described with reference to FIG.

In FIG. 2, reference numeral 1 denotes a P-type semiconductor substrate.
An N ⁺ buried layer 2 and a P ⁺ buried layer 3 are formed in a type semiconductor substrate 1.
Here, the N ⁺ buried layer 2 is provided in the NPN bipolar transistor forming region 4 to reduce the collector series resistance of the NPN bipolar transistor, and the P-channel MOS transistor is provided in the P-channel MOS transistor forming region 5 by a parasitic bipolar operation. It is formed so as not to wake up.
On the other hand, the P ⁺ buried layer 3 is formed in the element isolation region 6 of the NPN bipolar transistor in order to shorten the time of the isolation diffusion from above after the epitaxial layer growth,
The N-channel MOS transistor is formed in the N-channel MOS transistor forming region 7 so as not to cause a parasitic bipolar operation. The N ⁺ buried layer 2 and the P ⁺ buried layer 3 are manufactured by repeating a cycle of thermal oxidation, photolitho etching, and thermal diffusion twice, and the N ⁺ buried layer 2 is usually
It is formed to 20-100Ω / □ by using As or Sb, and the P ⁺ buried layer 3
Is usually formed using B (boron) at 50 to 300 Ω / □.

An N ^- epitaxial layer 8 is grown on the substrate 1 on which the N ⁺ buried layer 2 and the P ⁺ buried layer 3 have been formed as described above. At this time, the concentration and thickness of the epitaxial layer 8 are determined so that the device characteristics of the NPN bipolar transistor and the gate threshold voltage of the P-channel MOS transistor can be controlled. At this time, the N ⁺ buried layer 2 and the P ⁺ buried layer 3 diffuse upward in the epitaxial layer 8.

Thereafter, a P-type impurity is diffused from above into the N-channel MOS transistor formation region 7 and the epitaxial layer 8 in the element isolation region 6 to form a P ⁻ diffusion region 9. The P ^-
Diffusion region 9 is formed so as to reach P ⁺ buried layer 3, and NP
Device isolation of N bipolar transistor and N channel MOS
It is formed to control the threshold voltage of the transistor.

Thereafter, after selectively forming a thick device isolation oxide film 10 on the epitaxial layer 8, a P diffusion layer 11 as an active base of the NPN bipolar transistor is formed in the epitaxial layer region 8a of the NPN bipolar transistor formation region 4. I do. Thereafter, the p-diffusion region 9 on the epitaxial layer region 8b of the p-channel MOS transistor formation region 5 and the p ^- diffusion region 9 of the n-channel MOS transistor formation region 7
On the gate oxide film 12 and the gate electrode 13 of the MOS transistor
To form Subsequently, the source / drain of the P-channel MOS transistor and the inactive base of the NPN bipolar transistor (to make ohmic contact) are formed in the epitaxial layer region 8b of the P-channel MOS transistor formation region 5 and the P diffusion layer 11 as an active base. P ⁺ diffusion layer 14 is formed. Further, in the P ^- diffusion region 9 of the N-channel MOS transistor formation region 7 and the P-diffusion layer 11 as an active base and in the epitaxial layer region 8a where the active base is formed, the source / source of the N-channel MOS transistor is formed.
An N ⁺ diffusion layer 15 is formed as a drain and collector take-out portion of the NPN bipolar transistor. Thus, the BiCMOS type semiconductor integrated circuit is completed.

(Problems to be Solved by the Invention) However, in the conventional manufacturing method as described above, since the N ⁺ buried layer 2 and the P ⁺ buried layer 3 are formed through separate photolithography steps, both buried layers are formed. In addition to the space required to obtain a withstand voltage, a margin for alignment of about 1 to 2 μm is required between the devices 2 and 3, which hinders miniaturization of the device.

As a more improved method, as described in Nikkei Microdevices November 1986, p ^.
The portion where the buried layer is to be formed is covered with a Si ₃ N ₄ film, and this Si ₃ N ₄
Using the N ₄ film as a mask, ion-implant Sb for forming an N ⁺ buried layer, and then drive in an oxidizing atmosphere and simultaneously
There is a method of forming a thick oxide film in the region where the is implanted, removing the Si ₃ N ₄ film, implanting B ⁺ for forming a P ⁺ buried layer, and driving in.

According to this method, since the N ⁺ buried layer and the P ⁺ buried layer are formed by self-alignment, no alignment margin is required.

However, in this method, since the N ⁺ buried layer and the P ⁺ buried layer are close to each other, there is a problem that the method can be applied only to a device having a low isolation breakdown voltage.

SUMMARY OF THE INVENTION The present invention has been made in view of the above points, and provides a method of manufacturing a semiconductor device which does not require a margin for alignment between an N-type buried layer and a P-type buried layer, and which can increase isolation voltage by separating both buried layers. The aim is to provide a method.

(Means for Solving the Problems) According to the present invention, a polycrystalline silicon film is formed on a surface of a semiconductor substrate, and a polycrystalline silicon film is selectively formed in a P-type buried layer forming portion and an N-type buried layer forming portion. The polycrystalline silicon film is left only in the P-type buried layer forming portion and the N-type buried layer forming portion by utilizing the etching rate difference depending on the presence or absence of the P-type impurity. After forming an oxide film on the entire surface of the remaining polycrystalline silicon film and the surface of the substrate, a concave portion is formed in a part of the oxide film to expose the upper surface of the polycrystalline silicon film in the portion where the N-type buried layer is formed. Removing the polycrystalline silicon film, ion-implanting N-type impurities into the N-type buried layer forming portion of the semiconductor substrate through the concave portion of the oxide film and the removed portion of the polycrystalline silicon film, and then performing heat treatment. By the N-type of the substrate An N-type buried layer is formed in the impurity ion-implanted portion where the buried layer is formed, and at the same time, a P-type buried layer is formed in the P-type buried layer forming portion of the substrate by diffusing P-type impurities from the remaining polysilicon film. Form a layer.

(Operation) In the above method, a P-type impurity is selectively introduced into a polycrystalline silicon film on the surface of a semiconductor substrate, and a polycrystalline silicon film is formed on the substrate by utilizing an etching rate difference depending on whether or not the P-type impurity is introduced. By selectively leaving above, the N-type buried layer pattern and the P-type buried layer pattern are determined at the same time.
Therefore, there is no need for a margin for alignment between the buried layers. In addition, by selectively leaving the polycrystalline silicon films apart from each other, the distance between both buried layers can be increased.

(Embodiment) An embodiment of the present invention will be described below with reference to process sectional views of FIGS. 1 (a) to 1 (h).

First, as shown in FIG. 1A, a polycrystalline silicon film 22 having a thickness of about 6000 to 7000 is formed on a P-type semiconductor substrate 21 by a known CVD method.

Next, as shown in FIG.
After forming a resist pattern 23 by a known photolithographic technique above, using this resist pattern 23 as a mask, P ⁺
Polycrystalline silicon film (especially code polycrystalline silicon film (especially reference numeral 22a) and N ⁺ buried layer forming part of the buried layer forming portion
22b) with a dose of 8 × 10 ¹⁴ cm ^{−2 to} 5 × 10 ¹⁵ cm ⁻² and an energy of 30 to 40 K by a known ion implantation technique.
Inject at about eV.

Next, after removing the resist pattern 23, a heat treatment is performed at 800 ° C. to 850 ° C. for about 5 minutes to 10 minutes in an atmosphere of an inert gas such as nitrogen to activate the boron (P ⁺ -type impurity).

Next, as shown in FIG. 1C, a portion of the polycrystalline silicon film 22 where boron (P ⁺ -type impurity) is not ion-implanted is 4,000 to 50, using a known KOH-based anisotropic etching solution.
00Å Selectively remove by etching. At this time, the selective etching of the polycrystalline silicon film as described above is based on the KOH-based anisotropic etching as disclosed in the literature “Applied Physics 53 [10] (1984) P880-881”. Is
This is because the etching rate has an impurity concentration dependency.

Next, the entire surface of the polycrystalline silicon film 22 is etched by a known reactive ion etching to a thickness of about 2000 to 3000 mm. By this etching, as shown in FIG. 1 (d), the polycrystalline silicon film 22 other than the P ⁺ buried layer forming portion and the N ⁺ buried layer forming portion is entirely removed, and the P ⁺ buried layer forming portion and Only the polycrystalline silicon films 22a and 22b in the portion where the N ⁺ buried layer is formed remain. Also, the polycrystalline silicon films 22a and 22b have a thickness of 2
It is etched about 000Å-3000Å.

Next, as shown in FIG. 1E, an oxide film 24 having a thickness of about 12,000 to 15,000 is formed on the semiconductor substrate 21 and the polycrystalline silicon films 22a and 22b by a known CVD method.

Thereafter, as shown in FIG. 1 (f), a resist pattern 25 is formed on the oxide film 24 by a known photolithography method, and then the oxide film 24 is etched using the resist pattern 25 as a mask to form a concave portion 26. , The surface of the polycrystalline silicon film 22b at the portion where the N ⁺ buried layer is to be formed is exposed.

Subsequently, using the resist pattern 25 and the oxide film 24 as a mask, the exposed polycrystalline silicon film 22b at the portion where the N ⁺ buried layer is to be formed is removed by reactive ion etching as shown in FIG. 1 (g). Then, as shown in the figure, using the resist pattern 25 and the oxide film 24 as a mask, the N ^{+ of the} semiconductor substrate 21 is passed through the portion where the polycrystalline silicon film 22b is removed.
Antimony (N ⁺ -type impurity) is dosed to the buried layer forming portion at a dose of about 1 × 10 ¹⁵ cm ^{−2 to} 3 × 10 ¹⁵ cm ⁻² and an energy of 40 to 60 Ke.
Inject at about V.

Then, after removing the resist pattern 25, in an inert gas atmosphere such as argon containing a small amount of oxygen, 1150 ℃
A heat treatment of about 1200 ° C. for about 120 minutes to 180 minutes is performed. By this heat treatment, the N ⁺ -type impurity (antimony) is activated, N ⁺ buried layer 27 is formed on the N ⁺ buried layer forming part of the substrate 21 as shown in FIG. 1 (h), at the same time multi Crystalline silicon film 22
Boron (P ⁺ type impurity) is diffused from
P ⁺ buried layer 28 is formed on the first P ⁺ buried layer forming portion. At this time, an oxide film 29 is formed on the surface of N ⁺ buried layer 27 at the same time.

Thereafter, by removing the oxide films 24 and 29 and the polycrystalline silicon film 22a, a substrate having the P ⁺ buried layer 28 and the N ⁺ buried layer 27 is completed, and when manufacturing a BiCMOS semiconductor integrated circuit, Thereafter, the BiCMOS semiconductor integrated circuit is completed by performing the same process as the conventional process.

(Effects of the Invention) As described above in detail, according to the manufacturing method of the present invention, a polycrystalline silicon film is selectively left on a substrate by utilizing a difference in etching rate depending on whether a P-type impurity is introduced or not. Accordingly, the N-type buried layer pattern and the P-type buried layer pattern are determined at the same time, so that there is no need for a margin for matching between the two buried layers, and the element can be reduced in size. Also,
By determining the mutual distance of the polycrystalline silicon films to be selectively left in accordance with the isolation withstand voltage, the distance between both the buried layers can be separated in accordance with the isolation withstand voltage, so that a high isolation withstand voltage is required. The present invention is also applicable to a method for manufacturing a semiconductor device.

[Brief description of the drawings]

FIG. 1 is a process sectional view showing one embodiment of a method for manufacturing a semiconductor device according to the present invention, and FIG. 2 is a sectional view for explaining a method for manufacturing a conventional BiCMOS type semiconductor integrated circuit. 21: P-type semiconductor substrate, 22, 22a, 22b: polycrystalline silicon film, 24: oxide film, 26: recess, 27: N ⁺ buried layer, 28 ...
… P ⁺ buried layer.

Continuation of the front page (58) Field surveyed (Int.Cl. ⁶ , DB name) H01L 27/06 H01L 29/72

Claims (1)

(57) [Claims] (A) forming a polycrystalline silicon film on a surface of a semiconductor substrate; and (b) selectively forming a polycrystalline silicon film in a P-type buried layer forming portion and an N-type buried layer forming portion. (C) introducing a P-type buried layer forming part and an N-type buried layer forming part by using the etching rate difference depending on whether or not the P-type impurity is introduced. (D) forming an oxide film on the entire surface of the remaining polycrystalline silicon film and on the substrate surface; and (e) forming a recess in a part of the oxide film to form the N-type buried portion. Exposing the upper surface of the polycrystalline silicon film at the portion where the embedded layer is formed, and further removing the polycrystalline silicon film; and (f) thereafter, removing the polycrystalline silicon film through the concave portion of the oxide film and the polycrystalline silicon film. N-type impurity ions Implanting, (g) Thereafter, by heat treatment, at the same time to form the N-type buried layer in the impurity ion implantation portion is N-type buried layer forming part of the substrate, P from the remaining polycrystalline silicon film
Forming a P-type buried layer in a portion of the substrate where a P-type buried layer is formed by diffusion of a type impurity.