JP2829100B2 - Bus contention circuit - Google Patents

Description

Description: TECHNICAL FIELD The present invention relates to an information processing system, and more specifically, a bus contention circuit for controlling contention when a plurality of devices access a common device via a bus. About.

(Prior Art) In a conventional bus contention system, a plurality of contention participants are accommodated in a bus connected to a common device such as a common memory, and the contention of access to the common device among the contention participation devices is determined. A bus contention circuit is provided for control. When an access to the common memory occurs from a plurality of contention participating devices, the bus contention circuit gives priority to the earlier access among those accesses. Also,
If access occurs simultaneously from multiple competing participants,
The bus contention circuit is based on the priority
One competitive participant is selected in a predetermined priority order set in the encoder, and access to the common memory is permitted to the selected one.

(Problems to be Solved by the Invention) Therefore, in such a conventional bus contention circuit, contention control is performed such that a specific one of a plurality of contention participation devices is always given priority to access the common memory. Can't do it.

SUMMARY OF THE INVENTION It is an object of the present invention to provide a bus contention circuit which can solve the above-mentioned disadvantages of the prior art and can give a specific contention participant an access priority after a predetermined time.

(Means for Solving the Problems) In order to solve the above-described problems, the present invention is configured to connect a first device connected to a common device via a bus and at least one second device, In a bus contention circuit that controls contention when a first device and a second device access a common device, the first device outputs an access request signal requesting access to the common device, and responds to the access request signal. In response to the response signal, a common device is accessed via the bus, and the second device has a guard time long enough to guarantee access of the first device to the common device and a second guard time following the guard time. Output a guard signal defining an access time of a length necessary for the first device to access the common device, access the common device at the access time, and use the first and second devices. Contention control means connected to the device for controlling contention between the first and second devices, the contention control means receiving an access request signal at least before the start of the guard time of the guard signal. The first device corresponding to the signal is selected in a predetermined order, a response signal is output to the selected first device, and the second device accesses a common device during the guard signal access time.

(Operation) According to the present invention, the first device outputs an access request signal to the contention control means, and accesses a common device via the bus when a response signal is input from the contention control means. The second device outputs a guard signal including a guard time and an access time, and accesses a common device within the access time. The contention control means receives a guard signal from the second device and an access request signal from the first ordinary device,
A response signal is output to one selected first device in a predetermined order. When only the access request signal is input and when the access request signal and the guard signal are simultaneously input, a response signal is output immediately. With this simultaneous input, the first device terminates the access during the guard time, and the second device terminates the access during the access time. When the guard signal is input before the access request signal, the contention control means outputs a response signal after the guard signal ends.

Embodiment Next, an embodiment of a bus contention circuit according to the present invention will be described in detail with reference to the accompanying drawings. In the embodiment of the bus contention circuit according to the present invention, a plurality of contention participants are accommodated in a bus connected to a common device such as a common memory, and contention for access to the common device among the contention participation devices is controlled. You. At this time, a specific competing participant is always given priority over other competing participants. In the present specification, the former is called a priority device, and the latter is called a normal device. In this embodiment, both the ordinary device and the priority device compete for access to the memory. The priority device outputs a guard signal and acquires the access priority after a predetermined time.

For a better understanding of the present invention, an example of a conventional bus contention system will be described with reference to FIG. 4 prior to the description of an embodiment of the present invention. A plurality (n + 1) stage of contention participation device 32 ^(# 0~ ^{# n),} prior to access to the memory 33 from bus d, busy signal BSY from the bus contention control circuit 31
And when it is inactive, the corresponding access request signals REQ0 to REQ0 to
Make REQn active (negative logic).

As shown in FIG. 5, the bus contention control circuit 31 includes a priority encoder 35, a flip-flop (FF) 36, and a decoder 37. The priority encoder 35 outputs an access request signal ▲ ▼ to ▲
When any one of ▼ becomes active, the enable signal C is output to the flip-flop 36. When a plurality of access request signals REQ- occur, one of them is selected in a predetermined priority order, and the output to the input D of the flip-flop 36 corresponding to the selected access request signal REQ- is output. Activate. In response, flip-flop 36 activates output Q. The decoder 37
This is decoded and the corresponding one of the response signals ▼ to ア ク テ ィ ブ is activated (negative logic). The response signal of the plurality of competing participants 32 (FIG. 4)
The device to which ▼ is input accesses the memory 33.

In this conventional example, when a request signal REQ- for simultaneously accessing from a plurality of contention participation devices is generated, the bus contention control circuit 31 selects one contention participation device 32 in a predetermined priority order set in the priority encoder. Then, correspondingly, access to the memory 33 is permitted.

FIG. 1 shows an embodiment of a bus contention circuit according to the present invention. In this embodiment, two devices 51 and 52 are used as competing participants.
Are accommodated in the bus 3, which compete with each other and
The common memory 6 can be accessed via the. One of the competing participating devices, 51 in this embodiment, is a priority device, and the other device 52 is a normal device having a lower priority than the former. The priority device 51 always has a higher priority than the normal device 52 and does not lose the contention in accessing the memory 6 with the normal device 52. When accessing the memory 6, the priority device 51 is configured to output a guard signal GAD to be described later from the output 10 to the bus contention control circuit 4. Prior to accessing the memory 6, the normal device 52 outputs an access request signal REQ to the bus contention control circuit 4 and confirms the response signal ACK, thereby starting access to the memory 6 from the bus 3. Have been.

FIG. 2 shows a specific circuit configuration of the bus contention control circuit 4. The circuit 4 has a configuration in which a NAND gate 14, a flip-flop 18 and a NOR gate 16 are connected as shown. The flip-flop 18 receives the guard signal GAD from the priority device 51 at the input. This is inactive,
▲ ▼ active from NAND gate 14 for input
When the input corresponding to
18 activates its output Q and, in response,
Gate 16 outputs a significant response signal ▲ ▼.

FIG. 3 shows a timing waveform in the return control of the response signal ACK by the bus contention control circuit 4. The significant period of the guard signal GAD of the priority device 51 includes a portion corresponding to the guard period TG having a predetermined length and a portion corresponding to the access period T0 as shown in the figure. The length of the guard period TG is usually
It is set to a length of time that guarantees access to the memory 6 of 52. Of course, the length of the access period T0 depends on the priority device.
51 is set to a length necessary to access the memory 6.

The access request signal REQ and the response signal ACK input / output to / from the normal device 52 in response to such a guard signal GAD output from the priority device 51 are indicated by numerals 1, 2 and 3 in circles in FIG. It occurs in any of the three timing relationships as described above. In the first timing relation, the access request signal ▲ ▼ becomes active before the rising time t1 of the guard signal GAD, and in the second timing relation, the access request signal ▲ ▼ becomes active at the same time as the rising time t1 of the guard signal GAD. Active. In both cases, the priority device 51 is replaced by the normal device 52.
Is given priority to access the memory 6, and the bus contention control circuit 4
In response to REQ, a response signal ACK is provided to the ordinary device 52. Although not shown in this example, in an embodiment in which a plurality of ordinary devices 52 are provided, when the access request signal REQ occurs at the first or second timing shown in the figure, the bus contention control circuit 4 One of the plurality of access request signals REQ is selected with a predetermined priority, and a response signal ACK is output to one of the ordinary devices 52 corresponding thereto. The normal device 52 thus selected is guaranteed to access the memory 6 during the guard period TG, and the priority device 51 sets the guard period TG
, The memory 6 can be accessed during the access period TQ following.

By the way, as shown in FIG.
Normal device 5 within the significant period of 51 output guard signal GAD
Whenever the access request signal REQ is generated from 2, the bus contention control circuit 4 preferentially processes the access from the priority device 51 and waits for the fall of the guard signal GAD to output the response signal ACK to the ordinary device 52. I do. Therefore, regarding the access to the memory 6, the priority device 51 accesses first in the access period T0, and the ordinary device 52 accesses after the end of the guard signal GAD, that is, after time t2.

(Effects of the Invention) According to the present invention, when access competition is controlled using an access request signal for requesting access to a common device and a response signal indicating a bus contention control result for the access request signal, a plurality of contention participation devices Among them, a specific device preferentially treated is configured to output a guard signal. This ensures that even if other competing participants lose the competition, they will always be able to access them after a predetermined guard time. The present invention is effective in, for example, an application example in which, when a packet assembling circuit of an electronic exchange packetizes an input signal and stores the packet in a memory, the packet assembling circuit is given priority over another and competition control is performed.

[Brief description of the drawings]

FIG. 1 is a functional block diagram showing an embodiment of a bus contention circuit according to the present invention, FIG. 2 is a functional circuit diagram showing a configuration example of a bus contention control circuit in the embodiment shown in FIG. 1, and FIG. FIG. 4 is a time chart of the circuit shown in FIG. 2, and FIG.
FIG. 5 is a circuit diagram of the bus contention control circuit in the conventional example shown in FIG. Description of Signs of Main Part 3 Bus 4 Bus contention control circuit 51 Priority device 52 Normal device

Continuation of the front page (72) Inventor Kuta Saito 1-1-6 Uchisaiwaicho, Chiyoda-ku, Tokyo Nippon Telegraph and Telephone Corporation (72) Inventor Hiroshi Fujitani 1-1-6 Uchisaiwaicho, Chiyoda-ku, Tokyo Nippon Telegraph and Telephone Corporation In-company (56) References JP-A-60-238962 (JP, A) JP-A-61-264463 (JP, A) (58) Fields investigated (Int. Cl. ⁶ , DB name) G06F 13/362 G06F 15/16 360

Claims (2)

(57) [Claims] 1. A first device connected to a common device via a bus.
A bus contention circuit connected to the first device and at least one second device for controlling contention when the first and second devices access the common device, wherein the first device includes the common device. Outputting an access request signal for requesting access to the device; accessing the common device via the bus in response to a response signal to the access request signal; Outputting a guard signal defining a guard time long enough to guarantee access to the common device and an access time following the guard time necessary for the second device to access the common device; Accessing the common device at the access time, wherein the bus contention circuit is connected to first and second devices;
Competition control means for controlling contention between the first and second devices, the contention control means receiving the access request signal at least before the start of the guard time of the guard signal,
Selecting a first device corresponding to the access request signal in a predetermined order, outputting the response signal to the selected first device, wherein the second device selects the common device at the access time of the guard signal. A bus contention circuit for accessing a device. 2. The circuit according to claim 1, wherein, when the access request signal is input after the guard time of the guard signal is started, the contention control means sets the response after the end of the access time of the guard signal. A bus contention circuit for outputting a signal.