JP2830009B2 - Decryption device - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a decoding apparatus adapted to a case where, for example, an 8-bit digital image signal is compressed to 2 bits and transmitted.

[Conventional technology]

A block that calculates the two-dimensional correlation of a digital image signal, divides the digital image signal into small regions, and encodes a plurality of pixels contained in the block into a code signal having a bit number shorter than the original bit number. Coding is known.

The applicant of the present application obtains a dynamic range, which is a difference between the maximum value and the minimum value of a plurality of pixels included in a two-dimensional block, as described in JP-A-61-144989.
An adaptive coding device that performs coding adapted to the dynamic range has been proposed. Further, as described in Japanese Patent Application Laid-Open No. 62-92620, an adaptive coding apparatus that performs coding adaptive to a dynamic range with respect to a three-dimensional block formed from pixels in an area included in each of a plurality of frames is proposed. Have been. Further, as described in Japanese Patent Application Laid-Open No. 62-128621, a variable length encoding method in which the number of bits changes according to a dynamic range so that the maximum distortion generated when quantization is performed is constant. Proposed.

Coding adapted to these dynamic ranges (ADRC
Is referred to as "), the image quality is little degraded and the efficiency is high. On the decoding side of the ADRC, when the number of quantization bits is n, the median of the level range obtained by dividing the dynamic range into 2 ⁿ is output as the decoding level.

However, when the number of quantization bits of ADRC is small,
In the case where only higher-order bits of a code signal obtained by ADRC are transmitted in order to further compress transmission data, there is a problem that an error (quantization distortion) between the restored data and the original data increases.

In order to solve this problem, the present applicant has disclosed Japanese Patent Laid-Open No.
As described in Japanese Patent Application Laid-Open No. 200884, a correction code corresponding to the magnitude relationship between a target pixel and surrounding pixels is formed, this correction code is added to an encoded code of the target pixel, and the result of the addition is decoded. To propose a decryption device. According to this decoding apparatus, a decoding level having a more subdivided decoding level is obtained, and quantization distortion is reduced, as compared with a case where no countermeasure is taken.

[Problems to be solved by the invention]

Since the previously proposed method focuses on the magnitude relationship between the pixel of interest and surrounding pixels, even if the image in the block is effective for a flat image, the edge of the image is not included in the block. In some cases, the error cannot be reduced sufficiently.

Therefore, an object of the present invention is to generate a correction code in accordance with a pattern of a target pixel and a peripheral pixel, thereby obtaining a high-quality restored image corresponding to a bit number larger than the bit number of each transmitted pixel. It is to provide a device.

[Means for solving the problem]

The present invention converts the received transmission data having the first number of bits into a second number of bits having a number of bits larger than the first number of bits.
In a decoding device for converting into pixel data having the number of bits, a means for extracting peripheral pixels based on the transmission data of the pixel of interest, transmission data of the pixel of interest, and transmission data of the plurality of extracted peripheral pixels. Means for forming a pattern, a memory means for generating a correction code based on the bit pattern, and means for forming transmission data of the pixel of interest as upper bits and forming the correction code as lower bits to form composite data; The decoding device is characterized in that, in each address corresponding to the bit pattern of the means, the one having a maximum occurrence frequency in a predetermined period among a plurality of correction codes is stored.

[Action]

The answer (correction code CR) corresponding to the pattern classification is stored in the memory 25 on the receiving side. The pattern is classified by 10 bits consisting of received data of a target pixel to be decoded and peripheral pixels (for example, four pixels). This pattern is supplied to the memory 25 as an address signal,
The correction code CR is read from the memory 25. The correction code CR is set as the lower bits of the target pixel, and is synthesized with the received upper bits by the synthesizing circuit 26. 4 from synthesis circuit 26
The bit code is supplied to the ADRC decoding circuit 27, and the 8-bit code is restored.

Since the lower bits not transmitted by the pattern classification are restored, the quality of the restored image can be improved.

〔Example〕

An embodiment of the present invention will be described below with reference to the drawings. FIG. 1 shows the configuration of the transmitting side of this embodiment, and digital video data in which one sample is digitized to 8 bits is supplied to an input terminal indicated by 1.
The video data is converted by the blocking circuit 2 from a scan line order to a block order. For example, if the screen of one frame is as shown in FIG.
Pixel).

The output signal of the blocking circuit 2 is supplied to the maximum and minimum value detection circuit 3 and the delay circuit 4. The detection circuit 3 detects the maximum value MAX and the minimum value MIN of the block. The delay circuit 4 delays data for a time for detecting the maximum value MAX and the minimum value MIN. The calculation of (MAX−MIN) is performed in the subtraction circuit 5, and the dynamic range DR is obtained from the subtraction circuit 5.
The dynamic range DR is supplied to the division circuit 6, and the dynamic range DR is set to 1/16. The division circuit 6 can be constituted by a shift circuit. A quantization step Δ is obtained from the division circuit 6. In the subtraction circuit 7, the minimum value MIN is subtracted from the video data from the delay circuit 4, and video data from which the minimum value has been removed is obtained from the subtraction circuit 7.

The output data of the subtraction circuit 7 and the quantization step Δ are supplied to the quantization circuit 8. From the quantization circuit 8, a quantization code DT having a bit number smaller than the original bit number (8 bits), for example, 4 bits is obtained. This quantized code DT is supplied to the separating circuit 9 and the upper two-bit code DTu and the lower two bits
It is divided into bit codes DTL. The code DTu is supplied to the framing circuit 10 and the correction code generation circuit 11, and the code
DTl is supplied to the correction code generation circuit 11.

The quantization circuit 8 performs quantization adapted to the dynamic range DR. In other words, if the dynamic range DR is (2 ⁴ = 1
6) In the equally divided quantization step Δ, the video data from which the minimum value has been removed is divided, and the value obtained by rounding down the quotient and converting it into an integer is used as the quantization code DT. The quantization circuit 8 can be constituted by a division circuit or a ROM.

The dynamic range DR, the minimum value MIN, and the code DTu are converted into transmission data by the framing circuit 10, and the switching circuit
Supplied to 12. The framing circuit 10 forms transmission data to which the dynamic range DR, the minimum value MIN, and the code DTu are arranged byte-serial and to which a synchronization signal is added.
In addition, the framing circuit 10 generates additional codes (DR, MI
N) and the error correction code for the code DTu are encoded. As described above, in this embodiment, the original data of 8 bits per pixel is compressed by the ADRC into a 4-bit quantization code, and the upper 2 bits of the quantization code are selected and transmitted.

The correction code CR generated by the correction code generation circuit 11 is supplied to the switch circuit 12. Transmission data is taken out to the output terminal 13 of the switch circuit 12. The correction code CR is
It occurs once in each frame and is transmitted prior to transmission data using a blanking period or the like. The transmission path is, for example, a recording and reproducing process composed of a magnetic tape and a rotary head.

FIG. 3 shows the configuration of the receiving side, and received data is supplied to an input terminal indicated by 21. The received data is a switch circuit
22 and is divided into transmission data and correction data CR. The transmission data is supplied to the frame decomposition circuit 23, and the correction data CR is written in the memory 25.

In the frame decomposition circuit 23, the error correction code is decoded, and the dynamic range DR, the minimum value MIN, and the code DTu are separated. The code DTu is supplied to the peripheral pixel detection circuit 24, and as shown in FIG. 4, the pixel data Au,
Bu, Cu, and Du (2 bits × 4 = 8 bits) are output from the peripheral pixel detection circuit 24. If all the four peripheral pixels do not exist because the pixel near the boundary of the block is the target pixel, the peripheral pixels are turned back around the target pixel and used. For example, if the pixel at the upper left corner of the block is the target pixel, there is no pixel data Au and Bu, so the pixel data Du is referred to instead of Au, and the pixel data Cu is referred to instead of Bu.

A total of 10 bits of 8 bits from the peripheral pixel detection circuit 24 and the code DTu (target pixel data Yu) are supplied to the memory 25 as an address. These 10 bits indicate a local pattern of a block size, and a 2-bit correction code CR is read from the memory 25. The code DTu and the correction code CR are supplied to the synthesizing circuit 26, and the synthesizing circuit 26 forms a 4-bit code signal using the code DTu as upper bits and the correction code CR as lower bits.

The 4-bit code signal from the synthesizing circuit 26 is
Supplied to The dynamic range DR from the frame decomposition circuit 23 is supplied to the decoding circuit 27, and ADRC is decoded. The output signal of the decoding circuit 27 and the minimum value MIN from the frame decomposition circuit 23 are supplied to the addition circuit 28, and the addition circuit 28 obtains 8-bit restored data. The restored data is supplied to the block decomposing circuit 29, and the order of the blocks is returned to the order of scanning. The restored data is obtained at the output terminal 30 of the block decomposition circuit 29.

FIG. 5 shows an example of the correction code generation circuit 11 provided on the transmission side. The upper two bits DTu of the quantization code DT from the separation circuit 9 are supplied to the peripheral pixel detection circuit 41 and the selector 42, and the lower two bits DTu are supplied to the selector 42. By the peripheral pixel detection circuit 41, the target pixel data Yu (DT
Four codes Au, Bu, Cu, and Du (see FIG. 4) around u) are extracted, and these codes are supplied to the selector 42. The selector 42 selectively supplies one of the (2 bits × 6 = 12 bits) code and the 12-bit address formed by the read address generation circuit 43 to the memory 45.

The data read from the memory 45 is stored in the register 47 by the switch circuit 46 (the state in which the switch circuit 46 selects the output terminal a) or the maximum value detection circuit 50 (the state in which the switch circuit 46 selects the output terminal b). ). The output of the register 47 and +1 from the data generating circuit 49 are added by the adding circuit 48. Output data of the adding circuit 48 is supplied to the memory 45 as input data.

The read address generated by the read address generation circuit 43 is supplied to the detection circuit 51 and the selector 52. Detection circuit 51
Detects that the upper 10 bits of the 12-bit address have changed, and the output signal of the detection circuit 51 resets the maximum value detection circuit 50. The selector 52 selects a read address corresponding to the maximum value detected by the maximum value detection circuit 50. The correction code CR is obtained at the output of the selector 52. In order to reduce the transmission data, the selector 52 sets the lower 2 bits instead of all 12 bits of the read address to the correction code CR.
Select as

FIG. 6 shows an example of data stored in the memory 45. Attention pixel data Yu and peripheral pixel data Au, Bu, Cu,
The 10 bits with Du are the higher order of the address of the memory 45,
Two bits (00, 01, 10 or 11) corresponding to Yl (correction code CR) are set to the lower side of the address.

In order to form the correction code CR, when each of the quantization codes of one frame is initially set as a target pixel, each of the lower two bits Yl of the target pixel data (00) (01) (10) (11) The frequency of occurrence is examined. Therefore, in the initial state of one frame, the data in the memory 45 is all cleared to 0, the switch circuit 46 selects the output terminal a, the value of the read data of the memory 45 is incremented by 1, and Written to the same address. For example, when Yu, Au, Bu, Cu, and Du are all (00) and Yl is (01), the data at the address (000000000001) in the memory 45 is read, and the read data is incremented by one. Written to the above address. This process is performed with all the pixels in one frame as target pixels. As a result, as shown in FIG. 6, a distribution table of the frequency of occurrence of the lower 2 bits Yl for each of the patterns determined by the upper 10 bits of the address (2 ¹⁰ = 1024) is formed in the memory 45.

Next, the switch circuit 46 is set to select the output terminal b, the frequency data stored in the memory 45 is sequentially read, and the frequency data is supplied to the maximum value detection circuit 50. The maximum value detection circuit 50 detects a 2-bit code having the maximum frequency in each of the upper 10 bits of the address. For example, if the upper 10 bits of the address are (0000000000),
The address of the lower 2 bits corresponding to the largest one among the frequencies n1, n2, n3, n4 is detected. Based on the detection signal of the maximum value detection circuit 50, the selector 52 selects the address of the lower 2 bits having the highest frequency as the correction code CR. Therefore,
The correction code CR is the lower 2 that has the highest frequency in each pattern.
Means a bit.

As described above, the correction code CR is stored in the memory 25 on the receiving side.
(See FIG. 3). Since the 8-bit output signal from the peripheral pixel detection circuit 24 and the upper two bits of the code of the pixel of interest are supplied as an address to the memory 25, the optimum correction code CR according to the pattern is read. Since this correction code CR is combined with the received upper two bits, a 4-bit code very similar to the original data can be restored. Since this code is restored, a restored image of good image quality is obtained.

Unlike the above-described embodiment, a simple method of obtaining an optimum lower-order 2-bit correction code in advance from a plurality of images of a representative pattern and storing the correction code in a memory on the receiving side may be used. good.

For pattern classification, the accuracy may be further improved by adding information of the dynamic range DR of the block, for example, the upper 4 bits of the dynamic range DR to the code of the peripheral pixel.

Further, the present invention can be applied to block coding in which the average value of the upper bits and the average value of the lower bits are transmitted for each block, and the average value and the standard deviation are transmitted for each block.

〔The invention's effect〕

According to the present invention, even if the number of bits of each pixel to be transmitted is small, the number of bits is increased in accordance with the pattern on the decoding side, so that a restored image of good image quality can be obtained. Can be compressed.

[Brief description of the drawings]

FIG. 1 is a block diagram of a transmitting side according to an embodiment of the present invention, FIG. 2 is a schematic diagram showing an example of a block, FIG. 3 is a block diagram of a receiving side according to an embodiment of the present invention, and FIG. FIG. 5 is a schematic diagram showing an arrangement of a pixel of interest and peripheral pixels, and FIGS. 5 and 6 are a block diagram of a correction code generation circuit and schematic diagrams for explanation thereof. Explanation of main symbols in the drawings 1: input terminal of digital image data, 3: maximum and minimum value detection circuit, 8: quantization circuit, 9: separation circuit for separating upper and lower bits, 11: correction code generation Circuit, 24: peripheral pixel detection circuit, 25: memory, 26: combining circuit for combining upper bits and lower bits, 27: decoding circuit.

Claims (1)

(57) [Claims] 1. A decoding device for converting received transmission data having a first number of bits into pixel data having a second number of bits which is a number of bits greater than the first number of bits, the decoding apparatus comprising: Means for extracting a peripheral pixel based on the transmission data; means for forming a bit pattern from the transmission data of the pixel of interest and the transmission data of the extracted plurality of peripheral pixels; and Memory means for generating a correction code; and means for forming composite data using the transmission data of the pixel of interest as upper bits and the correction code as lower bits, and corresponding to the bit pattern of the memory means. A decoding device characterized by storing, at each address, one of a plurality of correction codes having a maximum occurrence frequency in a predetermined period.