JP2830841B2 - Surface emitting element mounting method and surface emitting element mounting board - Google Patents
Surface emitting element mounting method and surface emitting element mounting boardInfo
- Publication number
- JP2830841B2 JP2830841B2 JP8141654A JP14165496A JP2830841B2 JP 2830841 B2 JP2830841 B2 JP 2830841B2 JP 8141654 A JP8141654 A JP 8141654A JP 14165496 A JP14165496 A JP 14165496A JP 2830841 B2 JP2830841 B2 JP 2830841B2
- Authority
- JP
- Japan
- Prior art keywords
- emitting element
- light emitting
- surface light
- substrate
- bonding
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Classifications
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/30—Assembling printed circuits with electric components, e.g. with resistors
- H05K3/32—Assembling printed circuits with electric components, e.g. with resistors electrically connecting electric components or wires to printed circuits
- H05K3/34—Assembling printed circuits with electric components, e.g. with resistors electrically connecting electric components or wires to printed circuits by soldering
- H05K3/341—Surface mounted components
- H05K3/3431—Leadless components
Landscapes
- Semiconductor Lasers (AREA)
- Electric Connection Of Electric Components To Printed Circuits (AREA)
Description
【0001】[0001]
【発明の属する技術分野】本発明は面発光素子の実装方
法と面発光素子実装基板に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for mounting a surface light emitting element and a surface light emitting element mounting board.
【0002】[0002]
【従来の技術】光のもつ並列性、および空間伝播性をボ
ード間のデータリンク、情報処理などに応用するために
は、面方向に発光素子を二次元的に集積化することが望
まれる。面発光素子はこうした要請を満たすことが可能
であり、並列情報処理容量の増大が期待できる。また、
面発光素子の形成には劈開工程が不要であることや、ウ
エーハの状態で特性テストが可能であることなどから端
面型発光素子に比ベて量産に向くため、低コストな光源
として産業利用面でも有利となる。2. Description of the Related Art In order to apply the parallelism and spatial propagation properties of light to data links between boards, information processing, and the like, it is desired to integrate light emitting elements two-dimensionally in a plane direction. The surface emitting element can satisfy such a demand, and an increase in parallel information processing capacity can be expected. Also,
Since a cleavage process is not required for the formation of a surface-emitting device and a characteristic test can be performed in the state of a wafer, it is suitable for mass production compared to an edge-emitting device. But it is advantageous.
【0003】こうした面型半導体素子については、伊賀
らによって先駆的な研究が行われ、彼等の一連の研究成
果は1988年発行の伊賀他著のジャーナル・オブ・カ
ンタム・エレクトロニクス(Journal of Q
uantnm Electronics)第24巻18
45〜1855ページ記載の論文に歴史的な経緯を含め
てまとめられている。[0003] Pioneering research has been carried out by Iga et al. On such planar semiconductor devices, and a series of their research results has been published in 1988 by Iga et al., Journal of Quantum Electronics.
antnm Electronics) Vol. 24, No. 18
The papers on pages 45 to 1855 are summarized, including their historical background.
【0004】上記面発光素子を実際のシステムなどに組
み入れる際には、何らかの形で面発光素子を配線基板上
に実装し、駆動回路などと併せて用いる必要がある。面
発光素子を配線基板に実装する方法としては、これまで
駆動回路などが形成される基板上に直接面発光素子も形
成してしまう方法と、駆動回路などと面発光素子とを別
々に作製し、ハイブリッドに実装する方法とが提案され
てきた。When incorporating the above-mentioned surface light emitting device into an actual system or the like, it is necessary to mount the surface light emitting device on a wiring board in some form and use it together with a drive circuit. As a method of mounting a surface emitting element on a wiring board, a method in which a surface emitting element is also directly formed on a substrate on which a driving circuit or the like is formed, or a method in which a driving circuit or the like and a surface emitting element are separately manufactured. , And a method of implementing it in a hybrid.
【0005】図3は従来例の面発光素子が駆動回路など
と同一の基板上に形成された面発光素子実装基板の模式
的断面図であり、図中符号30は電子回路、31は基
板、32は面発光素子である。前者の例としては、図3
に示すようなSi基板31上に面発光レーザである面発
光素子32を結晶成長させて作製し、Si基板31をプ
ロセスしてCMOSなどの駆動回路である電子回路30
を形成するものがある。この方法はモノリシックにレー
ザ、回路類を形成してしまうため両者の間のアライメン
トが不要となる。FIG. 3 is a schematic cross-sectional view of a conventional surface light emitting device mounting substrate in which a surface light emitting device is formed on the same substrate as a drive circuit and the like. In the figure, reference numeral 30 denotes an electronic circuit, 31 denotes a substrate, 32 is a surface light emitting element. As an example of the former, FIG.
A surface emitting device 32, which is a surface emitting laser, is formed by crystal growth on a Si substrate 31 as shown in FIG.
There is something that forms. In this method, lasers and circuits are formed monolithically, so that alignment between them is not required.
【0006】図4は従来例の面発光素子を形成した基板
と配線基板とをはんだで接合した面発光素子実装基板の
模式的断面図であり、符号41は基板、42は面発光素
子、47はp型電極パッド、51は配線基板、52はは
んだバンプである。後者の例としては、図4に示すよう
な配線基板51にそれぞれが面発光レーザである面発光
素子42の位置に対応したはんだバンプ52を形成して
おき、面発光素子42の位置に金メッキしたp型電極パ
ッド47を形成した面発光レーザアレイ基板41を配線
基板51上に大まかに位置決めてしておいてリフローす
ると、溶融したはんだバンプ52に引っ張られて面発光
素子42のp型電極パッド47とはんだバンプ52とが
セルフアライメントするものがある。アライメントは始
めに大まかに行うだけなので、サブミクロンのような高
い精度は要求されず、コストに与える影響は少ない。FIG. 4 is a schematic cross-sectional view of a conventional surface light emitting element mounting board in which a substrate on which a surface light emitting element is formed and a wiring board are joined by soldering. Is a p-type electrode pad, 51 is a wiring board, and 52 is a solder bump. As an example of the latter, solder bumps 52 corresponding to the positions of the surface emitting elements 42, each of which is a surface emitting laser, are formed on a wiring board 51 as shown in FIG. When the surface emitting laser array substrate 41 on which the p-type electrode pads 47 are formed is roughly positioned on the wiring substrate 51 and reflowed, the p-type electrode pads 47 of the surface emitting element 42 are pulled by the molten solder bumps 52. And the solder bumps 52 are self-aligned. Since alignment is only performed roughly at the beginning, high accuracy such as submicron is not required, and the influence on cost is small.
【0007】[0007]
【発明が解決しようとする課題】しかしながら上述の従
来の実施例においては、いくつかの問題点が指摘され
る。まず最初の従来の実施例では、面発光レーザの材料
系が主にGaAs系で、基板となるSiとは格子定数が
不整合であるため、その結晶成長が技術的にかなり困難
になる。格子の不整合は欠陥を生じさせるため、この欠
陥がレーザの寿命を著しく低下させることになるし、レ
ーザの特性そのものも実用レベルには至っていない。レ
ーザの寿命は事業化の上で極めて重要なファクターであ
り、長期間の使用に耐え得るものを保証しなければなら
ないので上記の難点は致命的なものとなる。However, several problems are pointed out in the above-mentioned conventional embodiment. First, in the first conventional example, since the material system of the surface emitting laser is mainly a GaAs system and the lattice constant is inconsistent with that of Si as a substrate, crystal growth thereof becomes technically very difficult. Since the lattice mismatch causes defects, the defects significantly reduce the life of the laser, and the characteristics of the laser itself have not reached a practical level. The life of a laser is a very important factor in commercialization, and the above-mentioned difficulties are fatal since it is necessary to ensure that the laser can be used for a long time.
【0008】また、第二の従来の実施例でも、面発光素
子の電極として用いている金パッドと配線基板側のはん
だバンプおよび配線用基板との熱膨張係数が大きく異な
るため、リフローの際の温度上昇により両者の間の熱膨
張差による歪みが面発光素子にかかることになり、素子
特性、あるいは素子の寿命の低下を招いていた。また、
はんだバンプの代わりに金スズを用いた場合には、熱膨
張係数の差はわずかで歪みによる影響は回避できる可能
性があるが、依然として配線用基板との熱膨張係数との
差は残るし、リフロー時の温度上昇がはんだバンプの時
の200℃に対し、300℃とかなり高温になるため、
熱による素子劣化が起きるという問題点がある。こうし
た素子の寿命、特性を保証できなければ安定した光源と
しての役割を担っていくことは難しく、これらを安定し
て供給できる面発光素子の実装方法と面発光素子実装基
板が広く望まれていた。Also, in the second conventional example, since the thermal expansion coefficients of the gold pad used as the electrode of the surface light emitting element and the solder bumps on the wiring board side and the wiring board are greatly different, the reflow is difficult. Due to the rise in temperature, distortion due to a difference in thermal expansion between the two is applied to the surface light emitting element, resulting in a decrease in element characteristics or life of the element. Also,
When using gold tin instead of solder bumps, the difference in thermal expansion coefficient may be small and the effect of distortion may be avoided, but the difference from the thermal expansion coefficient with the wiring substrate still remains, Since the temperature rise during reflow is considerably high at 300 ° C, compared to 200 ° C for solder bumps,
There is a problem that the element is deteriorated by heat. If the life and characteristics of such devices cannot be guaranteed, it is difficult to play a role as a stable light source, and a surface emitting device mounting method and a surface light emitting device mounting substrate capable of stably supplying them have been widely desired. .
【0009】本発明の目的は、少ないコストの増加で特
性が安定し寿命の長い面発光素子の実装方法と、面発光
素子実装基板を提供することにある。SUMMARY OF THE INVENTION An object of the present invention is to provide a method for mounting a surface light emitting element having stable characteristics and a long life with a small increase in cost, and a surface light emitting element mounting substrate.
【0010】[0010]
【課題を解決するための手段】本発明の面発光素子の実
装方法は、複数の面発光素子を配線基板に実装する工程
において、面発光素子の形成された基板に設けられた面
発光素子の電極パッドに隣接して、該電極パッドと電気
的に接続する接合用パッドを形成し、配線基板上の接合
用パッドと対応する位置に設けられたはんだバンプと、
接合用パッドとをリフローにより接合させることによ
り、面発光素子が配線用基板に実装される。According to a method of mounting a surface light emitting element of the present invention, in a step of mounting a plurality of surface light emitting elements on a wiring board, the method for mounting the surface light emitting element provided on the substrate on which the surface light emitting element is formed is provided. Forming a bonding pad electrically connected to the electrode pad adjacent to the electrode pad, a solder bump provided at a position corresponding to the bonding pad on the wiring board;
The surface emitting element is mounted on the wiring substrate by bonding the bonding pad and the bonding pad by reflow .
【0011】また、面発光素子の形成された基板の電極
パッドの設けられた面上に、接合用パッド上面を除いて
誘電体膜が形成されていることが好ましい。 Further, on provided with the electrode pads of the substrate which is formed of the surface-emitting device surface, it is not preferable that the dielectric film except the bonding pad upper surface is formed.
【0012】本発明の面発光素子実装基板は、複数の面
発光素子が形成され、面発光素子の電極パッドと該電極
パッドと隣接し該電極パッドと電気的に接続する接合用
パッドとが同一面に設けられた基板と、接合用パッドと
対応する位置に基板に形成された電子回路のパッドと接
続するはんだバンプが配設された配線用基板とを備え、
接合用パッドとはんだバンプとがリフローにより接合さ
れている。In the surface light emitting element mounting substrate of the present invention, a plurality of surface light emitting elements are formed, and an electrode pad of the surface light emitting element and a bonding pad adjacent to the electrode pad and electrically connected to the electrode pad are the same. A substrate provided on the surface, and a wiring substrate provided with solder bumps connected to pads of an electronic circuit formed on the substrate at positions corresponding to the bonding pads,
The bonding pad and the solder bump are bonded by reflow .
【0013】本発明によれば、面発光素子の電極パッド
とはんだバンプとの接合用パッドとを各々独立して設け
るため、面発光素子のある電極パッドの位置と、配線基
板側にあるはんだバンプの位置とが異なり、熱膨張係数
差による歪みを面発光素子が直接受けることはなく、歪
みによる悪影響を回避することができる。According to the present invention, since the electrode pad of the surface light emitting element and the bonding pad for the solder bump are provided independently of each other, the position of the electrode pad with the surface light emitting element and the solder bump on the wiring board side are provided. Unlike the position, the surface light emitting element is not directly subjected to the distortion due to the difference in thermal expansion coefficient, and the adverse effect due to the distortion can be avoided.
【0014】また、面発光素子のパッドはヒートシンク
および熱の逃げ道としてのみ機能することができるし、
その回りをはんだバンプが流れてしまうのを防ぐ目的を
かねて誘電体膜で覆ってしまうことにより、その誘電体
膜がパッド自体のパッシベーション膜としての役割も受
け持つことが可能となる。Further, the pad of the surface emitting element can function only as a heat sink and a heat escape path.
By covering with a dielectric film for the purpose of preventing the solder bumps from flowing around the dielectric film, the dielectric film can also serve as a passivation film of the pad itself.
【0015】[0015]
【発明の実施の形態】次に本発明の実施の形態について
図面を参照しながら詳細に説明する。図1は本発明の一
実施の形態の面発光素子が形成された基板の模式的断面
図であり、図2は面発光素子が形成された基板と配線基
板との接合の工程を説明するための模式的断面図であ
り、(a)は両基板を対向させた状態、(b)は両基板
の位置合わせの状態、(c)ははんだバンプをリフロー
させた状態を示す。図中符号10はレーザ光、11は基
板、12は面発光素子、13は活性層、14はn型DB
R、15はp型DBR、16はn型電極、17はp型電
極パッド、18は接合用パッド、19は誘電体膜、21
は配線基板、22ははんだバンプである。Embodiments of the present invention will now be described in detail with reference to the drawings. FIG. 1 is a schematic cross-sectional view of a substrate on which a surface light emitting element according to an embodiment of the present invention is formed, and FIG. 2 is a view for explaining a bonding step between a substrate on which the surface light emitting element is formed and a wiring substrate. 3A is a schematic cross-sectional view, FIG. 3A shows a state in which both substrates are opposed, FIG. 3B shows a state in which both substrates are aligned, and FIG. 3C shows a state in which solder bumps are reflowed. In the figure, reference numeral 10 denotes a laser beam, 11 denotes a substrate, 12 denotes a surface emitting element, 13 denotes an active layer, and 14 denotes an n-type DB.
R and 15 are p-type DBRs, 16 is an n-type electrode, 17 is a p-type electrode pad, 18 is a bonding pad, 19 is a dielectric film, 21
Is a wiring board, and 22 is a solder bump.
【0016】面発光アレイ素子が二次元的に並ぶ基板1
1側の面発光素子12は図1に示されるような構造であ
り、活性層13がn型DBR14およびp型DBR15
で挟まれて共振器を形成している。DBR(多層膜反射
鏡、DistributedBragg Reflec
tor)は例えばAlAsとGaAsのλ/4厚で交互
に15〜20周期程度積層したものである。各面発光素
子はプロトン注入などで形成された高抵抗領域により電
気的に分離されており、n型電極16にも表面からエッ
チングし、金メッキすることで、p型電極パッド17と
ともに表面に電極パッドとして形成されている。電極パ
ッド17を金メッキ工程にて形成する際に、同時にその
隣に配線基板21側のはんだバンプ22と接合するため
の接合用パッド18を形成する。電極パッド17は例え
ば30ミクロン角、接合用パッド18は例えば50ミク
ロン角の大きさがあれば、p型電極パッド17はヒート
シンクの機能を果たすのに十分であり、接合用パッド1
8ははんだバンプ22とセルフアラインするのに十分な
大きさである。メッキ厚は3ミクロンから10ミクロン
でよい。p型電極パッド17および接合用パッド18を
形成後、p型電極パッド17のバッシベーシヨンおよび
接合用パッド18とはんだバンプ22との接合時のはん
だの流れ込み防止を兼ねてまず基板11の面発光素子側
全面にSiO2 などの誘電体膜19を熱CVD装置など
で蒸着する。その後、接合用パッド18の部分のみバフ
ァードフッ酸で除去する。他方、配線基板21の方で
は、図2(a)に示すように基板111側の接合用パッ
ド18の位置に合わせて、はんだバンプ22を形成す
る。はんだバンプ22の大きさは面発光素子12の素子
間ピッチが250ミクロンであれば、直径50ミクロン
あればよい。小さすぎるとセルフアラインしないし、大
きすぎると隣同士で短絡してしまう可能性がでてくる。
配線基板側には面発光素子駆動に必要な種々の回路類が
配置されている。例えば駆動回路であるとか、システム
にもよるが面発光素子選択回路などが挙げられる。こう
して得られた基板11と配線基板21とを赤外線顕微鏡
の下で図2(b)に示すように接合用パッド18がほぼ
はんだバンプ22の上に来るように配置する。その後、
両者を200℃の温度でリフローすると、図2(c)に
示すようにはんだバンプ22の張力に引き込まれて接合
用パッド18とはんだバンプ22とがセルフアラインし
て接合する。この際、フラックスをはんだバンプ22に
塗布しておくと、接合が滑らかに行える。あるいは完全
に酸素を遮断した雰囲気中で接合を行なってもよい。そ
して温度上昇後、約30秒経ったら温度を降下させ室温
に戻す。接合後は可能ならアセトンなどの有機溶剤にて
フラックスを洗い流す。Substrate 1 on which surface emitting array elements are two-dimensionally arranged
The surface light emitting element 12 on one side has a structure as shown in FIG. 1, and the active layer 13 is formed of an n-type DBR 14 and a p-type DBR 15
To form a resonator. DBR (Multilayer Reflector, Distributed Bragg Reflect)
(tor) is, for example, about 15 to 20 cycles of AlAs and GaAs alternately laminated with a thickness of λ / 4. Each surface light emitting element is electrically separated by a high resistance region formed by proton injection or the like. The n-type electrode 16 is etched from the surface and plated with gold to form an electrode pad on the surface together with the p-type electrode pad 17. It is formed as. When the electrode pad 17 is formed in the gold plating process, a bonding pad 18 for bonding to the solder bump 22 on the wiring board 21 side is formed at the same time. If the electrode pad 17 has a size of, for example, 30 μm square and the bonding pad 18 has a size of, for example, 50 μm square, the p-type electrode pad 17 is sufficient to perform the function of the heat sink, and the bonding pad 1
Numeral 8 is large enough to be self-aligned with the solder bump 22. The plating thickness can be from 3 microns to 10 microns. After forming the p-type electrode pad 17 and the bonding pad 18, first, the surface of the surface light-emitting element side of the substrate 11 is used to prevent the inflow of solder when the p-type electrode pad 17 is bonded and the bonding pad 18 and the solder bump 22 are bonded. A dielectric film 19 such as SiO 2 is deposited on the entire surface by a thermal CVD device or the like. Thereafter, only the portion of the bonding pad 18 is removed with buffered hydrofluoric acid. On the other hand, on the wiring board 21, the solder bumps 22 are formed in accordance with the positions of the bonding pads 18 on the board 111, as shown in FIG. The size of the solder bump 22 may be 50 microns if the pitch between the surface light emitting elements 12 is 250 microns. If it is too small, self-alignment will not be performed, and if it is too large, there is a possibility that adjacent circuits will be short-circuited.
Various circuits necessary for driving the surface emitting element are arranged on the wiring board side. For example, a driving circuit or a surface light emitting element selection circuit depending on the system may be used. The substrate 11 and the wiring board 21 thus obtained are arranged under an infrared microscope such that the bonding pads 18 are almost over the solder bumps 22 as shown in FIG. afterwards,
When both of them are reflowed at a temperature of 200 ° C., as shown in FIG. 2C, the tension is applied to the solder bumps 22 and the bonding pads 18 and the solder bumps 22 are self-aligned and bonded. At this time, if the flux is applied to the solder bumps 22, the bonding can be performed smoothly. Alternatively, the bonding may be performed in an atmosphere in which oxygen is completely blocked. After about 30 seconds from the temperature rise, the temperature is lowered and returned to room temperature. After bonding, if possible, wash away the flux with an organic solvent such as acetone.
【0017】以上の工程にて面発光素子の劣化の起きな
い実装が行える。アライメント精度も高精度なものは不
要であるのでコストには殆ど響かないし、面発光素子作
製の上での工程も誘電体蒸着と―部剥離という精度のい
らない工程が増えるだけなので、コストに大きく影響し
ない。Through the above steps, mounting without deterioration of the surface emitting element can be performed. High alignment accuracy is not required, so there is almost no effect on the cost. Also, in the process of fabricating the surface emitting element, the number of processes that do not require precision, such as dielectric deposition and-part separation, only increases, which greatly affects the cost. do not do.
【0018】以上の本発明の実施の形態で述ベた面発光
素子の構成は必ずしも、本例に従う必要はなく、任意に
選ぶことが可能である。また、各構成物のスケールも適
宜変更が可能である。リフローの温度もはんだバンプの
合金構成により異なってくる。The configuration of the surface emitting element described in the above embodiment of the present invention does not necessarily have to be in accordance with the present embodiment, but can be arbitrarily selected. Further, the scale of each component can be appropriately changed. The reflow temperature also depends on the alloy composition of the solder bump.
【0019】[0019]
【発明の効果】以上に説明したように、本発明によれば
面発光素子モジュール作製コストをほとんど変更せず
に、簡単な手法により、面発光素子の特性・寿命を安定
して供給できる面発光素子の実装方法を提供できる。As described above, according to the present invention, the surface light emitting device can stably supply the characteristics and the life of the surface light emitting device by a simple method without substantially changing the manufacturing cost of the surface light emitting device module. An element mounting method can be provided.
【図1】本発明の一実施の形態の面発光素子が形成され
た基板の模式的断面図である。FIG. 1 is a schematic cross-sectional view of a substrate on which a surface-emitting element according to an embodiment of the present invention is formed.
【図2】面発光素子が形成された基板と配線基板との接
合の工程を説明するための模式的断面図である。(a)
は両基板を対向させた状態を示す。(b)は両基板の位
置合わせの状態を示す。(c)ははんだバンプをリフロ
ーさせた状態を示す。FIG. 2 is a schematic cross-sectional view illustrating a step of joining a substrate on which a surface light emitting element is formed and a wiring substrate. (A)
Indicates a state in which both substrates are opposed to each other. (B) shows the state of alignment of both substrates. (C) shows a state where the solder bumps are reflowed.
【図3】従来例の面発光素子が駆動回路などと同一の基
板上に形成された面発光素子実装基板の模式的断面図で
ある。FIG. 3 is a schematic cross-sectional view of a surface emitting element mounting substrate in which a conventional surface emitting element is formed on the same substrate as a drive circuit and the like.
【図4】従来例の面発光素子を形成した基板と配線基板
とをはんだで接合した面発光素子実装基板の模式的断面
図である。FIG. 4 is a schematic cross-sectional view of a conventional surface light emitting element mounting substrate in which a substrate on which a surface light emitting element is formed and a wiring board are joined by soldering.
10 レーザ光 11、31、41 基板 12、32、42 面発光素子 13 活性層 14 n型DBR 15 p型DBR 16 n型電極 17、47 p型電極パッド 18 接合用パッド 19 誘電体膜 21、51 配線基板 22、52 はんだバンプ 30 電子回路 Reference Signs List 10 laser beam 11, 31, 41 substrate 12, 32, 42 surface emitting element 13 active layer 14 n-type DBR 15 p-type DBR 16 n-type electrode 17, 47 p-type electrode pad 18 bonding pad 19 dielectric film 21, 51 Wiring board 22, 52 Solder bump 30 Electronic circuit
Claims (3)
工程において、 前記面発光素子の形成された基板に設けられた前記面発
光素子の電極パッドに隣接して、該電極パッドと電気的
に接続する接合用パッドを形成し、 前記配線基板上の前記接合用パッドと対応する位置に設
けられたはんだバンプと、前記接合用パッドとをリフロ
ーにより接合させることにより、前記面発光素子が前記
配線用基板に実装されることを特徴とする面発光素子の
実装方法。1. A step of mounting a plurality of surface light emitting elements on a wiring board, wherein the plurality of surface light emitting elements are electrically connected to and adjacent to the electrode pads of the surface light emitting elements provided on the substrate on which the surface light emitting elements are formed. Forming a bonding pad to be connected to the wiring board, and reflowing the solder pad provided at a position corresponding to the bonding pad on the wiring board and the bonding pad.
A method for mounting a surface light emitting element, wherein the surface light emitting element is mounted on the wiring substrate by bonding with each other.
極パッドの設けられた面上に、前記接合用パッド上面を
除いて誘電体膜が形成されている、請求項1に記載の面
発光素子の実装方法。2. The surface according to claim 1, wherein a dielectric film is formed on a surface of the substrate on which the surface light emitting element is formed, on a surface on which the electrode pads are provided, except for an upper surface of the bonding pad. Light emitting element mounting method.
素子の電極パッドと該電極パッドと隣接し該電極パッド
と電気的に接続する接合用パッドとが同一面に設けられ
た基板と、 前記接合用パッドと対応する位置に、基板に形成された
電子回路のパッドと接続するはんだバンプが配設された
配線用基板とを備え、 前記接合用パッドと前記はんだバンプとがリフローによ
り接合されていることを特徴とする面発光素子実装基
板。3. A substrate on which a plurality of surface light emitting elements are formed, and an electrode pad of the surface light emitting element and a bonding pad adjacent to the electrode pad and electrically connected to the electrode pad are provided on the same surface. A wiring board provided with solder bumps connected to pads of an electronic circuit formed on the board at positions corresponding to the bonding pads, wherein the bonding pads and the solder bumps are reflowed;
Surface light-emitting element mounting substrate, characterized by being joined Ri.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP8141654A JP2830841B2 (en) | 1996-06-04 | 1996-06-04 | Surface emitting element mounting method and surface emitting element mounting board |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP8141654A JP2830841B2 (en) | 1996-06-04 | 1996-06-04 | Surface emitting element mounting method and surface emitting element mounting board |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH09326532A JPH09326532A (en) | 1997-12-16 |
| JP2830841B2 true JP2830841B2 (en) | 1998-12-02 |
Family
ID=15297078
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP8141654A Expired - Fee Related JP2830841B2 (en) | 1996-06-04 | 1996-06-04 | Surface emitting element mounting method and surface emitting element mounting board |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2830841B2 (en) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| DE102022114856A1 (en) * | 2022-06-13 | 2023-12-14 | Trumpf Photonic Components Gmbh | VCSEL for emitting laser light |
-
1996
- 1996-06-04 JP JP8141654A patent/JP2830841B2/en not_active Expired - Fee Related
Also Published As
| Publication number | Publication date |
|---|---|
| JPH09326532A (en) | 1997-12-16 |
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