JP2832072B2 - Image coding method and apparatus - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an image encoding method and apparatus for encoding image data.

[Conventional technology]

2. Description of the Related Art A facsimile apparatus, which is a typical example of a conventional still image communication apparatus, employs a method of sequentially scanning an image sequentially in a raster direction, and encoding and transmitting the image. In this method, it is necessary to transmit the coded data of all the images in order to grasp the entire image of the images, so that the transmission time is long and it is difficult to adapt to image communication services such as image database services and video tex. Was.

Therefore, hierarchical coding has been considered in order to quickly grasp the entire image. FIG. 22 shows a conventional hierarchical coding example.

101 to 104 are frame memories for storing reduced images of 1, 1/2, 1/4, and 1/8, respectively, and 105 to 107 are 1/100, respectively.
Reduction units for generating 2, 1/4, and 1/8 reduced images, and 108 to 111 are encoders for encoding 1/8, 1/4, 1/2, and 1 reduced images, respectively.

The reduction unit 105 performs main scanning on the image from the frame memory 101,
The image is reduced by a technique such as sub-sampling in both the sub-scanning directions to 1/2 to generate an image of 画像 size and stored in the frame memory 102. Further, the half-size image is reduced by the reduction unit 106 to create a quarter-size image, and the frame memory 103
Similarly, a 1/8 size low-resolution image is created by the reduction unit 107 and stored in the frame memory 104.

Then, by transmitting codes sequentially from low resolution ones, a rough overall image can be quickly grasped. In the example of FIG. 22, the image is 1 /
In this example, the image data is reduced to 2, 1/4, and 1/8, the encoding is performed in the order of 1/8, 1/4, 1/2, and 1 (actual size image), and the data is transmitted in this order. 1/8
To encode an image, the 1/8 image stored in the frame memory 104 is sequentially scanned, and entropy coding such as arithmetic coding is performed with reference to a target pixel to be encoded by the encoder 108 and surrounding pixels. For the / 4 image, encoding is performed by the encoder 109 by referring to the surrounding pixels of the target pixel from the frame memory 103 and the surrounding pixels of the / 8 image from the frame memory 104 to increase the encoding efficiency. I have. Similarly, the encoder 110 and 111 respectively encode the 1/2 image of the frame memory 102 by referring to the 1/4 image of the frame memory 103 and the original image of the frame memory 101 by referring to the 1/2 image of the frame memory 102. I do.

In such a hierarchical coding method, various reduction methods are employed in order to maintain information of a low-resolution image. For example, a method of applying a low-pass filter and then performing re-binarized sub-sampling or a method of providing an exceptional process to the filter operation to prevent a specific image from disappearing has been considered.

[Problems to be solved by the invention]

In the hierarchical coding method, the entire image can be transmitted at an early stage by sequentially transmitting the code of the reduced image in the order of the lower resolution as described above.

However, in this method, reduction is repeated several times in order to save image information of a low-resolution image. Since the order of encoding and transmission is the reverse of the reduction process, images of all layers including the original image must be stored in the memory. As a result, not only is the apparatus large, but also the processing is complicated.

Also, the hierarchical coding method is not suitable for a method of sequentially transmitting an image such as a facsimile by sequentially coding.

This is because, in normal facsimile communication, paper is used as a recording medium, so that a low-resolution image at an intermediate stage is not required at all. In addition, many terminals are inexpensive and popular, and hierarchical coding that requires a frame memory is not suitable for facsimile communication.

On the other hand, when hierarchical coding is applied to an image database or the like, the lowest resolution image may be used as an icon and used for database search. In this case, a hierarchical image other than the original image is often used only as an intermediate medium for sequentially decoding the image and obtaining the original image. Therefore, there is a disadvantage that unnecessary images must be stored in a database, and that a decoding time becomes long.

[Means (and action) for solving the problem]

The present invention has been made in view of the above points, and includes an inputting step of inputting original image data representing an original image, a first storing step of storing the input original image data in a memory, and an original reading out of the memory. A reduction step of forming reduced image data representing a reduced image of a desired size by performing a plurality of reduction processes on image data; a second storage step of storing the formed reduced image data in a memory;
An encoding step of encoding the reduced image data and the original image data stored in the memory; and input means for inputting the original image data representing the original image. First storage means for storing original image data input from the input means, and a reduced image representing a reduced image of a desired size by performing a plurality of reduction processes on the original image data read from the first storage means Reduction means for forming data, second storage means for storing reduced image data formed by the reduction means, reduced image data stored in the second storage means and stored in the first storage means And an encoding means for encoding the original image data.

〔Example〕

Hereinafter, the present invention will be described with reference to the drawings and along preferred embodiments.

FIG. 1 is an example of a binary image encoding apparatus to which the present invention is applied. 1 is a frame memory FM for storing one screen of the original image
Reference numerals 1 and 2 denote image reduction units for generating reduced images.
In the present embodiment, in the image reduction unit 2, both the vertical and horizontal
Perform reduction. Reference numeral 3 denotes a frame memory FM2 for storing the generated reduced image. Reference numeral 4 denotes an encoding unit that encodes the image reduced by the image reduction unit 2 and the original image using an arithmetic code method and transmits the encoded image.

First, an image signal is stored in the frame memory 1 via a line 10 from an image input device (not shown). An image signal is output from the frame memory 1 to a line 11 for each raster. This signal is selected by the selector 5 and input to the image reduction unit 2 from the line 51. Here, the image is reduced in half in the vertical and horizontal directions.

The selector 5 selects whether to reduce the original image or to further reduce the reduced image stored in the frame memory 3. When the reduced image (1/2 or 1/4 image) is selected by the selector 5, the reduced image is output from the frame memory 3 to the line 31, and the selector 5 selects a signal.
The data is input to the reduction unit 2 via the line 51.

One image reduced by half in both the vertical and horizontal directions in the reduction unit 2 is stored in the frame memory 3 from the line 21. Original image
After the image reduced to 1/2 is stored in the frame memory 3 by the above-described process, the 1/2 reduced image is output from the frame memory 3 to the line 31 for each raster, and is output to the line 51 by the selector 5 through the line 51 in the same process. A / 4 reduced image is formed in the frame memory 3. Similarly, 1/8 image, 1/16
Image,… vertical and horizontal until the desired image size 1/2
The reduction is repeated.

Assuming the desired image size is 1/2 ⁿ , the final obtained
After the 1/2 ⁿ reduced image is stored in the temporary frame memory 3 as an icon image or a communication management image, the icon image is encoded by the encoding unit 4 from the line 13, and encoded data is transmitted through the line 16. Is output. This encoded data becomes an icon indicating the outline of the original image to be encoded next.

Next, the original image is sent from the frame memory 1 via the line 12,
Similarly, it is encoded by the encoding unit 4. In this method, since the icon image and the original image are sequentially and independently encoded, the decoding unit does not need a frame memory. Further, by decoding the icon image in the decoding unit, a rough outline of the image can be quickly grasped. After decoding the icon image, if the original image is unnecessary, the decoding can be stopped or the reception can be stopped at this stage.

FIG. 2 shows details of the reduction unit 2. Reference numerals 210, 211, and 212 denote line memories for storing pixels for one line, respectively, which are input to the filter unit 220 from lines 213, 214, and 215, respectively. Details of the filter unit 220 will be described below.

FIG. 3 shows coefficients of a 3 × 3 filter used in the filter unit 220. In this embodiment, a low-pass filter is used, the weight coefficient of the center pixel is set to C (C is 4 as a standard), and a grace coefficient as shown in the figure is given. Assuming that the density value of the center pixel is Di, j (i = 1 to M, j = 1 to N; MN is the horizontal and vertical image size), the output density W of the filter is W = (Di-1, j -1 + 2Di, j-1 + Di + 1, j-1 + 2Di-1, j + CDi, j2Di + 1, j + Di-1, j + 1 + 2Di, j + 1 + Di + 1, j +1) ... (1).

The output W221 of the filter unit 220 is compared with the threshold value T by the comparator 230.
(In this embodiment, binarization is performed using T = 8 as a standard). At this time Is binarized as follows. The binarized output is the selector 24
0 is selected, and both the vertical and horizontal directions are reduced to 1/2 by the sub-sampling unit 250.

FIG. 4 is an explanatory diagram of subsampling. Main scan,
By taking out every other pixel data indicated by diagonal lines in the sub-scanning direction in the sub-scanning direction, 1/2 size (1/4 in area)
Are formed. This can be easily realized by the latch timing of the pixel data. The output of the sub-sampling unit 250 is output to the frame memory 3 shown in FIG.

By the way, as described above, the peripheral pixel density is preserved by the low-pass filter (coefficient in FIG. 3) and reduced by サ ブ by sub-sampling, but a line of one pixel width disappears due to the phase of the sub-sampling position. There are cases. An example is shown in FIG. FIG. 5 shows that after applying a low-pass filter with c = 4 and T = 8 in the equations (1) and (2),
This is a result when subsampling is performed at the center of 3 × 3 pixels. (A) is a case where a single black vertical line does not pass through the center of 3 × 3 pixels, and the sub-sampling result is white and 1
This line disappears. Similarly, the slanted black line as in (b), the central white line in (c), etc. disappear. Therefore, it is necessary to store information such as lines regardless of the sub-sampling position.

Therefore, as shown in FIG. 2, an exception processing unit 260 is provided, and information such as a thin line edge and an isolated point is stored by performing an exception process separately from the reduction process by filtering and subsampling. FIG. 6 shows the configuration of the exception processing unit 260.

The exception processing unit 260 includes a statistic processing unit 600 and an exception pattern processing unit 610. Each signal line number is the same line as the same number in FIG. In the statistical processing unit 600, the distribution of black and white of the pixel around the target pixel to be reduced is checked,
The exception pattern select signal 601 is sent to the exception pattern processing unit 610.
To determine the exception pattern. FIG. 7 shows an example. The main scanning direction (horizontal direction) is i, the sub-scanning direction (vertical direction) is j, and the pixel of interest to be reduced is x.
(I, j).

x (i, j) is located at the same position as the median value (Di, j in equation (1)) of the pixel to be filtered by the low-pass filter 3 × 3. ) Is calculated. The nature of the image, for example, a character, a line drawing, a dither image, a positive (positive) image, a negative (negative) image, or the like is determined based on the statistics, and an appropriate exception pattern is selected. The determination of a positive image or a negative image is performed as follows.

Assuming that the sum of the densities of the 5 × 5 pixel area is S Can be expressed as (X (i, j) = 0 or 10 0: white pixel 1: black pixel) If STN (= 18), it is determined that the image is a negative image because there are many black pixels.

A dither image or another image expressed in halftone is determined as follows. That is, 5 × 5 pixels are vertically divided into five stripes each having five pixels each, and the inversion of black and white in each stripe is counted. Assuming that the sum of the count values is CN, in the case of CN16, since the number of inversions is large, it is determined that the image is a dither image or a halftone image. This black-and-white inversion number can be easily configured by a counter.

In the exceptional pattern processing unit 610, 3 × 3 pixels and subsampling 25 in the reduced image from the line memories 210 to 212 are used.
With reference to 0 and the three pixels already reduced from the line memory 270, if the result by the filter is not desirable,
An exception pattern signal 261 and an exception pattern selection signal 262 are output, and the selector 240 can output an exception pattern signal instead of a filter output.

FIG. 8 shows reference pixels in the exception pattern processing unit 610. (1) represents an image after reduction processing, (2) represents an image before reduction processing, e represents a pixel of interest of the image to be reduced, and a, b, c, d, f, g, h, and i represent surrounding pixels. In the reference pixels, these are the same as the pixels applied to the filter unit 220. Pixel abc, def, g
hi is line 21 from line memory 210, 211, 212 respectively
3, 214, and 215 are input. On the other hand, X is a reduced pixel, and A, B, and C are already reduced pixels, and line 2
Entered through 51,271.

FIG. 9 shows an example of selecting an exception pattern when the statistical processing unit 600 determines the nature of an image. The patterns (1), (2) and (3) in FIG. 9 (a) are for the case where the output differs between a positive image and a negative image. In such a case, if the image is a positive image of a character or a line drawing, the reduced image is black (4).
Is preferred. Conversely, in the case of a negative image, white (5) is a preferred example. Accordingly, with respect to the pattern shown in FIG. 9A, the exception pattern processing unit 610 outputs black (1) for a positive image and white (0) for a negative image to the exception pattern signal 261.

At this time, a signal indicating an exception is output as an exception pattern selection signal 262, and the exception pattern 261 from the exception processing unit 260 is selected by the selector 240 in FIG. 2 to obtain a reduced pixel result (the pixel in FIG. 8 x). ).

The pattern (1) in FIG. 9 (b) is preferably black (2) from the point of density preservation for a dither image, but white (3) for a non-dither image such as a line drawing. It is.
Reduced pixel C in both cases (a) and (b) (FIG. 8)
May be white or black.

As described above, in the reduction method of the present embodiment, the reduced image by the sub-sampling after the filter processing is corrected using the exception processing pattern. Also, an exceptional pattern is selected by statistical processing, and adaptive reduction according to image quality is performed.

 FIG. 10 shows the configuration of the encoding unit 4 (FIG. 1).

An original image or an icon image that is a 1 / ²ⁿ reduced image is input from a line 12 and a line 13, respectively. 12,
13 is the same as the line of the same number in FIG. Selector 14
In, the type of image to be encoded, that is, an original image or an icon image, is selected. Line 15 is a signal for selecting the type of image.

The state prediction unit 17 refers to the pixels surrounding the pixel of interest to be coded, and generates a prediction state for the arithmetic code processed by the coding unit.

FIG. 11 is a detailed block diagram of the state prediction unit 17. The image signal to be encoded is input from line 200. 17-1 is 1
A line memory 17-2 stores the pixel state two lines before, and 171-185 are latches for storing the surrounding pixels of the coded pixel.

The pixel of interest (encoded pixel) to be encoded is latch
This is the value stored in 172. The value of the line 201 indicates the output state of the line memory outputs 17-1 and 17-2 and the 13 latches 173 to 185, that is, the surrounding state of the coded pixel.

The information of the above 15 pixels is input to the selector 186, and a signal for selecting the type of image is used to select and output the input information. That is, the selector 186 selects different reference pixels between the original image and the icon image. FIG. 12 shows an example of the reference pixel.

In this embodiment, the reference pixels of the icon image are seven pixels around as shown in FIG. 12A, and the reference pixels of the original image are 11 pixels as shown in FIG. 12B. That is, since the icon image is obtained by reducing the original image, the correlation with the surrounding pixels is lower than that of the original image. Therefore, the number of reference pixels is reduced. The selection of the reference pixel is performed by the selector unit 186,
A state prediction signal St206 indicating the surrounding state is generated. The state prediction signal St206 and the coded pixel signal 203 are output from the coder 18 (the
10), and the encoder 18 performs encoding based on these signals.

 FIG. 13 is a block diagram of the encoder 11.

Before explaining FIG. 13, the arithmetic codes used in the present embodiment will be described.

As conventionally known, the arithmetic code is a method in which a code is formed by an arithmetic operation so that an input signal sequence becomes a code represented by a decimal binary number. This method is Langdo
n and Rissanen et al., “Compression of Blac
k / White Images with Arithmetic Coding ", IEEE T
ran Com.COM-29,6, (1981.6).
According to this document, the input signal sequence that has already been encoded is S, the probability of occurrence of a less-probable symbol (LPS) is q, the operation register Augen
When d is A (S) and the sign register is C (S), the following arithmetic operation is performed for each input signal.

A (S1) = A (S) × q ≒ A (S) × 2− ^Q (1) A (S0) = <A (S) −A (S1)> _l (2) <> _l is valid Censoring is indicated by the digit l bit.

C (S0) = C (S) (3) C (S1) = C (S) + A (S0) (4) where the encoded data is a dominant symbol (MPS: 0 in the above example) Uses A (S0) and C (S0) for encoding the next data. Further, in the case of a less-probable symbol (LPS: 1 in the above example), A (S1) and C (S1) are used for encoding the next data.

The new value of A is multiplied by 2 ^S (S is an integer greater than or equal to 0), and 0.5
A is within the range of 1.0. This processing corresponds to shifting the operation register A S times in hardware. The same number of shifts are performed on the code register C, and the shifted-out signal becomes a code. The above processing is repeated to form a code.

Also, by approximating the appearance probability q of LPS by a power of 2 (2 ^−Q : Q is a positive integer) as shown in the equation (1),
Multiplication calculation is replaced by shift operation. In order to further improve this approximation, q is set to, for example, 2 as in the equation (5).
It is approximated by a power polynomial. This approximation improves the worst efficiency.

q ≒ 2− ^Q1 + 2− ^Q2 (5) Further, since the arithmetic code can switch the value of Q for each encoded data, the probability estimating unit can be separated from the encoding.

In the present embodiment, a dynamic method of estimating a probability while performing encoding as described above is employed.

The block diagram of the encoder of FIG. 13 for performing the above arithmetic coding will be described.

The state signal St206 from the state prediction circuit 13 is input to the counter memory 23 and the encoding condition memory 24.

The encoding condition memory 24 stores, for each state represented by the state signal St206, a dominant symbol MPS108 that is a symbol that is likely to appear, and an index I107 that indicates an encoding condition including an appearance probability of an LPS of an arithmetic code described later. Have been.
The MPS 108 is input to the predictive conversion circuit 27, where the YN signal becomes 0 when the pixel signal D203 matches the MPS 108.
Make 101. The YN signal 101 is input to the update circuit 25, and when the YN signal is 0, the count of the corresponding state among the count values stored in the counter memory 23 is incremented. If the count value C106 stored in the counter memory 23 matches the set value MC105 from the count table ROM 12, the index I107
Is updated (the direction in which the appearance probability q of LPS decreases). (The MPS is not inverted.) Note that the count table ROM 22 supplies the update circuit 25 with the number of MPSs MC105 shown in Table 1 determined in correspondence with the index I representing the appearance probability q of the LPS. .

Also, in the updating circuit 25, when the MPS 108 and the pixel signal D203 do not match, that is, when the YN signal from the predictive conversion circuit 27 is 1, the index I107 decreases (the LPS appearance probability q increases). Update. When a YN signal with a value of 1 comes when the index is 1, the MPS is inverted (0 →
1 or 1 → 0). Output I'109, MPS '
110 is the updated index value, which is stored in the encoding condition memory 24 again.

In the coding parameter determination circuit 26, the index I107
The arithmetic parameter Q111 of the arithmetic code is set in the arithmetic coder 28 based on the value of. The arithmetic encoder 28 arithmetically encodes the YN signal 101 from the prediction conversion circuit 27 using the parameter Q111 to obtain a code 102.

Note that an initial value is given to the encoding condition memory 24 so that I, MP
By not updating S, static encoding can be easily realized.

FIG. 17 is a block diagram of the predictive conversion circuit 27. The pixel signal D203 and the MPS 108 are input to the EX-OR circuit 29, and a YN signal 101 which is 0 when the pixel signal D203 matches the MPS 108 and 1 when the pixel signal D203 does not match is output in accordance with the logical formula in Table 2.

FIG. 14 is a block diagram of the updating circuit 25. YN signal 10
When 1 is 0, the count value C106 from the counter memory 23 is incremented by +1 in the adder 31 to become a signal C'112. This value is calculated by the comparator 33 as M from the count table ROM22.
Compared to C105, if the value of C 'matches the value of MC,
The update signal UPA113 is set. The YN signal 101 becomes the update signal UPB114, and the UPA and UPB enter the index change circuit 35. UPA and UPB are logically ORed by an OR circuit 37.
The output signal 115 of the circuit 37 is a switching signal of the selector 32. When the signal 115 is 1, the selector 32 selects the 0 signal 119 to reset the counter value.
One output signal C'112 is selected, and the counter update signal C "116
, And this is stored in the counter memory 23.

The index change circuit 35 includes a signal d117 (typically d = 1) for controlling the index update interval and the UPA11.
3. The current index I107 is input from the UPB 114 and the encoding condition memory 24.

Table 3 is a table showing an index updating method in the index changing circuit 35 (Table 3 shows a case where the update increments are d = 1 and d = 2). The updated index I 'is determined by referring to UPA and UPB. Also, UP when I = 1
When B = 1, the EX signal 118 is set. When the EX signal is 1, the inverter 36 inverts the current symbol of the MPS 108 (0 →
1 or 1 → 0) to obtain the updated MPS′110. When the EX signal is 0, MPS 'is not changed. The updated I'109 and MPS'110 are stored in the encoding condition memory 24 and used as the index I and MPS for the next processing. still,
The updating method shown in Table 3 can be constituted by a table using a ROM or the like, or can be constituted by logic using an adder / subtractor.

As described above, when as many MPSs as the number of MPSs determined according to the value of the index I representing the appearance probability q of the LPS approximated by the power-of-two polynomial are generated, the index I
Is added, and the appearance probability q of the LPS used for the arithmetic code is reduced. On the other hand, when the LPS occurs, the index I is subtracted by d to increase the appearance probability q of the LPS used for the arithmetic code. Further, when the LPS is generated while the index I indicating that the appearance probability q of the LPS is 0.5 is 1, the MPS is inverted.

In this way, the index and MPS
Is updated, arithmetic coding with good coding efficiency can be achieved.

FIG. 15 is an encoding efficiency curve of the arithmetic code used in the present embodiment. Hereinafter, the value of the index I is indicated by a small letter i.
This curve shows the appearance probability of LPS as q and the approximate probability q at the time of encoding.
_When expressed as _ei , it is expressed by equation (6). Then, the indexes I are sequentially assigned as 1, 2, 3,... From the larger value of the appearance probability q of the LPS to the smaller value.

Here, the numerator is entropy, and q _ei is a value represented by Expression (7).

The value of _{q ei = q 1 + q 2} ... (7) q 1, q 2 is given in Table 5 by the value of the polynomial approximation of the power of two. For example, they are shown in (8) to (10).

q _e1 '= 2 ^-1 ... (8) q _e2 ' = 2 ^-1 -2 ^-4 ... (9) q _e3 '= 2 ^-2 +2 ^-3 ... (10) At this probability, the efficiency η becomes 1.0. The peak point q _ei is hereinafter referred to as an effective probability. In addition, it is clear that the efficiency is improved when the intersection of the efficiency curves is called a boundary probability q _bi and coding is performed using the adjacent effective probability with this probability as a boundary.

In the present embodiment, the effective probabilities q _ei shown in Table 4 are selected from the probabilities that can be approximated by two terms as shown in Expression (5). _{Also, Q 1, Q 2, Q} 3 of Table 4 is the parameter Q _C 111 to be sent to the arithmetic encoder 18. That is, Q ₁ and Q ₂ are shift amounts given to the shift register, and the power of 2 is calculated by this shift operation. Q ₃ indicates the coefficient of the second term, and switches between + and-.

 The MC values in Table 1 are determined as follows.

That is, when the number of LPS N _L, the number of MPS was N _M, the probability of LPS is given by equation (11).

Solving this equation with N _M gives equation (12).

N _M = N _L (1 / q−1) (12) where x represents the fractional part rounded up. Expression (1
By giving q _bi shown in FIG. 6 to q in 2), the number N _Mi of dominant symbols (MPS) there is calculated. Therefore, MC is calculated from equation (13).

MCi = N _{Mi + 1} −N _Mi (13) The value of MC in Table 1 is obtained from equations (11), (12), and (13) using N _L =
It is calculated as 2.

Thus, the number N _{Mi of} the dominant symbols MPS corresponding to each index I based on each boundary probability q _bi as shown in FIG.
The calculated, the difference between the dominant symbol N _M between adjacent Indetsukusu and MC for each Indetsukusu I.

Then, the MC value is compared with the number of dominant symbols to be generated as described above. If the MC value matches the number of dominant symbols, the state is determined to be suitable for encoding using the adjacent index I. And the index I is changed. As a result, the index I is changed at a favorable timing based on the number of occurrences of the superior symbols, and the encoding using the optimal index I can be adaptively achieved.

 FIG. 16 is a block diagram of the arithmetic encoder 28.

Control signal determined by the code parameter determining circuit 26 Q _C 111 to Q ₁ in the shift register A70 of the (Table 4),
Q ₂ is input to the shift register B, and Q ₃ is input to the selector 72.
Q ₁ and Q ₂ are Augend for shift registers A and B, respectively.
It indicates how many bits to shift the signal As123 right.
The shifted results are output signals 130 and 131.

The signal 131 is complemented by the inverter 76 and
2 selects the output signal of the signal 131 or the inverter 76 by the control signal Q _3, to obtain an output signal 132. In the adder 72, the signal 130 from the shift register A70 and the signal from the selector 72
The addition of 132 is performed, and an _AS1 signal 124 is output. Subtractor 7
In 4 subtracts the A _S1 signal 124 from the A _S signal 123, A _S0 signal 125
Get. One of the selectors 75 in the A _S0 signal 125 and A _S1 signal 124 selected by the YN signal 101. That is A _S0 signal when the YN signal is 1, also the A _S1 signal when the YN signal is 0 is A 'signal 126. In the shift circuit 80, a process of shifting to the left until the MSB of the A 'signal becomes 1 is performed.
As' signal 127 is obtained. The shift signal 132 corresponding to the number of shifts enters the code register 79, and the number of bits corresponding to the number of shifts are output from the code register 79 in order from the MSB to become the code data 130.

The code data 130 is converted into a bit by a bit processing method (not shown).
Are processed so as to be within a finite number, and are transmitted to the decoder 14 side.

The contents CR128 code register 79 by the adder 77 A _S0
The signal is added to the signal 125 and the result is input to the selector 78. Also, the A _S0 signal
The 125 non-added signal CR128 also enters the selector 78,
CR '= CR when YN signal 101 is 1, CR' when YN signal is 0
= CR + A _S0 is output as the CR 'signal 129. The shift processing described above for the code register 79 is performed on the CR 'signal.

As described above, the icon image and the original image are independently encoded by the encoding unit 4 and transmitted in the order of the icon image and the original image, or stored in the storage device.

A case where this embodiment is used for transmitting an image such as a facsimile will be described. FIG. 18 shows an example. The facsimile transmitting section 18-1 sequentially transmits the icon image and the original image encoded in this embodiment to the facsimile receiving section 18-2 via the communication line 18-4. Facsimile receiver 18
In -2, the original image received after storing the previously received icon image in the storage device 18-3 is decoded and output to a medium such as paper. On the other hand, the stored icon images can be output as a list of received images or transmitted images as facsimile management information as shown in FIG.

Note that the icon image has a very small size and a very small data amount due to encoding. For example, if the size of the icon is set to 1/32 of the vertical size, 1/32 in the uncompressed state
This is a data amount of 1024, and when this is encoded, the data amount becomes extremely small, so that the memory device of the receiving terminal requires only a small capacity.

FIG. 20 shows an example in which the present embodiment is used for soft copy communication using a display as a medium, such as communication between computer terminals. FIG. 20 shows an example in which an image stored in the memory 20-1 of the terminal 20-2 is transmitted to the terminal 20-3 and stored in the memory 20-4. The icon image and the original image are coded and stored in the memory 20-1 by this method. First, the icon image is transmitted from the terminal 20-2 to the terminal 20-3 via the line 20-5. Since the data amount of the icon is very small as described above, the image can be quickly received and displayed on the display. At this time, an enlarged image may be displayed at the same time using a method such as interpolation.

At this time, if the received image is not the desired one, the terminal 20-3 can stop transmitting to the terminal 20-2 before receiving the original image. By doing so, it is possible to prevent unnecessary data transmission due to a wrong image at the time of image transmission.

FIG. 21 shows an example in which this embodiment is applied to an image database. The storage device 21-1 stores an encoded data pair of an icon image and an original image encoded using this method as an image database. Keyboard for image search
According to the instruction of 21-4, only the icon image of each image is read from the storage device 21-1 and displayed on the display 21-2.
Since the icon image uses this method, the data amount is small and can be grasped in an outline. Display 21-
The original image of the image selected from the icon image directory displayed on the keyboard 21-4 by the instruction of the keyboard 21-4 is coded independently of the icon image, so that the original image is decoded at high speed. 3 can be printed out. Therefore, waste in the image database can be eliminated, and the icon image and the original image can be independently decoded. The image database is more effective when it exists in the memory of another terminal as shown in FIG.

In the present embodiment, the icon image and the original image are both encoded using the arithmetic code method. However, similar effects can be obtained by using other entropy encoding methods such as known MH codes, MR codes, and MMR codes. can get.

[Effects of the Invention] As described above, according to the present invention, a reduced image of a desired size and an original image are encoded, and thereby, two-layer sequential code transmission of the reduced image and the original image can be performed,
Unnecessary intermediate layer code data can be saved, and the apparatus can be downsized without the need for a frame memory for the intermediate layer, encoding and decoding.

Also, when used for facsimile communication, storing reduced images enables facsimile communication management and the like with reduced images, and when applied to image databases, quick search can be performed by using reduced images for image search. It becomes possible. In addition, the original image can be directly decoded without decoding the unnecessary middle layer at the time of decoding, and there is an effect that the data amount and the decoding time can be improved.

[Brief description of the drawings]

FIG. 1 is a block diagram showing an outline of an encoding apparatus, FIG. 2 is a block diagram of a reduction unit, FIG. 3 is a diagram showing coefficients of a low-pass filter, FIG. 4 is a diagram showing a subsampling method, FIG. FIG. 6 is a diagram showing an example in which a thin line disappears due to a low-pass filter. FIG. 6 is a block diagram of an exception processing unit. FIG. 7 is a diagram showing a statistical processing method. FIG. 10 is a diagram showing an example of exception processing selection by statistical processing, FIG. 10 is a block diagram of an encoding unit, FIG. 11 is a block diagram of a state prediction unit, FIG. 12 is an example of a reference pixel position, FIG. Fig. 14 is a block diagram of an encoder, Fig. 14 is a block diagram of an update circuit, Fig. 15 is a diagram showing a coding efficiency curve, Fig. 16 is a block diagram of an arithmetic encoder, and Fig. 17 is a block diagram of a prediction conversion circuit. Figure 18, Figure 18 shows an example applied to facsimile communication, Figure 19 FIG. 20 is a diagram showing an output example of millimeter communication, FIG. 20 is a diagram showing an example applied to soft copy communication, FIG. 21 is a diagram showing an example applied to an image database, FIG. 22 is a diagram showing a conventional example, Reference numerals 1 and 3 denote a frame memory, 2 denotes an image reduction unit, 4 denotes an encoding unit, 14 denotes a selector, and 18 denotes an encoder.

Continued on the front page (58) Fields surveyed (Int.Cl. ⁶ , DB name) H04N 1/41-1/419 H04N 7/24-7/68 H04N 7/14-7/173 H04N 1/21 H04N 1 / 387-1/393

Claims (2)

(57) [Claims] An input step of inputting original image data representing an original image; a first storage step of storing the input original image data in a memory; and performing a plurality of reduction processes on the original image data read from the memory. Performing a reduction step of forming reduced image data representing a reduced image of a desired size, a second storage step of storing the formed reduced image data in a memory, reduced image data and original image data stored in the memory And a coding step of coding the following. 2. An input means for inputting original image data representing an original image, and a first means for storing the original image data input from the input means.
Storage means; reduction means for forming reduced image data representing a reduced image of a desired size by performing a plurality of reduction processes on the original image data read from the first storage means; A second storage unit for storing the reduced image data; and an encoding unit for encoding the reduced image data stored in the second storage unit and the original image data stored in the first storage unit. An image encoding device, characterized in that: