JP2833015B2 - Wiring formation method - Google Patents
Wiring formation methodInfo
- Publication number
- JP2833015B2 JP2833015B2 JP15020389A JP15020389A JP2833015B2 JP 2833015 B2 JP2833015 B2 JP 2833015B2 JP 15020389 A JP15020389 A JP 15020389A JP 15020389 A JP15020389 A JP 15020389A JP 2833015 B2 JP2833015 B2 JP 2833015B2
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- JP
- Japan
- Prior art keywords
- substrate
- wiring
- wiring material
- deposited
- film
- Prior art date
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Description
【発明の詳細な説明】 〔産業上の利用分野〕 本発明は、半導体装置の製造工程における配線形成方
法に関する。Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a wiring forming method in a semiconductor device manufacturing process.
本発明は、半導体装置の製造工程における配線形成方
法、更に詳しくは基体上のアスペクト比が1以上の接続
孔に、アルミニウム(Al)またはAlを主体とする合金か
らなる配線材料を埋め込む配線形成方法において、基体
を低温に保持して配線材料を薄く蒸着したのち、引き続
き、基体を高温にして配線材料を厚く蒸着することによ
り、接続孔内にボイドを残さずにステップカバレッジに
優れた配線を形成するようにしたものである。The present invention relates to a method of forming a wiring in a manufacturing process of a semiconductor device, and more particularly, to a method of forming a wiring in which a wiring material made of aluminum (Al) or an alloy mainly composed of Al is embedded in a connection hole having an aspect ratio of 1 or more on a substrate. , The wiring is thinly deposited while the base is kept at a low temperature, and then the wiring is thickly deposited by raising the base to a high temperature to form wiring having excellent step coverage without leaving voids in the connection holes. It is something to do.
LSI等の半導体装置においては、素子の微細化,高密
度化及び多層化に伴い、接続孔のアスペクト比すなわち
孔の深さと直径の比が1以上と大きな値が採用されつつ
あり、接続孔へ配線材料の埋め込み平坦化が難かしくな
りつつある。In semiconductor devices such as LSIs, the aspect ratio of the connection hole, that is, the ratio of the depth to the diameter of the hole is being adopted as a large value of 1 or more with the miniaturization, high density, and multi-layer of the element. It is becoming difficult to make the wiring material buried flat.
従来よりAlまたはAlを主体とする合金からなる配線材
料を、薄膜の形状で基体上に形成する方法は、平行平板
型等のスパッタリング法が主として用いられてきた。し
かし、従来からのスパッタリンク法においては、アスペ
クト比の大きな接続孔になると、その内部にはいわゆる
シャドウイング効果のため配線材料が入って行けず、接
続孔の底部や側壁でのステップカバレッジが不足し配線
の信頼性を落してしまう。これを改善する方法として、
基体に負のDCバイアス電圧またはRFバイアス電圧を印加
しながら成膜するバイアススパッタリング法、基体を高
温加熱しながら成膜する高温スパッタリング法、あるい
はこの両方法を併用する高温バイアススパッタリング法
がある(例えば月刊Semiconductor World誌,1988年2月
号,P.77参照)。これらの方法は、いずれも基体上に堆
積したAlやAlを主体とした合金等の配線材料の再スパッ
タリングや、あるいは熱エネルギーによる表面マイグレ
ーションを促進して、埋め込み特性を改善して平坦化を
達成しようというものである。Conventionally, as a method of forming a wiring material made of Al or an alloy mainly composed of Al on a substrate in the form of a thin film, a sputtering method such as a parallel plate type has been mainly used. However, in the conventional sputter link method, when a connection hole having a large aspect ratio is formed, the wiring material cannot enter into the connection hole due to a so-called shadowing effect, and the step coverage at the bottom and the side wall of the connection hole is insufficient. Then, the reliability of the wiring is reduced. As a way to improve this,
There is a bias sputtering method in which a film is formed while applying a negative DC bias voltage or an RF bias voltage to a substrate, a high temperature sputtering method in which a film is formed while heating a substrate at a high temperature, or a high temperature bias sputtering method in which both methods are used (for example, Monthly Semiconductor World Magazine, February 1988, p. 77). All of these methods achieve re-sputtering of wiring material such as Al or Al-based alloy deposited on the substrate, or surface migration by thermal energy to improve the filling characteristics and achieve flattening. It is to try.
一方、先に本発明者らは、さらに、より確実な埋め込
みを達成する方法として、基体を450℃以上で配線材料
の融点以下の高温に加熱しながら配線材料を真空蒸着す
る高温蒸着法を提案した。この方法は、スパッタリング
法と比べて高真空度であるために蒸発源からの粒子の平
均自由行程が大きく、且つ基体面垂直方向に対する粒子
の入射角度が小さいので基体面への粒子の垂直入射成分
が多く、接続孔の内部に容易に配線材料を堆積できる。
さらに、基体を高温加熱しているので、堆積した配線材
料の表面マイグレーションが同時に行われ、堆積膜のス
テップカバレッジがさらに優れるというものである。On the other hand, the present inventors have previously proposed a high-temperature deposition method in which a wiring material is vacuum-deposited while heating the substrate to a high temperature not lower than the melting point of the wiring material at 450 ° C. or higher as a method for achieving more reliable embedding. did. This method has a higher degree of vacuum than the sputtering method, so that the mean free path of the particles from the evaporation source is large, and the angle of incidence of the particles with respect to the direction perpendicular to the substrate surface is small. And a wiring material can be easily deposited inside the connection hole.
Further, since the substrate is heated at a high temperature, the surface migration of the deposited wiring material is performed at the same time, and the step coverage of the deposited film is further improved.
しかしながら、この高温蒸着方法では、例えば第5図
に示す表面に接続孔(3)を有するSiO2膜(2)が被着
形成されたシリコン基体(1)を、蒸着装置のチャンバ
内において最初から、450℃以上のヒーターブロックに
接触させるため、成膜(例えばAl成膜)の初期状態にお
いて、同図に示すようなAl(4)の島状成長が起り、接
続孔(3)内にボイド(5)が残りやすいという問題が
あった。However, in this high-temperature deposition method, for example, a silicon substrate (1) on which a SiO 2 film (2) having a connection hole (3) on the surface shown in FIG. In the initial state of film formation (for example, Al film formation), island-like growth of Al (4) occurs as shown in the figure, and voids are formed in the connection holes (3). There is a problem that (5) tends to remain.
本発明は、上述の点に鑑み、接続孔内にボイドを残さ
ずに配線材料を埋め込むと共に、接続孔へのステップカ
バレッジに優れた配線を形成できるようにした配線形成
方法を提供するものである。The present invention has been made in view of the above-described circumstances, and provides a wiring forming method in which a wiring material is buried without leaving a void in a connection hole and a wiring having excellent step coverage to the connection hole can be formed. .
本発明による配線形成方法は、接続孔を有する半導体
等の基体にAlまたはAlを主体とする合金からなる配線材
料を真空蒸着するが、最初に基体を450℃未満の低温に
保持して段差に沿って薄く真空蒸着した後、引き続き基
体を450℃以上で配線材料の融点以下の高温に加熱しな
がら厚く真空蒸着を行うものである。In the wiring forming method according to the present invention, a wiring material made of Al or an alloy mainly composed of Al is vacuum-deposited on a substrate such as a semiconductor having a connection hole, but the substrate is first kept at a low temperature of less than 450 ° C. Then, the substrate is vacuum-deposited thickly while heating the substrate to a high temperature of 450 ° C. or higher and lower than the melting point of the wiring material.
上記後段の基体の加熱温度は、450℃未満では接続孔
部分での配線材料の堆積膜のステップカバレッジが充分
でなく、一方、配線材料の融点を越えると、液体となっ
た配線材料の表面張力や粘性流動のため平坦性が悪化
し、共に本発明の効果を発揮することができない。If the heating temperature of the latter substrate is less than 450 ° C., the step coverage of the deposited film of the wiring material at the connection hole portion is not sufficient. On the other hand, if it exceeds the melting point of the wiring material, the surface tension of the liquid wiring material becomes liquid. And the viscous flow deteriorates the flatness, and cannot exert the effects of the present invention.
基体の加熱方法は、特に限定されるものではないが、
例えば抵抗加熱ヒータによる方法,ハロゲンランプやア
ークランプ照射による方法等が用いられる。The method of heating the substrate is not particularly limited,
For example, a method using a resistance heater, a method using irradiation with a halogen lamp or an arc lamp, or the like is used.
真空蒸着装置は、これも得に限定されるものではな
く、例えば抵抗加熱,電子ビーム加熱,高周波加熱等の
手段によりAlまたはAlを主体とする合金からなる配線材
料を蒸発させる装置が用いられる。真空蒸着時のチャン
バ内圧力は、通常の真空蒸着で用いられる真空度で充分
であり、一例として10-5Torrであれば良い。要は配線材
料の蒸発粒子の平均自由行程が大きく、基体に対する垂
直入射成分がスパッタリング法に比べて充分大きな割合
を占めるような真空度ならば良いのであり、本発明の効
果を損なわない範囲内で、任意に選定することが可能で
ある。The vacuum evaporation apparatus is not particularly limited, and an apparatus that evaporates a wiring material made of Al or an alloy mainly containing Al by means of, for example, resistance heating, electron beam heating, high-frequency heating, or the like is used. The pressure in the chamber at the time of vacuum deposition is sufficient to be the degree of vacuum used in ordinary vacuum deposition, and may be, for example, 10 −5 Torr. In short, it is only necessary that the degree of vacuum is such that the mean free path of the evaporating particles of the wiring material is large and the perpendicular incidence component to the substrate occupies a sufficiently large ratio as compared with the sputtering method, so long as the effects of the present invention are not impaired. , Can be arbitrarily selected.
真空蒸着法は、蒸発源の面積が基体の面積に比べて小
さい。また堆積膜形成時のチャンバ内の真空度は例えば
10-5Torrとスパッタリング法と比較してはるかに高真空
度であり、このため蒸着源からの粒子の平均自由行程が
大きく、基体面垂直方向に対する粒子の入射角度が小さ
い。すなわち基体面への粒子の垂直入射成分が多い。よ
って基体面に垂直に形成された深い接続孔の底部にも容
易に配線材料の粒子が入射でき、接続孔の内部に配線材
料を堆積することができる。In the vacuum evaporation method, the area of the evaporation source is smaller than the area of the substrate. Also, the degree of vacuum in the chamber at the time of forming the deposited film is, for example,
Since the degree of vacuum is much higher than that of the sputtering method at 10 -5 Torr, the mean free path of the particles from the evaporation source is large, and the incident angle of the particles with respect to the direction perpendicular to the substrate surface is small. That is, there are many perpendicular incident components of the particles on the substrate surface. Therefore, particles of the wiring material can easily enter the bottom of the deep connection hole formed perpendicular to the substrate surface, and the wiring material can be deposited inside the connection hole.
そして、最初に基体を450℃未満の低温に保持して薄
く蒸着することにより、堆積膜の島状成長は起らず、段
差に沿って均一な堆積膜が形成される。次に、引き続い
て基体を450℃以上でAlまたはAlを主体とする合金から
なる配線材料の融点以下の高温に加熱して所要の厚さに
蒸着すると、下層に均一な堆積膜が存在しているため、
島状成長は起らず、引き続き均一な堆積膜が形成され、
その結果、接続孔内にボイドを残すことなく配線材料の
埋め込みが達成される。また後段の基体を高温にして蒸
着することにより、堆積した配線材料の表面マイグレー
ションが同時に行われ、堆積膜のステップカバレッジは
さらに優れたものとなる。Then, by first depositing the substrate at a low temperature of less than 450 ° C. and thinly depositing it, island-like growth of the deposited film does not occur, and a uniform deposited film is formed along the steps. Next, when the substrate is subsequently heated to a temperature not lower than the melting point of the wiring material made of Al or an alloy mainly composed of Al at a temperature of 450 ° C. or higher and deposited to a required thickness, a uniform deposited film is present in the lower layer. Because
Island growth does not occur, a uniform deposited film is continuously formed,
As a result, embedding of the wiring material is achieved without leaving voids in the connection holes. In addition, by vapor-depositing the latter substrate at a high temperature, the surface migration of the deposited wiring material is performed at the same time, and the step coverage of the deposited film is further improved.
以上の作用により、半導体等の基体上の深い接続孔を
AlまたはAlを主体とする合金からなる配線材料で埋め込
む配線形成方法において、接続孔への埋め込み特性に優
れ、しかも接続孔部分の配線材料堆積膜表面の平坦性の
良いステップカバレッジに優れた配線の形成が可能とな
る。By the above operation, a deep connection hole on a substrate such as a semiconductor is formed.
In a wiring forming method of embedding with a wiring material made of Al or an alloy mainly composed of Al, a wiring having an excellent embedding property in a connection hole and a good flatness of a wiring material deposition film surface in a connection hole portion and an excellent step coverage. Formation is possible.
以下、図面を参照して本発明の実施例を説明する。 Hereinafter, embodiments of the present invention will be described with reference to the drawings.
実施例1 シリコン等の基体(1)に例えばCVD法により酸化シ
リコン(SiO2)からなる絶縁膜(2)を形成し、ここに
アスペクト比約1.2の接続孔(3)を開口する。次に第
1図に示すように2つの蒸着室(11)及び(12)と移送
室(13)、さらに図示しないが仕込み兼取り出し室を有
する枚葉式の真空蒸着装置(14)を用意する。Examples e.g., CVD substrate (1) such as a first silicon to form a silicon oxide insulating film made of (SiO 2) (2), wherein the opening of the aspect ratio of about 1.2 of the connecting hole (3). Next, as shown in FIG. 1, a single-wafer vacuum evaporation apparatus (14) having two evaporation chambers (11) and (12), a transfer chamber (13), and a charging / unloading chamber (not shown) is prepared. .
前記基体(1)を仕込み室から移送室(13)を経て第
1蒸着室(11)に送り、ホルダー(15)に設置する。第
1蒸着室(11)内圧力は真空ポンプ(16)により例えば
10-6Torrに減圧する。純度ファイブナインの高純度Alを
ハース(17)内で溶解し、蒸発源(18)とする。なお、
蒸発源(18)から基体(1)を臨む見込み角度αは略10
゜以内となるようにした。そして基体(1)を加熱せず
室温の状態で(もしくは450℃未満の加熱を行ってもよ
い)真空蒸着し、第2図Aに示すように、段差に沿って
約500Å程度の薄いAl堆積膜(21A)を形成する。この蒸
着では低温で成膜するためAlの島状成長は抑えられ均一
なAl堆積膜(21A)が形成される。次に、この基体
(1)を移送室(13)を経て第2蒸着室(12)に送り、
ヒータブロック(19)に密着して設置する。第2蒸着室
(12)内圧力,蒸発源(18)等の条件は第1蒸着室(1
1)と同じである。そして、基体(1)をヒータブロッ
ク(19)を介して450℃〜600℃に加熱しながら、真空蒸
着し、先の薄いAl堆積膜(21A)上にさらに約7500Å程
度の厚いAl堆積膜(21B)を形成する。このとき、成膜
の最初から加熱した場合と異なり、下層に均一なAl堆積
膜(12A)が存在しているため、上層のAl堆積膜(21B)
には島状成長は起らず、引き続き均一な成膜が行われ
る。また基体(1)を450℃〜600℃の高温にして蒸着す
るのでAl堆積膜(21B)の表面拡散が盛んなため、接続
孔(3)内にもAlが均一に流入し、ボイドのない埋め込
みが達成され、Al堆積膜(21)の表面の平坦化もよく、
ステップカバレッジに優れるものである。The substrate (1) is sent from the charging chamber to the first vapor deposition chamber (11) via the transfer chamber (13), and is set on the holder (15). The pressure in the first vapor deposition chamber (11) is, for example, controlled by a vacuum pump (16).
Reduce pressure to 10 -6 Torr. High purity Al of high purity Five Nine is dissolved in the hearth (17) and used as an evaporation source (18). In addition,
The expected angle α facing the substrate (1) from the evaporation source (18) is approximately 10
Within ゜. Then, the substrate (1) is vacuum-deposited at room temperature (or may be heated to less than 450 ° C.) without heating, and as shown in FIG. 2A, a thin Al deposit of about 500 ° is formed along the step. A film (21A) is formed. In this vapor deposition, since the film is formed at a low temperature, Al island growth is suppressed and a uniform Al deposited film (21A) is formed. Next, the substrate (1) is sent to the second vapor deposition chamber (12) via the transfer chamber (13),
Installed in close contact with the heater block (19). Conditions such as the internal pressure of the second vapor deposition chamber (12) and the evaporation source (18) are as follows.
Same as 1). Then, the substrate (1) is vacuum-deposited while being heated to 450 ° C. to 600 ° C. via the heater block (19), and a thicker Al deposited film (about 7500 °) (about 7500 °) is further formed on the thinner Al deposited film (21A). 21B). At this time, unlike the case where heating is performed from the beginning of the film formation, since the uniform Al deposited film (12A) exists in the lower layer, the upper Al deposited film (21B)
No island growth occurs, and a uniform film is continuously formed. Further, since the substrate (1) is deposited at a high temperature of 450 ° C. to 600 ° C., the surface diffusion of the Al deposited film (21B) is active, so that Al uniformly flows into the connection hole (3) without voids. The burying is achieved, and the surface of the Al deposition film (21) is flattened well.
Excellent step coverage.
実施例2 実施例1では低温用と高温用の2つの蒸着室(11)及
び(12)を有する真空蒸着装置(14)を用いたが、第3
図に示すように1つの蒸着室(31)を有する真空蒸着装
置(32)を用いて行うことも可能である。即ち、真空蒸
着装置(32)の蒸着室(31)内において、まず第4図A
に示すように基体(1)をヒータブロック(19)の下部
に之に接しないように爪部(33)を介して保持し、基体
(1)の温度を450℃未満に保つ。この状態で蒸発源(1
8)よりのAlを蒸着し、前述の第2図Aに示すように約5
00Å程度の薄いAl堆積膜(21A)を形成する。次に第4
図Bに示すように基体(1)を450℃〜600℃に加熱した
ヒータブロック(19)に密着し、薄いAl堆積膜(21A)
上に約7500Å程度の厚いAl堆積膜(21B)を形成する。
これにより実施例1と同様に接続孔(3)にボイドのな
い埋め込みが達成され、ステップカバレッジの良いAl堆
積膜(21)が形成される。Example 2 In Example 1, a vacuum evaporation apparatus (14) having two evaporation chambers (11) and (12) for low temperature and high temperature was used.
As shown in the figure, it is also possible to use a vacuum evaporation apparatus (32) having one evaporation chamber (31). That is, in the vapor deposition chamber (31) of the vacuum vapor deposition device (32), first, FIG.
As shown in (1), the base (1) is held at the lower portion of the heater block (19) via the claw (33) so as not to be in contact with the lower part, and the temperature of the base (1) is kept below 450 ° C. In this state, the evaporation source (1
8) Al is vapor-deposited to a thickness of about 5 as shown in FIG.
A thin Al deposition film (21A) of about 00 ° is formed. Then the fourth
As shown in FIG. B, the substrate (1) is brought into close contact with a heater block (19) heated to 450 ° C. to 600 ° C. to form a thin Al deposited film (21A).
A thick Al deposition film (21B) of about 7500 約 is formed thereon.
As a result, as in the first embodiment, void-free filling of the connection hole (3) is achieved, and an Al deposition film (21) having good step coverage is formed.
本発明によれば、半導体等からなる基体上に形成され
たアスペクト比が1以上の接続孔をAlまたはAlを主体と
する合金からなる配線材料で埋め込む配線形成方法にお
いて、基体を450℃未満に保持して配線材料を段差に沿
って薄く真空蒸着した後、引き続いて基体を450℃以上
配線材料の融点以下に加熱して、配線材料を厚く真空蒸
着することにより、接続孔内部にボイドを残すことな
く、配線材料の埋め込みを行うことができ、接続孔への
埋め込み特性に優れ、しかも接続孔部分の配線材料堆積
表面の平坦性の良いステップカバレッジに優れた配線
(各層配線を含む)を形成することができる。According to the present invention, in a wiring forming method in which a connection hole having an aspect ratio of 1 or more formed on a substrate made of a semiconductor or the like is filled with a wiring material made of Al or an alloy containing Al as a main component, After holding and vapor-depositing the wiring material thinly along the step, subsequently heating the substrate to 450 ° C. or higher and lower than the melting point of the wiring material, and vacuum-depositing the wiring material to leave voids inside the connection holes. Wiring material can be buried without any problems, and excellent wiring characteristics (including wiring in each layer) with excellent filling characteristics in connection holes and good step coverage with good flatness of wiring material deposition surface in connection hole portions can do.
従って、従来の通常のスパッタリング法はもとより、
バスアススパッタリング法等、ステップカバレッジに優
れているとされていた方法によっても困難であったアス
ペクト比が1を越える接続孔をも良好に埋め込むことが
でき、信頼性に富んだ配線の形成が可能となるものであ
る。Therefore, let alone the conventional ordinary sputtering method,
Connection holes with an aspect ratio of more than 1 that were difficult even with methods that were considered excellent in step coverage, such as bath as sputtering, can be buried well, and highly reliable wiring can be formed. It is what becomes.
第1図は、本発明の第1の実施例による配線形成方法を
示す概略断面図、第2図A及びBは本発明に係る配線形
成工程図、第3図は本発明の第2の実施例による配線形
成方法を示す概略断面図、第4図A及びBはそのヒータ
ブロックへの基体の保持方法を示す側面図、第5図は本
発明の説明に供する断面図である。 (1)はシリコン等の基体、(2)は絶縁膜、(3)は
接続孔、(4)はAl、(5)はボイド、(21A)(21B)
はAl堆積膜である。FIG. 1 is a schematic sectional view showing a wiring forming method according to a first embodiment of the present invention, FIGS. 2A and 2B are wiring forming process drawings according to the present invention, and FIG. 3 is a second embodiment of the present invention. FIGS. 4A and 4B are schematic cross-sectional views showing a wiring forming method according to an example, FIGS. 4A and 4B are side views showing a method of holding a base on the heater block, and FIG. 5 is a cross-sectional view for explaining the present invention. (1) is a substrate such as silicon, (2) is an insulating film, (3) is a connection hole, (4) is Al, (5) is a void, (21A) and (21B).
Is an Al deposited film.
Claims (1)
の接続孔に、アルミニウム又はアルミニウムを主体とし
た合金からなる配線材料を埋め込む配線形成方法であっ
て、 前記基体を450℃未満に保持して、前記配線材料を真空
蒸着して、段差に沿って成膜された薄い第1の堆積膜を
形成し、 次いで前記基体を450℃以上前記配線材料の融点以下に
加熱して、該配線材料を真空蒸着し、上記第1堆積膜上
に第1の堆積膜よりも厚い第2の堆積膜を形成する ことを特徴とする配線形成方法。1. A wiring forming method for embedding a wiring material made of aluminum or an alloy mainly composed of aluminum into a connection hole having an aspect ratio of 1 or more formed on a substrate, wherein the substrate is kept at a temperature of less than 450 ° C. Then, the wiring material is vacuum-deposited to form a thin first deposited film formed along a step, and then the substrate is heated to 450 ° C. or higher and the melting point of the wiring material, and A method for forming a wiring, comprising: vacuum depositing a material to form a second deposited film thicker than the first deposited film on the first deposited film.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP15020389A JP2833015B2 (en) | 1989-06-13 | 1989-06-13 | Wiring formation method |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP15020389A JP2833015B2 (en) | 1989-06-13 | 1989-06-13 | Wiring formation method |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH0314233A JPH0314233A (en) | 1991-01-22 |
| JP2833015B2 true JP2833015B2 (en) | 1998-12-09 |
Family
ID=15491778
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP15020389A Expired - Fee Related JP2833015B2 (en) | 1989-06-13 | 1989-06-13 | Wiring formation method |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2833015B2 (en) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2007044086A (en) * | 2005-08-05 | 2007-02-22 | Miyuki Yano | Teaching material for intellectual training relating to welfare |
-
1989
- 1989-06-13 JP JP15020389A patent/JP2833015B2/en not_active Expired - Fee Related
Also Published As
| Publication number | Publication date |
|---|---|
| JPH0314233A (en) | 1991-01-22 |
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