JP2833259B2 - Program repeat control method and program repeat control device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a program repeat control method and apparatus for controlling the repetitive execution of one instruction in a microprocessor.

[0002]

2. Description of the Related Art In recent years, high-speed execution of a program or reduction of the number of words in an instruction memory has been attempted.
A program repeat processing device that repeatedly executes an instruction once fetched, as disclosed in Japanese Patent No. 42301, has been devised.

An example of the above-described conventional program repeat control device will be described below with reference to the drawings.

FIG. 7 is a block diagram showing a conventional program repeat control device. 7, reference numeral 71 denotes a repeat counter for counting the number of program repetitions (same as the number of repeats); 72, a memory for storing instructions; 73, a program counter for giving an address to the memory 72; The held instruction register 75 is a control unit that decodes the output of the instruction register and outputs various control signals.

The operation of the conventional program repeat control device configured as described above will be described below. First, as shown in FIG. 8, a repeat counter set instruction 81 at address n of the memory 72 and an instruction A8 at address n + 1.
Instruction B83 is stored at addresses 2, n + 2, respectively.
When the program counter 73 reaches n in this state, the repeat counter set instruction 81 is stored in the instruction register 74, and the number of repeats (seven in this case) included in the instruction code is stored in the repeat counter 71.
The control unit 75 receives the output of the instruction register 74, and stores the next instruction stored in the instruction register 74 into the repeat counter 71.
Control is repeated until becomes zero. Then, when the program counter 73 becomes n + 1 and the instruction A82 is stored in the instruction register 74, the instruction A82 is executed seven times as shown in FIG. (Japanese Patent Publication 62-42301
No.)

[0006]

However, in the above configuration, the execution cycle of the repeat counter set instruction appears explicitly as shown in FIG. On the other hand, a digital signal processor (Digital Signal)
l Processor (hereinafter referred to as DSP)
One instruction or group of instructions is often executed thousands of times, but using a conventional program repeat controller consumes thousands of machine cycles to execute non-operational instructions such as the repeat counter set instruction as described above. As a result, there is a problem that this greatly hinders the high-speed operation which is the purpose of the DSP.

SUMMARY OF THE INVENTION The present invention has been made in consideration of the above problems, and has as its object to provide a program repeat processing apparatus in which a repeat counter set instruction execution cycle is substantially zero.

[0008]

According to the present invention, a first instruction to be repeatedly executed and a second instruction stored at an address next to the first instruction and instructing the first instruction to be repeatedly executed are stored. a memory for storing at least a program counter to provide an address signal to said memory, and an instruction register for temporarily storing the contents of said memory to said program counter indicates decodes the output of the instruction register decoder for outputting various control signals A register for temporarily holding the output of the decoder, a counter preset by the second instruction and decrementing the value by one each time the execution of the first instruction is completed, and a register other than the second instruction in the decoder. When decoded, the contents of the program counter are incremented, and the instruction register is fetched of the memory output. Instructing the register to take in the decode output, and when the second instruction of the instruction is decoded by the decoder, incrementing the contents of the program counter is prohibited from the subsequent instruction. Inhibiting the capture of the memory output, instructing the register to inhibit the capture of the decode output thereafter, and writing the number of repetitions indicated by the first instruction to the counter in the execution cycle of the second instruction. When the counter indicates that the value has been decremented by one each time the execution of the first instruction has been completed and the specified number of times has been repeated as a result, the program counter restarts the content increment operation. The instruction register is provided for resuming the operation of taking in the memory output, and the register is provided for receiving the decode output. A program repeat control and control means for instructing the interrupt operation resumes.

[0009]

According to the present invention, after the execution of the first instruction to be repeatedly processed in the memory is started,
In parallel with this, the second instruction for instructing repetitive execution of the first instruction and the repetitive execution control of the first instruction by the control means are performed.

[0010]

Hereinafter, a program repeat control apparatus according to an embodiment of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram of a program repeat control device according to an embodiment of the present invention. As shown in FIG. 2, this device operates with a two-phase clock of φ1 and φ2. In FIG. 1, 1 is a memory for storing an instruction, 2 is a program counter for giving an address signal to the memory 1, and the contents are incremented at the rising of the φ1 clock; 3 is an instruction register for taking in the output of the memory 1 at the rising of the clock φ1 4, a decoder for decoding the output of the instruction register 3; 5, a decoder register for capturing the output of the decoder 4 at the rising edge of the clock φ1;
Reference numeral 6 denotes various control signals output from the decoder register 5, 7
Is a latch that captures a part of the output of the instruction register 3 at the rising edge of the clock φ2, 8 is a repeat counter that uses the output of the latch 7 as an initial value and counts down at the rising edge of the clock φ1, and 9 is that the content of the repeat counter 8 becomes zero. A zero detection signal which becomes "1" when the decoder 4 decodes a later-described repeat counter set instruction 32, an instruction detection signal which becomes "1", and a zero detection signal 9 and an instruction detection signal 10 are input. The internal state is changed at the rise of the clock φ2, and a preset signal 12 and a count permission signal 13 described later are supplied to the counter 8 and a gate 16 described later.
A repeat control unit for outputting a later-described update prohibition signal 14 to a later-described gate 17 and a later-described decoder register update prohibition signal 15 to a later-described gate 17.
Is a preset signal for instructing to take in the output at the rising edge of the clock φ1.
A count enable signal instructing that countdown is performed at the rising edge of the clock φ1, an update inhibit signal 14 for inhibiting the program counter 2 and the instruction register 3 from updating the contents, and a 15 for the decoder register 5 updating the contents. A decoder register update inhibition signal 16 to be inhibited is logically ANDed with the update inhibition signal 14 and the clock φ1, and the result is written to the program counter 2 and the instruction register 3.
Is a gate which takes the logical product of the decoder register update inhibit signal 15 and the clock φ1 and outputs the result to the decoder register 5.

FIG. 3 shows the contents of the memory 1. An instruction A31 to be repeatedly executed is stored at address n.
However, at the address n + 1, a repeat counter set instruction 32 for instructing the execution of the instruction at the address n repeatedly is given by n + 2, n +
At address 3, an instruction B33 and an instruction C34, which are executed once each, are stored.

FIG. 4 shows a change in the internal state of the repeat control unit 11. The repeat control unit 11 has three internal states: a wait state 41, a repeat counter set state 42 , and a repeat counter countdown state 43. Waiting state 41 to repeat counter setting state 42
Is performed at the clock φ2 when the instruction detection signal 10 indicating that the decoder 4 has detected the repeat counter set instruction 32 is “1”. The transition from the repeat counter set state 42 to the repeat counter countdown set state 43 is performed unconditionally by the clock φ2. The transition from the repeat counter countdown set state 43 to the wait state 41 is performed by the clock φ2 when the zero detection signal 9 indicating that the content of the repeat counter 8 is zero is “1”. In each state, the output signal of the repeat control unit 11 is as shown in FIG.

FIG. 6 shows the state of each element constituting the program repeat apparatus shown in FIG. 1 and the operation of each signal. FIG. 6 shows cycle numbers used in the following description, and each cycle is represented by φ1, φ2 as shown in FIG.
2 clocks.

The program repeat control device configured as described above will be described below with reference to FIGS. 1 and 3, FIGS.
The operation will be described with reference to FIG. 6 based on the cycle numbers shown in FIG. (1) Cycle number = 1 Program counter 2: incremented by clock φ1 and the content becomes n. Memory 1: Access at address n. (2) Cycle number = 2 Program counter 2: incremented by clock φ1 and the content becomes n + 1. • Memory 1: Access address n + 1. Instruction register 3: At clock φ1, fetches instruction A31, which is the content of address n accessed in the previous cycle. Decoder 4: Decodes instruction A31. (3) Cycle number = 3 Program counter 2: incremented by clock φ1 and the content becomes n + 2. • Memory 1: Access to address n + 2. Instruction register 3: At clock φ1, fetches a repeat counter set instruction 32, which is the content of address n + 1 accessed in the previous cycle. Decoder 4: As a result of decoding the repeat counter set instruction 32, the instruction detection signal 10 is set to "1". Decoder register 5: The decoding result of instruction A31 decoded by decoder 4 in the previous cycle is taken in by clock φ1. As a result, some of the various control signals 6 become active, and the instruction A31 is executed. -Repeat control unit 11: Since the instruction detection signal 10 becomes "1", the internal state changes from the waiting state 41 to the repeat counter set state 42 at the clock φ2. As a result, the output of the repeat control unit is as shown in the repeat counter set state in FIG. Latch 7: A portion indicating the number of repeats from the repeat counter set instruction 32 stored in the instruction register 3 is fetched by the clock φ2. (4) Cycle number = 4 Program counter 2: incremented by clock φ1 and the content becomes n + 3. • Memory 1: Access to address n + 3. Instruction register 3: At clock φ1, fetches instruction B33, which is the content of address n + 2 accessed in the previous cycle. Decoder 4: Decodes instruction B33. Decoder register 5: The clock φ1 is blocked by the gate 17 because the decoder register update inhibit signal 15 is "1". Therefore, the contents of the decoder register 5 maintain the state of the previous cycle, that is, the result of decoding the instruction A31. Therefore, the instruction A31 is executed following the previous cycle. -Repeat counter 8: Since the preset signal 12 is "1", the value 3 held by the latch 7 is taken in at the clock φ1. Repeat controller 11: The internal state changes from repeat counter set state 41 to repeat counter countdown state 43 at clock φ2. As a result, the output of the repeat control unit is as shown in the repeat counter countdown state in FIG. (4) Cycle number = 5-6 Program counter 2: The clock φ1 is blocked by the gate 16 because the update inhibit signal 14 is “1”.
Therefore, the content of the program counter 2 does not change and keeps n + 3. • Memory 1: Access to address n + 3. Instruction register 3: The clock φ1 is blocked by the gate 16 because the update inhibit signal 14 is "1". Therefore, the contents of the instruction register 3 do not change and the instruction B33 is maintained. Decoder 4: Decodes instruction B33. Decoder register 5: The clock φ1 is blocked by the gate 17 because the decoder register update inhibit signal 15 is "1". Therefore, the contents of the decoder register 5 maintain the state of the previous cycle, that is, the result of decoding the instruction A31. Therefore, the instruction A31 is executed following the previous cycle. -Repeat counter 8: Count enable signal 13 is "1"
Therefore, the countdown is performed by the clock φ1. -Repeat control unit 11: Since the zero detection signal 9 indicating that the content of the repeat counter 8 has become zero is "0", there is no change in the internal state. Therefore, the output becomes the same as the state of the previous cycle. (5) Cycle number = 7 Program counter 2: Since the update inhibit signal 14 is "1", the gate 16 blocks the clock φ1.
Therefore, the content of the program counter 2 does not change and keeps n + 3. • Memory 1: Access to address n + 3. Instruction register 3: The clock φ1 is blocked by the gate 16 because the update inhibit signal 14 is "1". Therefore, the contents of the instruction register 3 do not change and the instruction B33 is maintained. Decoder 4: Decodes instruction B33. Decoder register 5: The clock φ1 is blocked by the gate 17 because the decoder register update inhibit signal 15 is "1". Therefore, the contents of the decoder register 5 maintain the state of the previous cycle, that is, the result of decoding the instruction A31. Therefore, the instruction A31 is executed following the previous cycle. -Repeat counter 8: Count enable signal 13 is "1"
Therefore, the countdown is performed by the clock φ1,
This time, the result is zero, so the zero detection signal 9
The repeat control unit 11: Since the zero detection signal 9 is "1", the internal state changes to the waiting state 41 at the clock φ2.
Therefore, the output is as shown in the wait state of FIG. (6) Cycle number = 8 Program counter 2: Count-up is restarted because update inhibit signal 14 has become "0". Therefore, the content of the program counter 2 becomes n + 4. • Memory 1: Access to address n + 4. -Instruction register 3: Since the update prohibition signal 14 has become "0", the capture of the output of the instruction register 3 at the clock φ1 of the memory 1 is resumed. The result is an instruction C34. Decoder register 5: Since the decoder register update inhibit signal 15 has become "0", the capture of the output of the decoder 4 into the decoder register 5 is resumed, and as a result, the content becomes the decoding result of the instruction B33. , The instruction B33 is executed ・ Repeat counter 8: No operation is performed because all control signals to the repeat counter 8 are “0” ・ Repeat control section 11: The instruction detection signal 10 is “1” 5, the wait state shown in FIG. 5 is maintained. (7) Cycle number = 9 Program counter 2: Program counter at clock φ1 The counter is incremented and the content becomes n + 5 Memory 1: Access address n + 5 Instruction register 3: Capture output of memory 1 at clock φ1 Decoder 4: Decode output of instruction register 3 Decoder register 5: Captures the decoding result of instruction C34, which is the output of decoder 4, at clock φ1, so that instruction C34 is executed.

As described above, according to the present embodiment, the memory 1
Is a repeat counter set instruction 32 which is a repeat processing control instruction after an instruction A31 to be a repeat processing target.
And the decoder register 5, the repeat counter 8, the instruction detection signal 10, the repeat control unit 11, the gates 16 and 1,
7, the execution of the instruction A31 and the execution of the repeat counter set instruction 32 are performed in parallel.
The execution of the repeat counter set instruction 32 can be made substantially 0 cycles.

In this embodiment, the number of repeats is included in the repeat counter set instruction 32, but may be given from a register (not shown).

[0018]

As described above, according to the present invention, a repeat counter set instruction, which is a repeat processing control instruction, is placed after a repeat processing instruction in a memory, and a decoder register, a repeat counter, and a repeat control unit are provided. The execution of the instruction and the execution of the repeat counter set instruction are performed in parallel, and the execution of the repeat counter set instruction can be performed substantially in zero cycles.

[Brief description of the drawings]

FIG. 1 is a block diagram of a program repeat processing device according to an embodiment of the present invention.

FIG. 2 is a diagram showing a clock used in the embodiment.

FIG. 3 is a diagram showing contents of a memory 1 in the embodiment.

FIG. 4 is a diagram showing an internal state transition of a repeat control unit 11 in the embodiment.

FIG. 5 is a diagram showing an output of a repeat control unit 11 in the embodiment.

FIG. 6 is a diagram showing an instruction execution process for explaining the operation in the embodiment.

FIG. 7 is a block diagram of a conventional program repeat processing device.

FIG. 8 is a diagram showing contents of a memory 72 in the conventional example.

FIG. 9 is a view showing an instruction execution process for explaining the operation in the conventional example.

[Explanation of symbols]

 1 Memory 2 Program Counter 3 Instruction Register 4 Decoder 5 Decoder Register 8 Repeat Counter 11 Repeat Control Unit 16 Gate 17 Gate

Claims (2)

(57) [Claims] An instruction fetch stage, a decode stage, and an execution stage are pipelined, and as a result of instruction decoding in a decode stage in a cycle n, the instruction instructs m-time repetition execution of an instruction currently in an execution stage. In the execution stage after the cycle n + 1, a program repeat control method in which the processing executed in the execution stage of the cycle n is repeated m times. 2. A memory for storing at least a first instruction to be repeatedly executed and a second instruction stored at an address next to the first instruction and instructing the first instruction to be repeatedly executed, A program counter for providing an address signal to a memory, an instruction register for temporarily storing the contents of the memory indicated by the program counter, a decoder for decoding the output of the instruction register and outputting various control signals, and an output of the decoder A temporary holding register, a counter preset by the second instruction and decrementing its value by one each time the first instruction is executed, and a counter for decoding other than the second instruction by the decoder. The program counter is incremented, the instruction register is fetched the memory output, and the register is When the second instruction is decoded by the decoder, the content counter is prohibited from incrementing the program counter and the instruction register is prohibited from capturing the memory output. The register is instructed to prohibit the subsequent capture of the decoded output, and in the execution cycle of the second instruction, the counter is instructed to write the number of repetitions indicated by the first instruction to the counter. Each time the execution of the first instruction is completed, its value is set to 1
When the result indicates that repetition of the specified number of times has been performed, the program counter restarts the content increment operation, the instruction register restarts the memory output capture operation, and the register stores the memory output capture operation. Control means for instructing restart of the operation of taking in the decoded output.