JP2833581B2 - Method for manufacturing semiconductor device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a method for manufacturing a semiconductor device, and more particularly to a method for manufacturing an element isolation region in a semiconductor device.

[0002]

2. Description of the Related Art An element isolation region of a semiconductor device including a MOS transistor of a reverse conductivity type formed on a silicon substrate of one conductivity type is usually formed by selective oxidation (LOCO).
A field oxide film formed on the surface of the silicon substrate by S) and a channel stopper layer of one conductivity type provided on the silicon substrate in contact with the bottom surface of the field oxide film. In the case of a semiconductor device including a MOS transistor of a reverse conductivity type channel, a first problem relating to an element isolation region accompanying miniaturization of a semiconductor element is the manifestation of a narrow-channel effect. . This is because when the one-conductivity-type channel stopper layer is in contact with the entire bottom surface of the field oxide film, the MOS transistor of the opposite-conductivity-type channel (the silicon substrate immediately below the gate electrode sandwiched between the opposite-conductivity-type source / drain regions) Field oxide film in the channel region (consisting of the surface)
This is because the effective one-conductivity-type impurity concentration in the vicinity of a beak (birds'-peak) increases, and the absolute value of the threshold voltage of this MOS transistor effectively increases. A second problem related to an element isolation region accompanying miniaturization of a semiconductor element is an increase in junction leakage due to stress remaining in (near a bird's beak) a field oxide film formed in a narrow portion. .

As a method for reducing such a narrow channel effect, after forming a field oxide film, ions of one conductivity type are implanted, and a MOS of a reverse conductivity type is formed.
There is a method of forming a one-conductivity type channel stopper layer on a silicon substrate at a distance from a channel region of a transistor and on a bottom surface of a field oxide film. For example, JP-A-3-
The "second invention of claims" described in Japanese Patent No. 177045 aims to simultaneously solve the problem relating to the narrow channel effect and the problem relating to the residual stress. The method of manufacturing a semiconductor device according to the "second invention of the claims" described in the above publication is as follows. First, a first silicon nitride film is formed on a semiconductor substrate, a layer made of a material having a lower rigidity is formed on the first silicon nitride film, and a second silicon nitride film is formed on this layer. To form Next, a field oxide film was formed on the surface of the semiconductor substrate by thermal oxidation using the laminated film composed of the second silicon nitride film, the above-mentioned layer and the first silicon nitride film as a mask, and this laminated film was used as a mask. A channel stopper layer is formed by ion implantation.

[0004]

SUMMARY OF THE INVENTION The above-mentioned Japanese Patent Application Laid-Open No. 3-177 is disclosed.
According to the method of manufacturing a semiconductor device according to the second aspect of the invention described in Japanese Patent No. 045, the channel stopper layer hardly comes into contact with the surface of the semiconductor substrate even near the bird's beak of the field oxide film. Certainly, the local increase in the impurity concentration of one conductivity type on the surface of the semiconductor substrate near the bird's beak is suppressed. However, Japanese Patent Application Laid-Open No. Hei.
In the detailed description of the present invention, there is no specific description for application to a semiconductor device.

Referring to FIG. 6, which is a schematic cross-sectional view of a manufacturing process of a semiconductor device, the invention of the first embodiment disclosed in the above-mentioned Japanese Patent Application Laid-Open No. Hei 3-177045 (hereinafter referred to as a first prior art). The outline is as follows.

First, for example, a first silicon oxide film 411 covering the surface of a P-type silicon substrate 401 is formed, and a polycrystalline silicon film 412 covering the surface of the first silicon oxide film 411 is formed. Subsequently, a first silicon nitride film 421 covering the surface of the polycrystalline silicon film 412 is formed, and a second silicon oxide film 431 covering the surface of the first silicon nitride film 421 is formed. Further, a second silicon nitride film 441 is formed to cover the surface of the second silicon oxide film 431 (FIG. 6A).

Next, using a photoresist pattern (not shown) as a mask, a second silicon nitride film 441,
Anisotropic etching is sequentially performed on second silicon oxide film 431 and first silicon nitride film 421 to form openings 461 a and 461 reaching polycrystalline silicon film 412.
b and the like are formed. Here, the opening width of the opening 461b is wider than the opening width of the opening 461a (although it is not specified in the above publication) (FIG. 6).
(B)].

Next, the photo resist film pattern is removed. A field oxide film is formed by selective oxidation using a stacked film including the second silicon nitride film 441, the second silicon oxide film 431, and the first silicon nitride film 421 as a mask, and the polycrystalline silicon film 412a is left. You. Here (although not explicitly stated in the above publication), the thickness of the field oxide film 402a immediately below the opening 461a is equal to the thickness of the field oxide film 402b immediately below the opening 461b. It is thinner [FIG. 6 (c)].

Subsequently, ion implantation of a P-type impurity is performed by using the above-mentioned laminated film as a mask, and a field oxide film 402 is formed.
P-type ion implanted layers 462a and 462a
2b is formed [FIG. 6 (d)].

According to the first prior art, a silicon nitride film having a thickness required as an oxidation-resistant mask at the time of selective oxidation is divided into a silicon nitride film 421 and a silicon nitride film 441. By interposing a silicon oxide film 431 having a lower rigidity than the silicon nitride film between 421 and 441, residual stress in the vicinity of the bird's beak of the field oxide films 402a and 402b is reduced. The field oxide films 402a, 402b and P
In order for the type ion implantation layers 462a and 462b to function as element isolation regions of an actual device, after they are formed,
It is necessary that a semiconductor element be formed without hindrance. However, in the first conventional technique, it is difficult to remove the laminated film used as the oxidation-resistant mask. That is, although it is possible to selectively remove the silicon nitride film 441 after forming the P-type ion-implanted layers 462a and 462b, the thickness of the field oxide films 402a and 402b is reduced (or the amount of reduction is suppressed). ), It is difficult to remove the silicon oxide film 431.

In contrast to the first prior art, the "invention of the second embodiment" of Japanese Patent Laid-Open Publication No. Hei 3-177045 discloses that an opening is formed in a laminated film similarly to the first prior art. Is formed, a spacer made of a third silicon nitride film is formed on the side surface of the opening. In this state, it is difficult to remove the laminated film used as the oxidation-resistant mask in the "invention of the second embodiment" as in the first prior art. In the detailed description of Japanese Patent Application Laid-Open No. H3-177045, the application of "the invention of the second embodiment" includes, as an application of silicon oxide between a first silicon nitride film and a second silicon nitride film. There is a suggestion that a polycrystalline silicon film may be interposed instead of interposing a film (hereinafter, this is referred to as a second conventional technique).

Referring to FIGS. 7 and 8 which are schematic cross-sectional views of a manufacturing process of a semiconductor device, a semiconductor device based on the second conventional technique is formed as follows.

First, for example, a silicon oxide film 511 covering the surface of a P-type silicon substrate 501 is formed, and the first polycrystalline silicon film 5 covering the surface of the silicon oxide film 511 is formed.
12 are formed. Subsequently, a first silicon nitride film 521 covering the surface of the first polycrystalline silicon film 512 is formed, and a second polycrystalline silicon film 533 covering the surface of the first silicon nitride film 521 is formed. You. further,
A second silicon nitride film 541 is formed to cover the surface of the second polycrystalline silicon film 533 (FIG. 7A).

Next, using a photoresist pattern (not shown) as a mask, a second silicon nitride film 541,
Anisotropic etching is sequentially performed on second polycrystalline silicon film 533 and first silicon nitride film 521, and
Opening 561 reaching first polycrystalline silicon film 512
a, 561b and the like are formed. The opening width of the opening 561b is wider than the opening width of the opening 561a [FIG.
(B)].

Next, the photo resist film pattern is removed. A third silicon nitride film 552 is formed on the entire surface [FIG. 7 (c)]. This third silicon nitride film 55
2 is etched back by anisotropic etching to form a silicon nitride film spacer 553 covering the side surfaces of the openings 561a and 561b (FIG. 7D).

Next, the silicon nitride film spacer 553, the second silicon nitride film 541, the second polycrystalline silicon film 5
A field oxide film is formed by selective oxidation using the stacked film including the first silicon nitride film 33 and the first silicon nitride film 521 as a mask, and the polycrystalline silicon film 512a is left. The thickness of the field oxide film 502a immediately below the opening 561a is smaller than the thickness of the field oxide film 502b immediately below the opening 561b. Subsequently, ion implantation of a P-type impurity is performed using the laminated film as a mask, and the P-type impurities connected to the field oxide films 502a and 502b are implanted.
Type ion implantation layers 562a and 562b are formed on a P type silicon substrate 501 (FIG. 8A).

Next, the silicon nitride film 541 is removed by anisotropic etching, and a silicon nitride film spacer 553 is formed.
a is left [FIG. 8 (b)]. Next, second polycrystalline silicon film 533 is selectively removed. Subsequently, the silicon nitride film spacer 553a and the first silicon nitride film 521 are selectively removed by hot phosphoric acid. Furthermore, the first
Of polycrystalline silicon film 512a is selectively removed.

Next, second ion implantation of P-type impurities, heat treatment, and the like are performed. By these series of processes, the above P
Type ion implantation layers 562a and 562b are activated and converted into P-type channel stopper layers 503a and 503b,
At the same time, a channel doped layer 504 is formed [FIG.
(C)].

Next, the silicon oxide film 511 is removed. A gate oxide film 505 is formed by thermal oxidation, and a gate electrode 506 is formed. Further, N-type source / drain regions 507 are formed by ion implantation of N-type impurities or the like, and the semiconductor device is completed (FIG. 8D).

According to the second conventional technique, the first
Unlike the prior art, a stacked film composed of the second silicon nitride film 541, the second polycrystalline silicon film 533, and the first silicon nitride film 521 (and the silicon nitride film spacer 553) used for the oxidation resistant mask is different from the conventional technology. Removal is easy. However, the polycrystalline silicon film has a higher Young's rule than the silicon oxide film (and the silicon nitride film).
It is difficult to reduce the residual stress in the vicinity of the bird's beak of the field oxide films 502a and 502b.

Accordingly, an object of the present invention is to form a silicon nitride film on a silicon substrate and thereafter form a layer made of a material having a lower rigidity on at least the silicon nitride film, and to include these films. Forming a field oxide film on the silicon substrate surface by thermal oxidation using the laminated film as a mask, and forming a channel stopper layer in contact with the bottom surface of the field oxide film by ion implantation using the laminated film as a mask; SUMMARY OF THE INVENTION It is an object of the present invention to provide a method of manufacturing a semiconductor device including a semiconductor device including a field oxide film in which a stress in the vicinity of a bird's beak is easily relieved and the removal of the stacked film is facilitated.

[0022]

According to a first aspect of the method of manufacturing a semiconductor device of the present invention, a first silicon oxide film covering a surface of a one conductivity type silicon substrate is formed and has a first thickness. Forming a silicon nitride film covering the surface of the first silicon oxide film, and forming a second silicon oxide film having a second thickness and covering the surface of the silicon nitride film; Forming a photo-resist film pattern that selectively covers the surface of the second silicon oxide film on a region where an element isolation region is to be formed on the surface of the one conductivity type silicon substrate; and using the photo-resist film pattern as a mask At least the second silicon oxide film is anisotropically etched with a mixed gas of trifluoromethane and tetrafluoromethane, and then anisotropically etched with a mixed gas of difluoromethane and carbon dioxide. Anisotropically etching the silicon nitride film to form a first opening having a first opening width reaching the first silicon oxide film through the second silicon oxide film and the silicon nitride film; Forming at least a second opening having a second opening width wider than the first opening width, removing the photoresist film pattern, and forming the second silicon oxide film and the silicon nitride film. By selective oxidation using a mask as a mask, the surface of the one-conductivity-type silicon substrate immediately below the first opening and the second opening is provided with a sum of the first film thickness and the second film thickness. A field oxide film having a thin third film thickness portion and a fourth film thickness portion larger than the third film thickness and smaller than the sum of the first film thickness and the second film thickness. Forming and forming the field oxide film The entire surface subjected to the field oxide film and the first ion implantation of one conductivity type impurity of the first implant energy is the projected range in the vicinity of the interface of the one conductivity type silicon substrate portion of the thickness of,
Further, at least the fourth thickness of the field oxide film has a projection range near the interface between the field oxide film and the one conductivity type silicon substrate, and the second impurity of the one conductivity type by the second implantation energy. The first and second one-conductivity type ion implantation layers are respectively brought into contact with the third film thickness portion and the fourth film thickness portion in contact with the bottom surface of the field oxide film. Forming on the one-conductivity-type silicon substrate, selectively removing the second silicon oxide film by CMP and selectively removing the silicon nitride film by hot phosphoric acid, Forming a channel-doped layer in a region where an element forming region is to be formed on the surface of the one-conductivity-type silicon substrate by third ion implantation, and removing the first silicon oxide film Forming a gate insulating film in a region where the device forming region is to be formed, forming a gate electrode, and performing fourth ion implantation of a reverse conductivity type impurity using the field oxide film and the gate electrode as a mask. Forming a source / drain region of the opposite conductivity type in the region where the formation region is to be formed. Preferably, the formation of the first and second one conductivity type ion implantation layers includes oblique rotation ion implantation of one conductivity type impurity.
More preferably, the implantation angle in the oblique rotation ion implantation is defined by the second opening.

According to a second aspect of the method of manufacturing a semiconductor device of the present invention, a silicon oxide film is formed to cover the surface of a one conductivity type silicon substrate, and the surface of the silicon oxide film having a first thickness is formed. Forming a first silicon nitride film to cover the surface of the first silicon nitride film with a second thickness;
Forming an insulating film made of a G film or a BPSG film;
Forming a second silicon nitride film covering the surface of the insulating film with a film thickness of: and forming the second silicon nitride film on a region where a device isolation region is to be formed on the surface of the one conductivity type silicon substrate Forming a photoresist film pattern that selectively covers the surface of the silicon nitride film; anisotropically etching the second silicon nitride film using the photoresist film pattern as a mask to form trifluoromethane and tetrafluoromethane; Anisotropically etching at least the insulating film with a mixed gas of fluoromethane and anisotropically etching the first silicon nitride film with a mixed gas of difluoromethane and carbon dioxide; A first opening having a first opening width reaching the silicon oxide film through the second silicon nitride film, the insulating film and the first silicon nitride film; Forming at least a second opening having a second opening width larger than the opening width; removing the photoresist film pattern; forming a third silicon nitride film on the entire surface; Forming a silicon nitride film spacer on the side surfaces of the first and second openings by performing an etch-back by anisotropic etching on the silicon nitride film; The selective oxidation using the silicon nitride film and the silicon nitride film spacer as masks forms the first film thickness on the surface of the one conductivity type silicon substrate immediately below the first opening and the second opening. , A second film thickness, a portion having a fourth film thickness smaller than the sum of the third film thickness, and a first film thickness, a second film thickness, and a third film thickness larger than the fourth film thickness. Fifth film thickness portion smaller than the sum of film thicknesses Forming a field oxide film having: a first range having a projection range near an interface between the field oxide film and the one conductivity type silicon substrate in a portion of the field oxide film having the fourth thickness. A first ion implantation of one-conductivity-type impurity is performed over the entire surface by implantation energy, and at least a portion of the fifth-layer thickness of the field oxide film near the interface between the field oxide film and the one-conductivity-type silicon substrate. A second ion implantation of one-conductivity-type impurity is performed over the entire surface by a second implantation energy having a projection range, and the field oxide film of the fourth film thickness portion and the fifth film thickness portion is removed. Forming first and second one-conductivity-type ion-implanted layers in contact with the bottom surface on the one-conductivity-type silicon substrate; and mixing di-fluoromethane and carbon dioxide. The third silicon nitride film is selectively removed by anisotropic etching with a gas, the insulating film is selectively removed by gas etching with hydrogen fluoride, and the first silicon nitride film and Selectively removing the silicon nitride film spacer;
Forming a channel-doped layer in a region where a device formation region is to be formed on the surface of the one conductivity type silicon substrate by ion implantation, removing the silicon oxide film, and forming a gate in a region where the device formation region is to be formed. An insulating film is formed, a gate electrode is formed, and the field oxide film and a reverse conductivity type impurity are implanted in a fourth ion implantation using the gate electrode as a mask. Forming source / drain regions. Preferably, the formation of the first and second one conductivity type ion implantation layers includes oblique rotation ion implantation of one conductivity type impurity. More preferably, the implantation angle in the oblique rotation ion implantation is defined by the second opening.

According to a third aspect of the method of manufacturing a semiconductor device of the present invention, a first silicon oxide film covering a surface of a one conductivity type silicon substrate is formed, and the first silicon oxide film having a first thickness is formed. Forming a first silicon nitride film covering the surface of the silicon oxide film, covering the surface of the first silicon nitride film with a second thickness, and forming an insulating film made of a PSG film or a BPSG film; Forming a second silicon nitride film having a third thickness and covering the surface of the insulating film; and forming a second silicon nitride film having a fourth thickness and covering the surface of the second silicon nitride film. Forming a silicon oxide film; and forming a photoresist film pattern that selectively covers a surface of the second silicon oxide film on a region where an element isolation region is to be formed on the surface of the one conductivity type silicon substrate. Using the above photoresist pattern as a mask, The second silicon oxide film and a second
Anisotropically etch the silicon nitride film, and anisotropically etch at least the insulating film with a mixed gas of trifluoromethane and tetrafluoromethane,
The first silicon nitride film is anisotropically etched with a mixed gas of fluoromethane and carbon dioxide to form a second silicon oxide film, a second silicon nitride film,
Penetrating the insulating film and the first silicon nitride film;
Forming at least a first opening having a first opening width reaching the silicon oxide film and a second opening having a second opening width wider than the first opening width; The photo-resist film pattern is removed, a third silicon nitride film is formed on the entire surface, and the third silicon nitride film is etched back by anisotropic etching to form the first and second openings. The step of forming a silicon nitride film spacer on the side surface and the selective oxidation using the second silicon oxide film, the second silicon nitride film, the insulating film, the first silicon nitride film and the silicon nitride film spacer as a mask The first film thickness, the second film thickness, the third film thickness, and the fourth film thickness are provided on the surface of the one conductivity type silicon substrate immediately below the first opening and the second opening. Of the fifth film thickness smaller than the sum of And a sixth film thickness portion which is larger than the fifth film thickness and smaller than the sum of the first film thickness, the second film thickness, the third film thickness, and the fourth film thickness. A step of forming a field oxide film and a first range having a projection range near an interface between the field oxide film and the one-conductivity-type silicon substrate in a portion of the field oxide film having the fifth thickness.
A first ion implantation of one-conductivity-type impurity is performed over the entire surface by the implantation energy of at least a portion of the field oxide film having the sixth film thickness in the vicinity of the interface between the field oxide film and the one-conductivity-type silicon substrate. A second ion implantation of one conductivity type impurity is performed over the entire surface by a second implantation energy having a projection range in the field oxide film of the fifth film thickness portion and the sixth film thickness portion. Forming a first and second one-conductivity-type ion-implanted layers in contact with the bottom surface of the one-conductivity-type silicon substrate, removing the second silicon oxide film, and forming difluoromethane and The second silicon nitride film is selectively removed by anisotropic etching using a mixed gas with carbon oxide, and the insulating film is selectively removed by gas etching using hydrogen fluoride. Selectively removing the first silicon nitride film and the silicon nitride film spacer with hot phosphoric acid, and performing third ion implantation of required conductivity type impurities to form an element formation region on the surface of the one conductivity type silicon substrate. Forming a channel-doped layer in a region to be formed;
The first silicon oxide film is removed, a gate insulating film is formed in a region where the element formation region is to be formed, a gate electrode is formed, and the field oxide film and a reverse conductivity type impurity using these gate electrodes as a mask are formed. Forming source / drain regions of the opposite conductivity type in the regions where these element formation regions are to be formed by the fourth ion implantation. Preferably, the fifth film thickness is sufficiently larger than the fourth film thickness, and the first and second one-conductivity-type ion implantation layers include oblique rotation ion implantation of one-conductivity-type impurities. I have. More preferably, the implantation angle in the oblique rotation ion implantation is defined by the second opening.

[0025]

Next, the present invention will be described with reference to the drawings.

Referring to FIG. 1 which is a schematic cross-sectional view of a manufacturing process of a semiconductor device, one application example of the first embodiment of the present invention is that an N-channel MOS transistor having a design rule of 0.25 μm is used in this embodiment. It is applied to the manufacture of

First, for example, if the impurity concentration is 1 × 10 ¹⁵ cm
The surface of the P-type silicon substrate 101 having a thickness of about ^-3
a first silicon oxide film (pad oxide film) 11 of about nm
1 is formed by thermal oxidation. This silicon oxide film 11
1 is covered with a silicon nitride film 121 having a thickness of about 200 nm by a vapor phase growth method. Further, the surface of the silicon nitride film 121 has a thickness of 40
It is covered with a second silicon oxide film 131 having a thickness of about 0 nm (FIG. 1A). In this embodiment mode, a film thickness obtained by adding an effective film thickness of the silicon oxide film 131 (for example, a silicon oxide film converted to a silicon nitride film) to the film thickness of the silicon nitride film 121 is a series of values described below. It must have an effective film thickness sufficient to function as a mask for boron ion implantation. If the silicon oxide film 131 is not formed and only the thick silicon nitride film is formed (not the laminated structure film), for example, 510 n
A silicon nitride film having a thickness of about m is required, and cracks tend to occur in the silicon nitride film itself during the film formation stage.

Next, a photoresist film pattern (not shown) is formed to cover the surface of the silicon oxide film 131 on a region of the surface of the P-type silicon substrate 101 where an element formation region is to be formed. Using this photo resist film pattern as a mask, anisotropic etching is sequentially performed on silicon oxide film 131 and silicon nitride film 121 to form first opening 161 reaching silicon oxide film 111.
a, the second opening 161b and the like are formed. Opening 16
The first and second opening widths in 1a and 161b are, for example, about 0.3 μm and 0.8 μm.

Here, the anisotropic etching of the silicon oxide film 131 is performed by using trifluoromethane (CHF ₃ ).
Ion etching (RIE) using a mixed gas of methane and tetrafluoromethane (CF ₄ ) is preferable,
Anisotropic etching of the silicon nitride film 121 is
Fluoromethane (CH ₂ F ₂ ) and carbon dioxide (C
RIE using a mixed gas with O ₂ ) is preferred. In RIE using a mixed gas of trifluoromethane and tetrafluoromethane, a silicon oxide film can be selectively etched with respect to a silicon nitride film. RIE using a mixed gas of difluoromethane and carbon dioxide
Then, as described in, for example, Japanese Patent Publication No. Hei 7-118474, the etching rate between the silicon nitride film and the silicon oxide film is about 7: 1. Silicon oxide film 13
1 or switching of etching gas for silicon nitride film 121 or (for silicon oxide film 111)
The setting of the etching end point of the silicon nitride film 121 is performed, for example, by detecting the emission spectrum of cyan ((CN) ₂ ).

Next, the photo resist film pattern is removed. A field oxide film is formed by selective oxidation using a stacked film including the second silicon oxide film 131 and the silicon nitride film 121 as a mask. At this time, as described in, for example, Japanese Patent Application Laid-Open No. 7-66281, when the opening width is smaller than 1 μm, the thickness of the field oxide film is different between the narrow portion and the wide portion.
The film thickness of the field oxide film 102a immediately below the portion 61a and the film thickness of the field oxide film 102b immediately below the opening 161b are about 200 nm and 350 nm, respectively. In the present embodiment, the height of the upper surface of field oxide film 102b is higher than the height of the upper surface of silicon nitride film 121.
It is lower. In the present embodiment, the silicon oxide film 1
Since the field oxide film is formed by using the laminated film including the silicon nitride film 31 and the silicon nitride film 121 as a mask, the field oxide film is formed in comparison with the selective oxidation using only a single-layer silicon nitride film having a thickness of about 510 nm as a mask. The stress in the vicinity of the bird's beak is easily alleviated.

Subsequently, using the above-mentioned laminated film as a mask, for example, 80 keV
Ion implantation of boron of about 1 × 10 ¹³ cm ^-2 and 140
Boron ion implantation with at least two types of implantation energies is performed, such as boron ion implantation at about 1.5 × 10 ¹³ cm ⁻² at keV. As a result, the first boron ion implanted layer 162a and the second boron ion implanted layer 162b that are in contact with the bottom surfaces of the field oxide films 102a and 102b respectively become the P-type silicon substrate 101.
Formed. Since boron ion implantation is performed with at least two kinds of implantation energies as described above, the effective boron concentration of the boron ion implantation layer 162a formed immediately below the thin portion of the field oxide film 102a is better. The boron concentration is higher than the effective boron concentration of the boron ion implantation layer 162b formed immediately below the thick portion of the field oxide film 102b. In order to suppress the narrow channel effect, the field oxide films 102a, 102
In the bird's beak of FIG. 2B, the boron ion implantation layers 162a and 162b
Is formed so as not to contact [FIG. 1 (b)].

The reason why the boron ion implantation is performed as described above is as follows. When boron ion implantation is performed using only the implantation energy corresponding to the thick portion of the field oxide film, a boron ion implantation layer formed in the thin portion of the field oxide film is formed on the bottom surface of the field oxide film. The contact stops (see FIG. 6D). On the other hand, when boron ion implantation is performed only with the implantation energy corresponding to the thin portion of the field oxide film, the boron ion implantation layer formed in the thin portion of the field oxide film becomes thin. It is formed only near the bird's beak (see FIG. 8A).

If the field oxide film 102b is sufficiently thicker than the field oxide film 102a, the field oxide film (particularly, the field oxide
In the bird's beak portion b), the difference in depth between the upper end portion of the boron ion implanted layer (particularly, the boron ion implanted layer 162b) and the bottom surface of the first silicon oxide film 111 is increased, and especially the MOS transistor In some cases, it is not easy to suppress the parasitic MOS transistor effect (at the end of the channel region). In such a case, it is preferable to add an oblique rotation ion implantation of boron. Further, it is preferable that the implantation angle and the implantation energy are defined by the aspect ratio of the second opening 161b and the thickness of the field oxide film 102b.

Next, the silicon oxide film 131 is removed by chemical mechanical polishing (CMP) (FIG. 1C). The removal of the silicon oxide film 131 utilizes the fact that the height of the upper surface of the field oxide film 102b is lower than the height of the upper surface of the silicon nitride film 121 and the difference between the rotational loads of the silicon oxide film and the silicon nitride film in CMP. doing.
As described above, in the present embodiment, the field oxide film 102
It is easy to substantially selectively remove the silicon oxide film 121 without reducing the film thicknesses of a and 102b. Note that in this embodiment, it is not preferable to use a PSG film or a BPSG film instead of the silicon oxide film 131. This is because the PSG film or BPS
This is to prevent a change in the impurity concentration of the P-type silicon substrate 101 near the bottom surfaces of the field oxide films 102a and 102b due to outward diffusion of phosphorus (or boron and phosphorus) from the G film.

Next, the silicon nitride film 121 is selectively removed by wet etching using hot phosphoric acid.
For example, boron ions of about 3 × 10 ¹² cm ⁻² are implanted at 30 keV, and a third boron ion implantation layer (not shown) is formed on the surface of the P-type silicon substrate 101 immediately below the silicon oxide film 111. You. For example, the silicon oxide film 11 is formed by wet etching with buffered hydrofluoric acid.
After 1 is removed, a sacrificial oxide film (not shown) is formed on the exposed surface of the P-type silicon substrate 101. In this process, the first boron ion implantation layer 162a, the second boron ion implantation layer 162b, and the third boron ion implantation layer 162b are formed.
The ion-implanted layers are respectively activated to become the first P-type channel stopper layer 103a, the second P-type channel stopper layer 103b, and the channel dope layer 104 (FIG. 1D). Channel dope layer 104 has a depth of less than 0.1 μm.

After the sacrificial oxide film is removed by wet etching using buffered hydrofluoric acid or the like, the gate oxide film 105 having a thickness of, for example, about 8.5 nm is thermally oxidized.
Is formed on the surface of the P-type silicon substrate 101 in a region where an element formation region is to be formed. Gate electrode 106
Is formed, an N-type source / drain region 107 having a junction depth of about 0.1 μm is formed by ion implantation of arsenic using the gate electrode 106 and the field oxide films 102a and 102b as a mask. The semiconductor device according to the present embodiment is completed [FIG. 1 (e)].

In the first conventional technique (the same applies to the second conventional technique), unlike the present embodiment, the first conventional technique is provided between the silicon oxide film 411 and the silicon nitride film 421. The polycrystalline silicon film 412 is also involved in the selective oxidation. In this connection, problems inherent in the first conventional technique (as well as the second conventional technique) arise. A first inherent problem is a decrease in junction breakdown voltage of the N-type source / drain region 407 (increase in junction leakage accompanying this) and a decrease in electrostatic breakdown resistance. This is because the bird's beak ends of the field oxide films 402a and 402b are jagged reflecting the grains of the polycrystalline silicon film 412, and thus the end of the N-type source / drain region 407 on the field oxide film side is jagged. Because it becomes. The second inherent problem is that the field oxide film 40
This is a reduction in the function of suppressing the parasitic MOS transistor effect (function as an element isolation region) in a narrow portion like 2a. This is because the oxidized thickness of the surface of the P-type silicon substrate 401 is particularly small in a narrow portion due to the presence of the polycrystalline silicon film 412, and the field oxide film 40
The thickness at which the bottom surface of 2a cuts into the P-type silicon substrate 401 is reduced. Therefore, it is difficult to suppress the lateral diffusion of the N-type source / drain region 407 at the end of the field oxide film 402a.
The punch-through resistance of the N-type source / drain regions 407 of two N-channel MOS transistors adjacent to each other via the gate electrode 02a is reduced.

On the other hand, the berth beak ends of the field oxide films 102a and 102b according to the present embodiment are not jagged. Further, the field oxide film 1
The depth of the bottom of 02a (about 160 nm) can be made deeper than the junction depth of the N-type source / drain region 107. For these reasons, in the present embodiment, there is no problem peculiar to the first conventional technique (and the second conventional technique).

One application example of the first embodiment relates to an N-channel MOS transistor. However, the application of this embodiment is not limited to this, and can be applied to a P-channel MOS transistor. . The various numerical values and the like of the application example of the first embodiment are not limited to the values and the like described above.

Referring to FIGS. 2 and 3 which are schematic cross-sectional views of a manufacturing process of a semiconductor device, an application example of the second embodiment of the present invention also shows that the present embodiment has an N value of 0.25 μm design rule. This is applied to the manufacture of a channel MOS transistor, and is as follows.

First, for example, if the impurity concentration is 1 × 10 ¹⁵ cm
The surface of the P-type silicon substrate 201 having a thickness of about ^-3
A silicon oxide film (pad oxide film) 211 of about nm is formed by thermal oxidation. The surface of the silicon oxide film 211 is covered with a first silicon nitride film 221 having a thickness of about 100 nm by a vapor growth method. The surface of the silicon nitride film 221 is covered with a PSG film 232 having a thickness of about 400 nm by a vapor growth method. Furthermore, this PS
The surface of the G film 232 is covered with a second silicon nitride film 241 having a thickness of about 120 nm (FIG. 2A). In the present embodiment, the silicon nitride film 221, the PSG film 2
32 and the effective film thickness of the silicon nitride film 241 are sufficient to function as a mask for a series of boron ion implantations for forming a P-type channel stopper layer. It is necessary to be. Also,
In the present embodiment and the embodiment, BP is used instead of the PSG film 232.
Although an SG film may be used, it is not preferable to use a silicon oxide film instead of the PSG film 232 for the same reason as described in the first related art.

Next, a photoresist film pattern (not shown) is formed to cover the surface of the silicon nitride film 241 on the region of the surface of the P-type silicon substrate 201 where the element formation region is to be formed. Using this photo resist film pattern as a mask, the silicon nitride film 241 and the PSG film 2
32 and the silicon nitride film 221 are sequentially anisotropically etched to form a first opening 261a, a second opening 261b and the like reaching the silicon oxide film 211. The first and second opening widths of the openings 261a and 261b are, for example, 0.3 μm and 0.8 μm. Similarly to the first embodiment, the anisotropic etching of the PSG film 232 is preferably performed by RIE using a mixed gas of trifluoromethane and tetrafluoromethane.
Anisotropic etching of the silicon nitride film 221 is also performed
RI using mixed gas of fluoromethane and carbon dioxide
E is preferred.

Next, the photo resist film pattern is removed. A third silicon nitride film 252 having a thickness of about 50 nm is formed on the entire surface by low pressure vapor deposition (LPCVD) (FIG. 2B). This LPCVD is performed at a little less than 800 ° C. using ammonia (NH ₃ ) and monosilane (SiH ₄ ) as source gases. Silicon nitride film 25
2 is formed by LPCVD because the silicon nitride film 252 formed by this method has excellent step coverage in the openings 261a and 261b.

Next, the silicon nitride film 252 is etched back by a mixed gas of difluoromethane and carbon dioxide, leaving a silicon nitride film spacer 253 covering the side surfaces of the openings 261a and 261b. [Figure 2
(C)]. The thickness of the second silicon nitride film 241 is
It is preferable that the thickness is larger than the thickness of the silicon nitride film 252. In such a case, the third silicon nitride film 252
In the above-described etch back, the positions of the upper ends of the silicon nitride film spacers 253 are changed to the openings 261a and 261.
b, it is easy to stay on the side surface of the silicon nitride film 241, and the side surfaces of these openings 261 a and 261 b
Avoidance of exposure of the SG film 232 is facilitated.

Next, the second silicon nitride film 241, PS
A laminated film composed of the G film 232 and the first silicon nitride film 121 and the openings 261a and 26 provided in the laminated film
A field oxide film is formed by selective oxidation using the silicon nitride film spacer 253 covering the side surface of 1b as a mask. The thickness of the field oxide film 202a immediately below the opening 261a and the thickness of the field oxide film 202b immediately below the opening 261b are 200 nm and 350 nm, respectively.
About. As described above, in this embodiment, the oxidation-resistant mask is formed of the three-layered laminated film and the silicon nitride film spacer 25.
3, the stress in the vicinity of the bird's beak of the field oxide film can be alleviated more easily than in the first embodiment. Further, since the PSG film 232, which is an intermediate layer of the three-layer structure, is covered with the silicon nitride films 221 and 241 and the silicon nitride film spacer 253, the PSG film during selective oxidation is formed.
Outward diffusion of phosphorus (conductive impurity) from the film 232 is suppressed.

Subsequently, using the laminated film and the silicon nitride film spacer 253 as a mask, the P-type silicon substrate 20 is formed.
Perpendicular to the surface of 1, for example, 1 × 10 ¹³ cm at 80 keV
Ion implantation of about ^-2 boron and 1.5 × at 140 keV
Boron ion implantation is performed using at least two types of implantation energies, such as boron ion implantation of about 10 ¹³ cm ⁻² . Thereby, the field oxide film 20
A first boron ion implantation layer 262a and a second boron ion implantation layer 262b contacting the bottom surfaces of 2a and 202b, respectively, are formed on the P-type silicon substrate 201. In order to suppress the narrow channel effect, the field oxide film 2
02a and 202b, Bird's Beak
The ion implantation layers 262a and 262b are formed so as not to contact the silicon oxide film 211, respectively (FIG. 2D). Similarly to the first embodiment, also in the present embodiment, when the thickness of the field oxide film 202b is sufficiently larger than the thickness of the field oxide film 202a, oblique rotation ion implantation of boron is added. Is preferred. Further, the implantation angle and the implantation energy depend on the aspect ratio of the second opening 261b and the field oxide film 20.
It is preferable that the thickness be defined by the thickness 2b.

Next, the silicon nitride film 241 is removed by RIE using a mixed gas of difluoromethane and carbon dioxide. By this RIE (the silicon nitride film spacer 253 is also etched), the silicon nitride film spacer 253 becomes a silicon nitride film spacer 253a (FIG. 3A).

Next, the PSG film 232 is selectively removed by gas etching using hydrogen fluoride (HF).
This gas etching is performed at a pressure of about 130 Pa at room temperature. The etching rate of the silicon oxide film in this gas etching is the same as that of the PSG film (or B
This is a value lower than 10 ⁻³ of the etching rate of the PSG film (FIG. 3B). In the present embodiment, since the silicon nitride film spacer 253a is present, it is not preferable to selectively remove the PSG film 232 by CMP unlike the first embodiment. Paradoxically but therefore
(Field oxide film 10 in the first embodiment)
In contrast to the restriction on the thickness of the silicon nitride film 121 from the thickness 2b, the first
The thickness of the silicon nitride film 221 is
No limitation is imposed by the film thickness of 2b.

Next, as in the first embodiment, the silicon nitride film 221 and the silicon nitride film spacer 253a are selectively removed by wet etching with hot phosphoric acid. For example, 3 × 10 ¹² cm ^{−2 at} 30 keV
Boron ion implantation is performed, and a third boron
An ion implantation layer (not shown) is formed on the surface of the P-type silicon substrate 201 immediately below the silicon oxide film 211. After the silicon oxide film 211 is removed by, for example, wet etching with buffered hydrofluoric acid, a sacrificial oxide film (not shown) is formed on the exposed surface of the P-type silicon substrate 201. In this process, the first boron ion implantation layer 2
62a, the second boron ion-implanted layer 262b and the third boron ion-implanted layer are activated, and the first P-type channel stopper layer 203a, the second P-type channel stopper layer 203b, It becomes the channel dope layer 204 (FIG. 3C). Channel dope layer 204 has a depth of less than 0.1 μm.

After the sacrificial oxide film is removed by wet etching with buffered hydrofluoric acid or the like, a gate oxide film 205 having a thickness of, for example, about 8.5 nm is formed by thermal oxidation.
Is formed in a region of the surface of the P-type silicon substrate 201 where an element formation region is to be formed. Gate electrode 206
Is formed, an N-type source / drain region 207 having a junction depth of about 0.1 μm is formed by ion implantation of arsenic using the gate electrode 206 and the field oxide films 202a and 202b as a mask. The semiconductor device according to the present embodiment is completed [FIG. 3D].

The second embodiment has the advantages of the first embodiment, including the solution of the problems inherent in the first conventional technique (and the second conventional technique). Have.

The application example of the second embodiment also relates to an N-channel MOS transistor.
The application of the present embodiment is not limited to this,
It can be applied to a P-channel MOS transistor. In addition,
The various numerical values and the like of the application example of the second embodiment are not limited to the values and the like described above.

Referring to FIGS. 4 and 5, which are schematic cross-sectional views of a manufacturing process of a semiconductor device, an application example of the third embodiment of the present invention also shows that the present embodiment has an N5 of 0.25 μm design rule. This is applied to the manufacture of a channel MOS transistor, and is as follows.

First, for example, if the impurity concentration is 1 × 10 ¹⁵ cm
^The thickness of the P-type silicon substrate 301 of about ^-3
1 nm silicon oxide film (pad oxide film) 31
1 is formed by thermal oxidation. This silicon oxide film 31
1 is covered with a first silicon nitride film 321 having a thickness of about 100 nm by a vapor phase growth method. The surface of the silicon nitride film 321 has a thickness of 400
It is covered with a PSG film 332 of about nm. Further, the surface of the PSG film 332 is covered with a second silicon nitride film 341 having a thickness of about 50 nm. Further, the surface of the silicon nitride film 341 is covered with a second silicon oxide film 351 having a thickness of about 20 nm [FIG.
(A)]. In the present embodiment, the silicon oxide film 35
1, the sum of the effective thicknesses of the silicon nitride film 341, the PSG film 332, and the silicon nitride film 321 functions as a mask for a series of boron ion implantations for forming a P-type channel stopper layer. It is necessary that the film thickness be sufficient for this. In this embodiment and the embodiment, P
A BPSG film may be used instead of the SG film 232,
PSG film or BPS instead of silicon oxide film 351
It is not preferable to use a G film.

Next, a photoresist film pattern (not shown) is formed to cover the surface of the second silicon oxide film 351 on the surface of the P-type silicon substrate 301 where the element formation region is to be formed. Is done. Using this photo resist film pattern as a mask, anisotropic etching is sequentially performed on silicon oxide film 351, silicon nitride film 341, PSG film 332 and silicon nitride film 321, and a first opening reaching silicon oxide film 311 is formed. 361a, a second opening 361b and the like are formed. The opening 361a,
The first and second opening widths at 361b are, for example, 0.3
μm and 0.8 μm. Similarly to the first and second embodiments, the anisotropic etching of the PSG film 332 is preferably performed by RIE using a mixed gas of trifluoromethane and tetrafluoromethane.
RIE using a mixed gas of difluoromethane and carbon dioxide is also preferable for the anisotropic etching of 21. Next, the photo resist film pattern is removed. 50n film thickness over the entire surface by LPCVD
An about m third silicon nitride film 352 is formed (FIG. 4B).

Next, the silicon nitride film 352 is etched back by a mixed gas of difluoromethane and carbon dioxide, leaving a silicon nitride film spacer 353 covering the side surfaces of the openings 361a and 361b. [FIG.
(C)]. In this embodiment mode, unlike the second embodiment mode, the second silicon oxide film 351 is provided. Therefore, the thickness of the second silicon nitride film 341 is smaller than that of the third silicon nitride film 352. The thickness can be reduced without being restricted by the film thickness. Further, in the present embodiment,
Since the second silicon oxide film 351 is interposed between the third silicon nitride film 351 and the second silicon nitride film 341 as compared with the second embodiment, the formation of the silicon nitride film spacer 353 is not necessary. The controllability (for the detection of the end point, etc.) in the etch back is excellent.

Next, the second silicon oxide film 351 and the second
Oxidation using a stacked film composed of the silicon nitride film 341, the PSG film 332 and the first silicon nitride film 321 as a mask and a silicon nitride film spacer 353 covering the side surfaces of the openings 361 a and 361 b provided in the stacked film as masks Thereby, a field oxide film is formed. The field oxide film 302a and the opening 361 just below the opening 361a
The film thickness of the field oxide film 302b immediately below b is about 200 nm and about 350 nm, respectively. As described above, in the present embodiment, the oxidation-resistant mask is constituted by the laminated film having the four-layer structure and the silicon nitride film spacer 353. Further, as described above, there is no restriction on the film thickness of the silicon nitride film 341. Relaxation of the stress in the vicinity of the bird's beak of the oxide film becomes easier than in the second embodiment. Similarly to the second embodiment, outward diffusion of phosphorus (conductivity type impurity) from PSG film 332 during selective oxidation is suppressed.

Subsequently, using the laminated film and the silicon nitride film spacer 353 as a mask, the P-type silicon substrate 30 is formed.
Perpendicular to the surface of 1, for example, 1 × 10 ¹³ cm at 80 keV
Ion implantation of about ^-2 boron and 1.5 × at 140 keV
Boron ion implantation is performed using at least two types of implantation energies, such as boron ion implantation of about 10 ¹³ cm ⁻² . Thereby, the field oxide film 30
A first boron ion implantation layer 362a and a second boron ion implantation layer 362b contacting the bottom surfaces of 2a and 302b, respectively, are formed on the P-type silicon substrate 301. In order to suppress the narrow channel effect, the field oxide film 3
02a, 302b, Bird's Beak
The ion implantation layers 362a and 362b are formed so as not to contact the silicon oxide film 311 (FIG. 4D). As in the first and second embodiments, also in the present embodiment, when the thickness of the field oxide film 302b is sufficiently larger than the thickness of the field oxide film 302a, the oblique rotation ion implantation of boron is performed. Is preferably added. Further, it is preferable that the implantation angle and the implantation energy are defined by the aspect ratio of the second opening 361b and the thickness of the field oxide film 302b.

Next, trifluoromethane and tetra.
By RIE with a mixed gas with fluoromethane or wet etching with buffered hydrofluoric acid,
The second silicon oxide film 351 is removed. When the etching of the silicon oxide film 351 is removed, the thicknesses of the field oxide films 302a and 302b are also reduced to at most about 30 nm. However, the initially set silicon oxide film 3
Since the film thickness of the field oxide film 302a is sufficiently smaller than the film thickness of the field oxide film 302a, etc.
Such a decrease in the film thickness does not lower the function as an element isolation region [FIG. 5 (a)].

Next, the silicon nitride film 34 is formed by RIE using a mixed gas of difluoromethane and carbon dioxide.
1 is removed, and the silicon nitride film spacer 353 becomes a silicon nitride film spacer 353a (FIG. 5B).

Next, similarly to the second embodiment, the PSG film 332 is formed by gas etching using hydrogen fluoride.
Is selectively removed [FIG. 5 (c)].

Next, as in the first and second embodiments, the silicon nitride film 321 and the silicon nitride film spacer 353a are wet-etched with hot phosphoric acid.
Is selectively removed. For example, 3 × 10 ^{12 at} 30 keV
A boron ion implantation of about cm ⁻² is performed, and a third boron ion implantation layer (not shown) is
It is formed on the surface of the P-type silicon substrate 201 immediately below.
After the silicon oxide film 311 is removed by, for example, wet etching with buffered hydrofluoric acid, a sacrificial oxide film (not shown) is formed on the exposed surface of the P-type silicon substrate 301. In this process, the first boron ion implantation layer 362a, the second boron ion implantation layer 362b, and the third boron ion implantation layer are activated, and the first P-type channel stopper layer 303a is activated. , The second P-type channel stopper layer 303b and the channel dope layer 304. Channel dope layer 304 has a depth of less than 0.1 μm.

After the sacrificial oxide film is removed by wet etching with buffered hydrofluoric acid or the like, a gate oxide film 305 having a thickness of, for example, about 8.5 nm is formed by thermal oxidation.
Is formed in a region of the surface of the P-type silicon substrate 301 where an element formation region is to be formed. Gate electrode 306
Is formed, an N-type source / drain region 307 having a junction depth of about 0.1 μm is formed by ion implantation of arsenic using the gate electrode 306 and the field oxide films 302a and 302b as a mask. The semiconductor device according to the present embodiment is completed [FIG. 5D].

The third embodiment has the advantages of the second embodiment, including the solution of the problems inherent in the first conventional technique (and the second conventional technique). Have.

The application example of the third embodiment also relates to an N-channel MOS transistor.
The application of the present embodiment is not limited to this,
It can be applied to a P-channel MOS transistor. In addition,
Numerical values and the like in one application example of the third embodiment are not limited to the values and the like described above.

[0066]

As described above, in the method of manufacturing a semiconductor device according to the present invention, the selective oxidation is performed by the first laminated film having the two-layer structure including the second silicon oxide film and the silicon nitride film.
Second laminated film having a three-layer structure including a silicon nitride film, a PSG film (or a BPSG film), and a second silicon nitride film, and a third nitride film covering an opening provided in an opening of the laminated film. An insulating film spacer made of a silicon film, or a first silicon nitride film and a PSG film (or BPSG film)
Film), a second silicon nitride film, and a second silicon oxide film, a third stacked film having a four-layer structure, and a third silicon nitride film covering an opening provided in an opening of the stacked film. The insulating film spacer is used as an oxidation-resistant mask.

For this reason, the second silicon oxide film constituting the first stacked film is selectively removed by CMP,
And a PSG film (or BP) constituting the third laminated film
The SG film is selectively removed by gas etching with hydrogen fluoride. That is, in the method of manufacturing a semiconductor device according to the present invention, the removal of the laminated film used for the oxidation-resistant mask is performed without any trouble. Further, according to the present invention, it is easy to alleviate the stress in the vicinity of the bird's beak of the field oxide film.

[Brief description of the drawings]

FIG. 1 is a schematic cross-sectional view of a manufacturing process according to an application example of the first embodiment of the present invention.

FIG. 2 is a schematic cross-sectional view of a manufacturing process according to an application example of the second embodiment of the present invention.

FIG. 3 is a schematic cross-sectional view of a manufacturing process according to an application example of the second embodiment.

FIG. 4 is a schematic cross-sectional view of a manufacturing process according to an application example of the third embodiment of the present invention.

FIG. 5 is a schematic cross-sectional view of a manufacturing process according to an application example of the third embodiment.

FIG. 6 is a diagram for explaining a problem of the first conventional technology, and is a schematic cross-sectional view of a manufacturing process of the first conventional technology.

FIG. 7 is a diagram for explaining a problem of the second conventional technology, and is a schematic cross-sectional view of a manufacturing process of the second conventional technology.

FIG. 8 is a view for explaining a problem of the second conventional technique, and is a schematic cross-sectional view of a manufacturing process of the second conventional technique.

[Explanation of symbols]

101, 201, 301, 401, 501 P-type silicon substrates 102a, 102b, 202a, 202b, 302a,
302b, 402a, 402b, 502a, 502b
Field oxide films 103a, 103b, 203a, 203b, 303a,
303b, 403a, 403b, 503a, 503b
P-type channel stopper layers 104, 204, 304, 504 Channel-doped layers 105, 205, 305, 505 Gate oxide films 106, 206, 306, 506 Gate electrodes 107, 207, 307, 507 N-type source / drain regions 111 , 131, 211, 311, 351, 411, 4
31,511 silicon oxide films 121,221,241,252,321,341,3
52, 421, 441, 521, 541, 552 Silicon nitride films 161a, 161b, 261a, 261b, 361a,
361b, 461a, 461b, 561a, 561b
Openings 162a, 162b, 262a, 262b, 362a,
362b Boron ion implantation layer 232, 332 PSG film 253, 253a, 353, 353a Silicon nitride film spacer 412, 412a, 512, 512a, 533 Polycrystalline silicon film 462a, 462b, 532a, 562b P-type ion implantation layer

──────────────────────────────────────────────────続 き Continued on the front page (58) Field surveyed (Int.Cl. ⁶ , DB name) H01L 21/316 H01L 21/76

Claims (10)

(57) [Claims] A first conductive type silicon substrate covering a surface thereof;
A silicon oxide film having a first thickness;
Forming a silicon nitride film covering the surface of the silicon oxide film, and forming a second silicon oxide film having a second thickness and covering the surface of the silicon nitride film; Forming a photoresist film pattern that selectively covers the surface of the second silicon oxide film on a region where a device isolation region is to be formed on the surface;・ Methane (CHF ₃ ) and tetrafluoro
At least the second silicon oxide film is anisotropically etched with a mixed gas of methane (CF ₄ ) and mixed with a mixed gas of difluoromethane (CH ₂ F ₂ ) and carbon dioxide (CO ₂ ). Anisotropically etching the silicon nitride film to form a first opening having a first opening width reaching the first silicon oxide film through the second silicon oxide film and the silicon nitride film, respectively; Forming at least a second opening having a second opening width wider than the first opening width; removing the photoresist film pattern to form the second silicon oxide film and the silicon nitride film By selective oxidation using a mask as a mask, the surface of the one-conductivity-type silicon substrate immediately below the first opening and the second opening is formed by adding the first film thickness and the second film thickness. Part of thin third film thickness And the first film thickness and the second film thickness which are larger than the third film thickness.
Forming a field oxide film having a fourth film thickness portion smaller than the sum of the film thicknesses of the field oxide film and the one conductivity type of the field oxide film in the third film thickness portion of the field oxide film. A first ion implantation of one conductivity type impurity is performed over the entire surface by a first implantation energy having a projection range near an interface of the silicon substrate, and at least a portion of the field oxide film having the fourth thickness is formed. A second ion implantation of one conductivity type impurity is performed over the entire surface by a second implantation energy having a projection range in the vicinity of the interface between the field oxide film and the one conductivity type silicon substrate. Forming a first and second one-conductivity-type ion-implanted layers on the one-conductivity-type silicon substrate, the first and second one-conductivity-type ion-implanted layers being respectively in contact with the bottom surface of the field oxide film in the fourth thickness portion; (C P), the second silicon oxide film is selectively removed, and the silicon nitride film is selectively removed by hot phosphoric acid. Forming a channel-doped layer in a region where a device forming region is to be formed on the surface of the substrate; removing the first silicon oxide film; forming a gate insulating film in a region where the device forming region is to be formed; Forming an electrode and forming a source / drain region of a reverse conductivity type in a region where the element formation region is to be formed by fourth ion implantation of a reverse conductivity type impurity using the field oxide film and the gate electrode as a mask; A method for manufacturing a semiconductor device, comprising: 2. The method of manufacturing a semiconductor device according to claim 1, wherein forming the first and second one-conductivity-type ion-implanted layers includes oblique rotation ion implantation of one-conductivity-type impurities. 3. The method according to claim 2, wherein an implantation angle in said oblique rotation ion implantation is defined by said second opening. Forming a first silicon nitride film covering a surface of the silicon oxide film having a first thickness, wherein the first silicon nitride film has a first thickness and covers a surface of the silicon oxide film;
Covering the surface of the first silicon nitride film with a thickness of
Forming an insulating film made of a PSG film or a BPSG film,
Forming a second silicon nitride film having a third thickness and covering the surface of the insulating film; and forming the second nitride film on a region where a device isolation region is to be formed on the surface of the one conductivity type silicon substrate. Forming a photo-resist film pattern that selectively covers the surface of the silicon film; anisotropically etching the second silicon nitride film using the photo-resist film pattern as a mask; Anisotropically etching at least the insulating film with a mixed gas of and tetrafluoromethane,
The first silicon nitride film is anisotropically etched with a mixed gas of difluoromethane and carbon dioxide to penetrate the second silicon nitride film, the insulating film, and the first silicon nitride film, respectively. Forming at least a first opening having a first opening width reaching the silicon oxide film and a second opening having a second opening width wider than the first opening width; The photo-resist film pattern is removed, and a third
Forming a silicon nitride film on the side surfaces of the first and second openings by performing etch-back on the third silicon nitride film by anisotropic etching; The selective oxidation using the second silicon nitride film, the insulating film, the first silicon nitride film, and the silicon nitride film spacer as masks to form the one conductivity type immediately below the first opening and the second opening. A fourth thinner than the sum of the first thickness, the second thickness, and the third thickness is formed on the surface of the silicon substrate.
And a first film thickness greater than the fourth film thickness,
Forming a field oxide film having a second film thickness and a fifth film thickness portion smaller than the sum of the third film thickness; and forming a fourth film thickness portion of the field oxide film. A first ion implantation of one conductivity type impurity is performed over the entire surface by a first implantation energy having a projection range near an interface between the field oxide film and the one conductivity type silicon substrate. A second ion implantation of one conductivity type impurity by a second implantation energy having a projection range near an interface between the field oxide film and the one conductivity type silicon substrate in a portion having a fifth thickness; A first and a second one-conductivity-type ion-implanted layers respectively contacting the bottom surface of the field oxide film at the fourth thickness portion and the fifth thickness portion on the one-conductivity type silicon substrate; Forming process and Selectively removing the third silicon nitride film by anisotropic etching with a mixed gas of difluoromethane and carbon dioxide, and selecting the insulating film by gas etching with hydrogen fluoride (HF) The first silicon nitride film and the silicon nitride film spacer are selectively removed with hot phosphoric acid, and the third ion implantation of the required conductivity type impurity is performed to remove the surface of the one conductivity type silicon substrate. Forming a channel / doped layer in a region where a device formation region is to be formed; removing the silicon oxide film; forming a gate insulating film in a region where the device formation region is to be formed; forming a gate electrode; A fourth ion implantation of a reverse conductivity type impurity using the oxide film and the gate electrode as a mask causes a reverse conductivity type source / drain to be formed in a region where the element formation region is to be formed. The method of manufacturing a semiconductor device characterized by a step of forming a band. 5. The method of manufacturing a semiconductor device according to claim 4, wherein said first and second one-conductivity-type ion implantation layers include oblique rotation ion implantation of one-conductivity type impurities. 6. The method according to claim 5, wherein an implantation angle in the oblique rotation ion implantation is defined by the second opening. 7. A first substrate covering a surface of a silicon substrate of one conductivity type.
A silicon oxide film having a first thickness;
Forming a first silicon nitride film covering the surface of the first silicon nitride film, covering the surface of the first silicon nitride film with a second thickness, and forming an insulating film made of a PSG film or a BPSG film; Forming a second silicon nitride film having a third thickness and covering the surface of the insulating film; and forming a second silicon nitride film having a fourth thickness and covering the surface of the second silicon nitride film. Forming a silicon oxide film; and forming a photoresist film pattern that selectively covers a surface of the second silicon oxide film on a region where an element isolation region is to be formed on the surface of the one conductivity type silicon substrate. Using the photoresist film pattern as a mask, anisotropically etching the second silicon oxide film and the second silicon nitride film to obtain trifluoromethane and tetrafluoromethane;
At least the insulating film is anisotropically etched with a mixed gas of fluoromethane and difluoromethane.
The first silicon nitride film is anisotropically etched with a mixed gas with carbon oxide to penetrate the second silicon oxide film, the second silicon nitride film, the insulating film, and the first silicon nitride film, respectively. Forming at least a first opening having a first opening width reaching the first silicon oxide film and a second opening having a second opening width larger than the first opening width. Removing the photo-resist film pattern;
Forming a silicon nitride film on the side surfaces of the first and second openings by performing etch-back on the third silicon nitride film by anisotropic etching; The first opening and the second opening are formed by selective oxidation using the second silicon oxide film, the second silicon nitride film, the insulating film, the first silicon nitride film, and the silicon nitride film spacer as a mask. A portion having a fifth film thickness smaller than the sum of the first film thickness, the second film thickness, the third film thickness and the fourth film thickness,
The first film thickness, the second film thickness, and the third film thickness are larger than the fifth film thickness.
Forming a field oxide film having a thickness of less than the sum of the fourth thickness and a sixth thickness of the field oxide film; and forming the field oxide film of the fifth thickness portion of the field oxide film. A first ion implantation of one conductivity type impurity is performed on the entire surface by a first implantation energy having a projection range near an interface between the oxide film and the one conductivity type silicon substrate, and at least the sixth ion implantation of the field oxide film is performed. A second ion implantation of one conductivity type impurity is performed over the entire surface by a second implantation energy having a projection range near an interface between the field oxide film and the one conductivity type silicon substrate at a thickness of First and second one-conductivity-type ion-implanted layers are respectively formed on the one-conductivity-type silicon substrate so as to be in contact with the bottom portion of the field oxide film in the fifth-thickness portion and the sixth-thickness portion, respectively. Process and The second silicon oxide film is removed, and the second silicon nitride film is selectively removed by anisotropic etching using a mixed gas of difluoromethane and carbon dioxide. A step of selectively removing the insulating film by etching and a step of selectively removing the first silicon nitride film and the silicon nitride film spacer by hot phosphoric acid; and a third ion implantation of a required conductivity type impurity. Forming a channel dope layer in a region where a device forming region is to be formed on the surface of the conductive silicon substrate; removing the first silicon oxide film and forming a gate insulating film in a region where the device forming region is to be formed Forming a gate electrode, and forming the element formation region by fourth ion implantation of a reverse conductivity type impurity using the field oxide film and the gate electrode as a mask. The method of manufacturing a semiconductor device characterized by a step of forming the source and drain regions of the opposite conductivity type. 8. The method according to claim 7, wherein the fifth film thickness is sufficiently larger than the fourth film thickness. 9. The semiconductor device according to claim 7, wherein said first and second ion implantation layers of one conductivity type include oblique rotation ion implantation of impurities of one conductivity type. Manufacturing method. 10. The method according to claim 9, wherein an implantation angle in the oblique rotation ion implantation is defined by the second opening.