JP2833915B2 - Information transmission system - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an information transmission system including an information transmission source such as an exchange and one or more terminals for receiving information transmitted from the information transmission source. The present invention relates to an information transmission system suitable for transmitting information and controlling the information.

[0002]

2. Description of the Related Art FIG. 4 shows an example of an information transmission system connecting an information transmission source and a terminal. Here, in order to simplify the description, an information transmission source 11 such as an exchange is connected to one terminal 12 by highways (transmission paths) 13 ₁ and 13 ₂ . In such information transmission systems, in the case that performing the inspection of highway 13 _1, 13 _2,
For example, this is short-circuited on the way to form a loop, and it is checked whether a signal is transmitted correctly.

FIG. 5 shows a configuration of an information transmission system conventionally proposed for performing such a loop test. In this system, the information transmission source 11 and the terminal 1
2, a control device 14 is arranged. Control device 14
Inside, a bypass switch 15 for forming a loop in the middle of the highways 13 ₁ and 13 ₂ is provided. The bypass switch 15 is controlled via an I / O (input / output port) 18 connected to a CPU (central processing unit) 16 via a bus 17.

[0004] Information on the CPU16 from highway 13 ₁ for transmitting information sent from the information sending source 11 are inputted. When the information transmission source 11 outputs information indicating that a loop test is to be performed for maintenance and inspection, the CPU 16 controls the I / O 18 based on the information and causes the bypass switch 15 to close. In this way, a loop is formed in the middle of the highways 13 ₁ and 13 ₂ , and a test is performed.

FIG. 6 shows another information transmission system which enables a loop test. In this system, in addition to the highways 13 ₁ and 13 _2, a transmission path 21 for a communication protocol such as HDLC and a control device 22 for receiving and decoding this communication protocol are prepared. Also, terminal 1
2A, a bypass switch 23 for forming a loop at the entrance and a control circuit 24 for decoding control information (instruction information) sent from the control device 22 and controlling the bypass switch 23 are provided. Is provided.

In the information transmission system shown in FIG.
When the information transmission source 11 performs a loop test, the information transmission source 11 transmits information to that effect to the transmission path 21 for the communication protocol.
2 communicates with the control circuit 24 using a predetermined protocol to close the bypass switch 15 of the terminal 12A. In this way, a loop is formed in the highways 13 ₁ and 13 ₂ , and a test is performed.

[0007]

In the conventional information transmission system shown in FIG. 5, when a plurality of terminals are prepared, it is necessary to prepare I / Os for individually controlling the terminals. These I / Os are connected to the CPU 16 by buses 17, respectively. Therefore, the control device 1
In addition to the complicated circuit configuration of No. 4, there was a problem that the integration efficiency deteriorated. Further, even if an attempt is made to replace a certain circuit portion as a result of the loop test, since each I / O is connected by the bus 17, it is difficult to realize the circuit portion.

The latter information transmission system using a communication protocol such as HDLC (High Level Data Link Control Procedure) shown in FIG. 6 can solve these disadvantages. However, in the latter information transmission system, the information transmission source 11 is newly added to the transmission path 2 for the communication protocol.
1 and a control circuit 2 is provided for each terminal (only one terminal 12A is shown in the figure).
4 must be prepared to process the protocol with the control device 22. For this reason, it is necessary to prepare a program for this processing in the control device 22 and each terminal, and to arrange a circuit portion for executing the processing, which also has a problem that the integration efficiency is deteriorated.

Further, in the information transmission system shown in FIGS. 5 and 6, not only the loop test but also the terminal 12,
It is normal to send various kinds of control information to 12A. Therefore, as the types of such information increase, there is also a problem that the information processing capability, the information transfer efficiency, and the information processing speed decrease in any of the information transmission systems.

SUMMARY OF THE INVENTION An object of the present invention is to make it possible to control a terminal without complicating a transmission path between an information transmission source and the terminal or a circuit configuration therebetween, and without reducing the information processing capability and the like. To provide an information transmission system.

[0011]

According to the first aspect of the present invention, there is provided (a) a time slot for a main signal bit of a frame.
Is additional information of the main signal the first information given frame
A first information sending means for sending incorporated into predetermined bit positions of the slot, (b) a terminal receiving the frame, (c) from the first information source provided separately, the bit position
And a second information transmitting means for inserting the second information in place of the first information in the information transmission system.

That is, according to the first aspect of the present invention, the first information transmitting means such as an exchange is provided with a main signal bit tag of the frame .
Additional information for controlling the terminal to the main signal of the time slot
The first information, which is the information, is stored in a predetermined slot of the frame in advance.
It sent to incorporate the provisions bit position terminal, the second information transmitting unit, such as a personal computer the first place by e.g. Similarly personal con Manipulator the information of the frame
Data or the like is used to select or insert the second information using the indication information created in the same manner as the second information. In this way, the terminal on the receiving side can determine its own control content by referring to the bit position defined for each piece of control information .

[0013] In the second aspect of the present invention, according to claim 1, wherein
In the information transmission system, the second information sending means includes the first information.
Decodes the frame sent by the report sending means, and decodes the frame.
The second information is transmitted by the transmission timing created based on the
Information is transmitted. Thereby, the first
The second information is transmitted to the terminal according to the instruction of the information transmitting means.

[0014]

According to a third aspect of the present invention, there is provided the first aspect.
When inserting the second information, the third
Means for creating indication information as the above information and inserting it into the above-described bit position using the indication information. By controlling the third information, the second information can be inserted only when it is desired to insert the second information.

According to the fourth aspect of the present invention, the terminal that receives the first information in which the second information is incorporated extracts a bit addressed to itself from a predetermined bit position in an arbitrary slot of the received frame. Bit extraction means and control means for performing control according to the extracted bits are provided. This information for a specific terminal obtained one bit at a time for one frame may be combined in order to form one control information, or when a certain number of frames are repeatedly transmitted, The control content may be specified based on which frame bit information.

According to the fifth aspect of the present invention, it is specified that a plurality of terminals receive a frame. In this case, each terminal extracts a bit from a predetermined unique bit position of an arbitrary slot of the frame and uses it for control.

[0018]

DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be described in detail below with reference to embodiments.

FIG. 1 shows a control device as a main part of an information transmission system according to an embodiment of the present invention. The control device 31 is, for example, the information processing device 1 shown in FIG.
1 and is intended to be placed first in the middle of the highway 13 ₁ between the terminal 12. Signal of the frame format to be transmitted to the first highway 13 _1A connected to the information processing apparatus 11 is input to the serial-parallel conversion circuit 32 of the control device 31, wherein the parallel data 33,3
4 is converted.

The parallel data 33 is supplied to a control information insertion circuit 35, where 1-bit control information 36 is inserted at a specific bit position of a specific slot. The parallel data 37 output from the control information insertion circuit 35 is input to a parallel / serial conversion circuit 38 and converted into serial data 39. The serial data 39 is output to the first highway _131B after the phase shift is adjusted by the secondary output highway phase adjustment circuit 41. This first highway 13 _1B is connected to the corresponding terminal 12
(See FIG. 4).

On the other hand, the parallel data 34 is supplied to various control timing generation circuits 43. The various control timing generation circuits 43 are provided in the memory read address generation circuit 4.
5. Various timing signals are supplied to each of the memory write / read address selection circuit 46, the control information storage memory 47, the indication information storage memory 48, and the gate circuit 49.

Here, the memory write / read address selection circuit control information storage memory 47 and indication information storage memory 48 store control information or indication information from the firmware 51. . Here, the control information and the indication information 52 output from the firmware 51 are latched by the write data latch register 53, and according to the memory write address 55 output from the memory write address / control timing creation circuit 54. Control information storage memory 4
7 or the indication information storage memory 48.

Memory write / read address selection circuit 46
Is a circuit for switching a memory address between writing and reading. Here, various control timing generation circuits 43
The address 56 created by the memory read address creation circuit 45 based on the fixed cycle memory write / read timing supplied to the memory read address creation circuit 45 from the
And memory address / control timing generation circuit 5
4 is switched to the memory write address 57 output from the memory 4.

The read data latch register 58 latches control information or indication information read from the control information storage memory 47 or the indication information storage memory 48, and sends them to the firmware 51. ing. When reading the control information or the indication information, the address 56 created by the memory read address creating circuit 45 is used as the address information. The firmware 51 checks the read control information and indication information so as to check whether or not the corresponding data has been normally written in the control information storage memory 47 and the indication information storage memory 48, respectively. Has become.

Next, the configuration of the control information storage memory 47 and the indication information storage memory 48 and the configuration of data output from the firmware 51 will be described.

Each of the control information storage memory 47 and the indication information storage memory 48 has an 8-bit configuration. All TS (time slots) are transmitted in all frames transmitted on the first highways 13 _1A and 13 _1B to be used. It has the capacity just multiplied. Here, all frames refer to a plurality of frames that are repeated periodically. The firmware 51 uses 16-bit data, allocates the upper 8 bits of the data as indication information, and uses the lower 8 bits as control information to be actually transmitted to the controlled device (terminal device).

The indication information has the same characteristics as a flag indicating that a change in data has been detected when the data has changed in the firmware 51. In the present embodiment, after the control information (bits) transmitted by the firmware 51 is converted into parallel by the serial / parallel conversion circuit 32, the corresponding controlled device of the predetermined TS of the corresponding frame of the first highway _131B. This bit is used when inserting at the bit position corresponding to.

The indication information is set in the same bit position (upper) of the same address as the bit position (lower) of the corresponding control information to be inserted.

In this information transmission system, the firmware 5
The control information and indication information output from 1 are
The data is written to the corresponding control information storage memory 47 or indication information storage memory 48, respectively.
Then, based on the read timing created by the memory write address / control timing creation circuit 54 and the read address according to the highway TS created by the various control timing creation circuits 43, a serial / parallel conversion circuit is used. Parallel data 34 output from 32
Is read out at the same timing as.

The control information output from the control information storage memory 47 and the parallel data 33 output from the serial / parallel conversion circuit 32 are input to a data section (not shown) of the control information insertion circuit 35, and the indication information is output. The indication information output from the storage memory 48 is input to a selection signal section (not shown) of the control information insertion circuit 35. As a result, the indication information output from the indication information storage memory 48 is stored in the first highway 13 in the predetermined TS.
_The data is written to a bit position corresponding to a terminal (not shown) connected to _1B .

FIG. 2 shows how control information is inserted from the firmware 51 using the indication information. FIG. 3A shows the configuration of one frame. In our example we have set the TS ₁ of one frame composed of TS ₁ ~TS _N for terminal control information, M bits constituting this (b ₁ ~b _M Fig (b))
Is assigned to each terminal one bit at a time. Also, FIG. 3C sets the same TS assigned for terminal control information in the same configuration frame as FIG. 2A as indication information, and sets this as a selection signal section (not shown) of the control information insertion circuit 35. Is entered. In the control information insertion circuit 35, for example, when the indication information is "1", the control information output from the firmware 51 is selected, and when the indication information is "0", the parallel data 33 is selected. If the data shown in d) is inputted from the firmware 51 as indication information, the control information outputted from the firmware 51 is inserted into the _{b 1, b 4, b 6} , b 8 shown in FIG. 2 (b) The information of the first highway _131A is notified to the remaining bits as they are. Thus, for example, a first terminal (not shown) extracts only the first bit b ₁ of TS _1,
Based on this, the corresponding control such as a loop test is executed. The second terminal will perform the same control as well to extract the second bit b ₂ of TS _1. The same applies hereinafter.

FIG. 3 shows an example of 10 frames F₁
~ F_TenOf terminal control when is repeated periodically
It is for explaining the situation. For example, the first frame
Mu F ₁Is a frame that instructs the execution of a loop test
If this first frame F₁TS in₁The first bee
B₁(See Figure 2), the first terminal is
Highway 13 of₁, 13_Two(See Fig. 6)
A loop test will be performed. In this case, other frames
Room F_Two~ F_TenAre assigned to each other control
It is possible.

[0033] When a frame transmitted first to highway 13 ₁ as independent one frame each bit of predetermined bit positions of the TS reception side terminal corresponds to each frame The information for control may be decoded by extracting information one bit at a time in one frame and concatenating them into a predetermined bit length.

Although the embodiment does not specifically describe how the data output from the firmware 51 is created, the data may be created according to the instruction of the information transmission source 11 described with reference to FIG. Alternatively, the firmware 51 may be created and output independently by operating a keyboard or the like (not shown). In the former case, the control device 31 directly controls the terminal 12, so that the load on the information transmission source 11 can be reduced. However,
In this case, for example, the parallel data 34 output from the serial / parallel conversion circuit 32 is
Must be entered.

In this embodiment, the control information and the indication information are outputted from the firmware 51. However, such data may be outputted with the intervention of software.

[0036]

As described above, according to the present invention, 1-bit information is added to a main signal at a predetermined bit position of a predetermined slot of a frame, for example, by using indication information for each terminal. To control the terminal
Since the first information and the second information, which are the control information of (1) and (2), are selected or inserted, it is sufficient to read and control the corresponding bits on the terminal side (controlled side), and the circuit of the entire information transmission system is controlled. The configuration can be simplified. Further, there is no need to use a special control program, and there is an effect of improving data transfer efficiency.

[Brief description of the drawings]

FIG. 1 is a block diagram illustrating a main part of an information transmission system according to an embodiment of the present invention.

FIG. 2 is an explanatory diagram showing a structure of one frame in the embodiment.

FIG. 3 is an explanatory diagram showing a case where a plurality of frames are repeatedly transmitted in this embodiment.

FIG. 4 is a system configuration diagram showing a general form of an information transmission system in the case of one terminal.

FIG. 5 is a system configuration diagram illustrating a first example of a conventionally proposed information transmission system in a case of one terminal.

FIG. 6 is a system configuration diagram showing a second example of a conventionally proposed information transmission system in the case of one terminal.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 11 Information transmission source 12 Terminal 13 ₁ 1st highway 13 ₂ 2nd highway 23 Bypass switch 31 Controller 32 Serial / parallel conversion circuit 35 Control information insertion circuit 45 Memory read address creation circuit 46 Memory write / read Address selection circuit 47 Control information storage memory 48 Indication information storage memory 51 Firmware

──────────────────────────────────────────────────続 き Continuation of the front page (56) References JP-A-61-255142 (JP, A) JP-A-52-91312 (JP, A) JP-A-60-29082 (JP, A) (58) Field (Int.Cl. ⁶ , DB name) H04L 29/08 H04L 12/42 H04Q 11/04 303 H04J 3/00

Claims (5)

(57) [Claims] 1. A time slot for a main signal bit of a frame.
Where the first information is additional information of the bets of a main signal frame
A first information transmitting unit that transmits the data by incorporating the data into a predetermined bit position of a predetermined slot; a terminal that receives the frame; and a first information source that is provided separately from the bit position.
And a second information sending means for inserting the second information in place of the first information . 2. The second information sending means decodes the frame sent by the first information sending means, and based on the decoding result,
The second information is transmitted according to the transmission timing created by
Information transmission system according to claim 1, wherein that output. 3. The method according to claim 2, wherein said second information sending means is used to store second information.
When inserting the information, the indication as the third information
The first information and the second information based on this information.
Select and send the one you want to send
The information transmission system according to claim 2 . 4. The terminal according to claim 1, further comprising :
Extract bits from predetermined bit positions in desired slots
Bit extraction means and control according to the extracted bits
2. The information transmission system according to claim 1, further comprising control means for performing the operation. 5. A plurality of terminals receiving the frame.
And each terminal has an arbitrary slot in the frame.
The information transmission system according to claim 1, wherein a bit is extracted from a predetermined unique bit position .