JP2834372B2 - Music information processing apparatus and music information processing method - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a music information processing system, and more particularly to an improvement in communication control of music information.

[0002]

2. Description of the Related Art Conventionally, there is a MIDI (musical instrument digital interface) system as a typical example of communication of music information. The MIDI is a standard for ensuring consistency between devices when an electronic musical instrument, a sequencer, a computer, a rhythm machine, and the like are interconnected and performance information of digital signals is communicated in real time.

[0003] Connectors used for communication of this MIDI system are "MIDI IN" and "MIDI OUT".
It has three types of terminals, "MIDI THRU".
Through these terminals, the performance information of the digital signal is serially transmitted asynchronously in one direction. The transmitted data includes channel messages, system messages, voice messages such as note on / off and pitch vendor, and mode messages such as all note off and poly mode on.

On the other hand, music data communication is also performed in electronic musical instruments. For example, an SIO (serial input / output) device and a PIO (parallel input / output) device. The data communication of such a PIO device is performed in parallel, and the number of data communication bits is 8, 16, 32 bits or the like. Then, in data communication, for example, after transmitting music data, transmitting communication control information,
After transmitting the next music data, the next communication control information is transmitted, so that the music data and the communication control information are transmitted separately. The communication control information includes communication conditions (protocol) such as the number of data bytes, data bit length, data communication speed, and error detection method of the plurality of music data.
Is shown.

[0005]

However, the above M
In the IDI system, music data and communication control information cannot be transmitted at high speed because of serial transmission. The PIO device can transmit at high speed because of parallel transmission.

Although the number of data communication bits of this PIO device is 8, 16, 32 bits, etc., the number of bits of music data to be transmitted does not match such a number of bits, which is wasteful. It could not be said that it was used effectively. For example, the number of bits of music data transmitted in an 8-bit communication system is 7 bits, 6 bits, or the like, and the difference of 1 bit or 2 bits is not used and wasted.

SUMMARY OF THE INVENTION The present invention has been made to solve the above-mentioned problems, and an object of the present invention is to eliminate the above-mentioned waste of data communication bits of a music information processing system and to use the system effectively in data communication. It is in.

[0008]

In order to achieve the above object, according to the present invention, music data and communication control information relating to communication of the music data are received from a transmitting means via a data bus and a communication control means. It was sent to the means in parallel.

[0009]

As a result, the music data and the communication control information are transmitted in parallel, so that there are no useless empty bits in the data communication bits, and the entire system can be used effectively. Also, since the music data and the communication control information are sent at the same time, the processing according to the communication control information and the processing according to the music data are performed simultaneously or within a short time,
The whole process is executed quickly and smoothly.

[0010]

【Example】

<< 1 >> Overall Circuit FIG. 1 shows an overall circuit of an electronic musical instrument. Input / output circuit 10
In 0, keys of a keyboard (not shown), a panel switch group (not shown) and a MIDI interface (not shown), on / off event data of each switch, and other data are stored. This on / off event is detected by a scanner (not shown).
The keyboard is composed of strings, tubes (leads), hits (pads),
A computer keyboard can be used instead.

The ROM 101 stores a program corresponding to a flowchart described later, a program executed by the main CPU 103, a program corresponding to other processing, and various data. The RAM 102 has a main CPU 1
Various data used in the processing of step 03 and various processed data are stored. The main CPU 103 converts the event data stored in the event queue register EQ of the input / output circuit 100 into a format shown in FIG.

Address data is transmitted via the address bus 113 to the transmission / reception control circuit 104, the input / output circuit 100,
It is transmitted and received among the OM 101, the RAM 102, the main CPU 103, the keyboard, the panel switch group, and the scanner. Also, various information (data and programs such as event data EV and command data CM) is transmitted and received by the transmission / reception control circuit 104 and the input / output circuit 1 via the data bus 114.
00, ROM 101, RAM 102, main CPU 10
3. Sent between the keyboard, panel switch group, and scanner.

The master tone generator 105 and the slave tone generator 106 include a transmission / reception control circuit 10
The tone data corresponding to the event data EV transmitted through the D / A converter 4 is generated.
The sound is generated by the sound system 112 via the anagro mixer 111 and the anagro mixer 111.

The ROM 107 stores a program corresponding to a flowchart described later, a program executed by the master CPU 301 of the master tone generator 105, a program corresponding to other processes, and various data.
The various data include tone waveform data MW corresponding to a plurality of types of tone colors. The tone waveform data MW of a plurality of timbres is sequentially read in a time division manner and sent to the master tone generator 105 and the slave tone generator 106 to generate tone data. In the RAM 108,
Various data used for various processes and various processed data are stored.

Address data is transmitted via an address bus 115 to the transmission / reception control circuit 104, master tone generator 105, slave tone generator 106, ROM 1
07, transmitted and received between the RAM 108. In addition, various information (data and programs such as event data EV and command data CM and the like) are transmitted and received by the transmission / reception control circuit 104, the master tone generator 105, the slave tone generator 106, the ROM 107, the RA via the data bus 116.
M108, the main CPU 103, the keyboard, the panel switch group, and the scanner are transmitted and received.

In the transmission / reception control circuit 104, the CPU
Transmission and reception of various information between the circuit group such as 103 and the circuit group such as the master tone generator 105 and the slave tone generator 106 are controlled. From the external reset circuit 117, the main CPU 103 and the transmission / reception control circuit 10
In step 4, an external reset signal RESET is sent when the power is turned on or the like, and is reset to an initial state.

The master reset signal M-RST and the slave reset signal S-RST corresponding to the external reset signal RESET are sent from the transmission / reception control circuit 104 to the master tone generator 105 and the slave tone generator 106 with a shift. Reset to state. From the master clock generator 109, the transmission / reception control circuit 104, the master tone generator 1
The master clock signal MCK is sent to the slave tone generator 05 and the slave tone generator 106, and various processes are synchronized.

<< 2 >> Transmission / Reception Control Circuit 104 FIG. 2 shows the transmission / reception control circuit 104. Various information (data such as event data EV and command data CM and programs) on the data bus 114 is transmitted via the interface unit 203 to the data bus 116.
To the data bus 11 via the interface unit 203.
4 is sent out.

The data on the data bus 116 is stored in the extension address generator 205 and output to the address bus 115 at a timing corresponding to each time-division channel. The stored data is the upper two bits (extended address data) of the read address data RA of the tone waveform data MW of the ROM 107. The time division channel number data CN for reading the tone waveform data MW and the master / The output timing is controlled by the slave bit signal M / S.

The upper read address data RA, the time division channel number data CN, and the master / slave bit signal M / S are transmitted by the master CPU 301 to the RA.
It is read from the assignment memory 306 of M108 and sent to the extended address generator 205. In the extended address generator 205, the higher-order read address data R is divided in the division time according to the time division channel number data CN and the master / slave bit signal M / S.
A is output and sent to the ROM 107 to read out the tone waveform data MW.

In the decoder 201, the main CPU 103
Address data, read / write signal RD1 / W
The inverted signal of R1 is converted, the converted signal is supplied to the interface unit 203, and input / output control of the above various information between the interface unit 203 and the data bus 114 is performed.

In the decoder 202, the master tone generator 105 or the slave tone generator 106
Data, read / write signal RD2 / W
The inverted signal of R2 is converted, the converted signal is supplied to the interface unit 203, and input / output control of the above various information between the interface unit 203 and the data bus 116 is performed. The conversion signals include address control signals ADC1 and ADC2 which become high level when a part (the upper few bits data) or all of the address data becomes a specific value, and the read / write signal R
D1 / WR1, RD2 / WR2.

The specific value of the address data is, when viewed from the main CPU 103 side, an address value when the interface unit 203 (or master tone generator 105, slave tone generator 106, ROM 107 or RAM 108) is addressed, and This is an address value when the interface unit 203 or the (input / output circuit 100, ROM 101 or RAM 102) is addressed when viewed from the tone generator 105 side. The address control signals ADC1 and ADC2 may use a transmission instruction signal of the event data EV and the command data CM, or a chip enable signal of the interface unit 203.

The master clock signal MCK from the master clock generator 109 is input to the clock generator 204, and various clock signals φ0 to φA and a sub master clock signal SMCK are generated and output. The clock signals φ0 to φA are output from the extension address generator 2
05, and the switching control of the time division channel is performed.

The clock signals φ0 to φA and the external reset signal RESET from the external reset circuit 117
Is input to the reset controller 206, and the master reset signal M-RST and the slave reset signal S
-RST is generated and the master tone generator 1
05 and the slave tone generator 106. The reset controller 206 also generates an internal reset signal RST, which is sent to the clock generator 204 and the extended address generator 205,
It is reset to the initial state.

<< 3 >> Interface Unit 203 FIG. 3 shows the interface unit 203. Information D10 to D17 on the data bus 114 are
The data is sent to the data bus 116 via the buffer 502. On the other hand, information D20 to D27 on data bus 116
Is sent to the data bus 114 via the latch 504 and the buffer 503.

The inverted signal of the write signal WR 1 from the main CPU 103 and the address control signal ADC 1 from the decoder 201 are supplied to the latch 501 via a NAND gate 505 as a latch signal. Latching to the latch 501 is performed at the rising edge of the latch signal. The inverted signal of the read signal RD2 from the master CPU 301 and the address control signal ADC2 from the decoder 202 are connected to the NAND gate 50.
7, the data D10 to D17 are sent to the buffer 502 as gate signals, and are sent to the data bus 116.

On the other hand, the master tone generator 10
5 / An inverted signal of the write signal WR2 from the slave tone generator 106 and the address control signal ADC2 from the decoder 202 are connected to the NAND gate 508.
Is supplied as a latch signal to the latch 504 via the. Latching to the latch 504 is performed at the rising edge of the latch signal. The inverted signal of the read signal RD1 from the main CPU 103 and the address control signal ADC1 from the decoder 201 are connected to the NAND gate 5
The information D20 to D27 are supplied to the buffer 503 through the data bus 114 via the data bus 114 via the data bus 114.

The latches 501 and 504 may be capable of storing data of 8 bits or more, or may be capable of storing a plurality of 8-bit data. The address control signals ADC1 / ADC2 are supplied to the decode 201 / ADC2.
Directly through main CPU 103 / master CP without going through 202
It may be supplied from U301. Further, the interface unit 203 can be used not only for transmitting and receiving data but also for communicating other data and communication control data TC such as address data and communication control data TC. The interface unit 203 is of an asynchronous type, but may be of a synchronous type. Further, the latches 501 and 504 and the buffers 502 and 503 can be omitted according to the form of data communication, or can be changed to a data bus.

<< 4 >> Event Data EV and Command Data CM FIG. 4 shows the format of the event data EV and command data CM. The 8-bit event data EV is
Mainly from the main CPU 103 to the 8-bit data bus 11
4 to the interface unit 203, and further via the 8-bit data bus 116 to the master C.
The signal is sent to the PU 301 to perform tone control and communication control. The command data CM is mainly sent from the master CPU 301 to the main CPU 103 via the interface unit 203, and a request for the next event data EV or information transmission is performed.

The event data EV includes a key-on /
There are six types: off, tone change, volume change, tone change for each tone, overall tone change, and re-initialization. Each type of event data EV is configured with four 8-bit data as one block. The first of the four event data EVs is "11110100", indicating that it is an event. However, the reinitialization is “10000000”, which is distinguished from other events.

The upper 5 bits excluding the most significant bit of the second event data EV indicate each type of the event, and based on the second event data EV,
The master CPU 301 identifies each event. The lower two bits of the second event data EV indicate a timbre channel. The tone channels can be assigned tone numbers of four types of tones that can be generated simultaneously. The tone numbers are selected by the panel switch group or the like, and the tone channels are assigned the four types of tone. The number data of each tone color channel is shown. This tone color channel may be the time division channel number data CN or the tone color number data.

Third and fourth event data EV
Indicates the contents of each of the above events. Based on the third and fourth event data EV, the master CPU 30
1 executes each event. More specifically, the data includes key number data, touch data (velocity data), timbre number data, volume data, pitch data, and the like.

The first bit of each event data EV is communication control data TC. The event data EV changes from "1" to "0" to "1" to "0" from the first to the fourth to identify the order of the received event data EV. The first “1”, the third “1”, the second “0”, and the fourth “0” are identified based on the command data CM of the master CPU 301. Of course, the number of bits of the communication control data TC may be one or more, and the number of bits of the event data EV may be other than eight.

The command data CM indicates a transmission request of the next event data EV, and is "00000000""0" according to the order of the requested event data EV.
00000001 "" 00000010 "" 000000 "
11 ". Command data CM for transmitting the situation
Indicates a normal communication end “0FFн”, a command interpretation error abnormal end “0E0н”, and a timeout abnormal end “0E”.
Eн ”.

The event data EV may include events such as tempo, rhythm, effect, modulation, quantization, key scaling, and the like. The communication control data TC includes a plurality of data orders, a destination, and a transmission destination. The communication condition (protocol) such as the source, the number of transmission units, the number of data bytes, the data bit length, the data communication speed, and the method of error detection may be indicated. The event data EV and the command data CM are stored in the ROMs 101 and 107.
Included in the program stored in the RAM 10
2, 108, and may be rewritten as needed.

The transmission and reception of the event data EV and the command data CM are performed by the main CPU 103 and the master CP.
Not only during U301, but also between electronic musical instruments, sequencers, computers, rhythm machines, tone generators,
The processing may be performed among the envelope generator, the address controller, the key assigner, the tone controller, the touch response controller, the quantization controller, the modulation controller, the effect controller, the program controller, the interface, and the sound system. The number of data communication bits may be 16 bits other than 8 bits, 32 bits, or the like.

The transmission and reception of the event data EV and the command data CM are executed in a main routine of music processing of the main CPU 103 and the master CPU 301 described later. Therefore, since it is not executed in the interrupt processing,
The communication processing is always executed in a predetermined order in each processing, and the communication processing is executed stably and smoothly. Further, since the communication control data TC is transmitted in parallel with the data in the event data EV, there is no useless empty bit in the data communication bits, and the entire system can be used effectively. Further, since the communication control data TC and the data in the event data EV are transmitted at the same time, the processing according to the communication control data TC and the processing according to the data in the event data EV are performed simultaneously or within a short time. Thus, processing according to the event is executed quickly and smoothly.

<< 5 >> Master Tone Generator 105 FIG. 5 shows the master tone generator 105 and its peripheral circuits. The address bus controller 304 and the data bus controller 305 are controlled by the master CPU 301.
Through the interface unit 203 and the ROM 10
7 or RAM 108 is accessed. In addition, the tone generator 303 outputs R through an address bus controller 304 and a data bus controller 305.
The tone waveform data MW of the OM 107 is read out in a time-division manner. The read address data RD is frequency number data accumulated for each time-division channel in the tone generator 303.

In the address bus controller 304, the address bus 115 is connected to the master CPU 301,
Alternatively, the high impedance state connected or not connected to the tone generator 303 is switched in a time sharing manner. In the data bus controller 305, the high impedance state in which the data bus 116 is connected to the master CPU 301 or connected to or not connected to the tone generator 303 is switched in a time sharing manner. In the high impedance state, master CPU 301 and tone generator 303 are connected.

The connection between the address bus controller 304 and the data bus controller 305 is switched by the bus timing controller 302. That is, the bus timing controller 302 has a master clock signal MCK and a master reset signal M-RST.
Alternatively, the slave reset signal S-RST is supplied and converted, whereby the selection switching signal is supplied to the address bus controller 304 and the data bus controller 305. As a result, the buses 115 and 116 and the master CPU 3
01, and connection and disconnection between the buses 115 and 116 and the tone generator 303 are switched.

Via the address bus controller 304, the master CPU 301 or the tone generator 30
3 sends address data to the address bus 115,
It is not sent in the opposite direction. However, data is transmitted bidirectionally between the master CPU 301 or the tone generator 303 and the data bus 116 via the data bus controller 305.

The tone generator 303 includes 12
A tone generation system (oscillator) for the channels is formed by time division processing, and the tone is generated polyphonically. The RAM 108 has an assignment memory 306. The assignment memory 306 stores a total of 24 pieces of data relating to musical sound data assigned to each channel of the time-division processing for each channel and for each of the master tone generator 105 / slave tone generator 106.

The stored data includes the timbre channel number data, the timbre number data, the upper two bits read address data RA (extended address data),
Lower read address data (not shown), key number data, touch data (velocity data), volume data, pitch data, time-division channel number data TC,
Master / slave bit signal M / S, etc. Master/
The slave bit signal M / S indicates whether the tone generation source is the master tone generator 105 (“0”) or the slave tone generator 106 (“1”), that is, indicates the distinction between circuits. When these data are the same in some channels and master / slave, they may be omitted in order to make the storage system efficient.

The ROM 107 stores tone waveform data MW corresponding to a plurality of types of timbres. The plurality of types of timbres include waveform shapes (e.g., piano, violin, flute, drum, etc., sine waves, triangular waves, rectangular waves, etc., organ types, parkas types, etc., envelope waveforms, etc.). All or part of each waveform until the end of sounding), various spectral components, and various formants. Each tone of the tone waveform data MW is selected based on the upper two-bit data of the read address data RA, and each point of the selected tone waveform data MW is the lower 18-bit data of the read address data RA, that is, the above-described accumulated data. The frequency is read out based on the frequency number data. The tone waveform data MW of the plurality of tones are sequentially read out in a time-division manner, and the master tone generator 105 and the slave tone generator 106
To generate music data.

The slave tone generator 106
Also has the same configuration as master tone generator 105. However, this slave tone generator 106
Then, the master CPU 301 does not operate. Therefore, only in this slave tone generator 106, the master CP
U301 may not be provided. Of course,
In the slave tone generator 106, the master CPU
301 may operate to execute the same time-division processing as the master tone generator 105 described later.

<< 6 >> Bus Timing Controller 30
2. Address bus controller 304 and data bus controller 305 FIG. 6 shows the bus timing controller 302, address bus controller 304, and data bus controller 305. The address data AD from the master CPU 301 is supplied to the address bus 115 via a buffer 401, and is supplied to the tone generator 30.
3 is supplied to the address bus 115 via the buffer 402. The address data AD from the master CPU 301 to the tone generator 303 is stored in the buffers 401 and 402.
Sent through.

Data from the master CPU 301 is supplied to the data bus 116 via a buffer 403, and data from the data bus 116 is supplied to the master CPU 301 via the buffer 403. Further, the data from the tone generator 303 is supplied to the data bus 116 via the buffer 404, and the data from the data bus 116 is supplied to the buffer 404.
Is supplied to the tone generator 303 via the.

The data from the master CPU 301 to the tone generator 303 is stored in the buffer 403.
And 404, the tone generator 303
Is sent to the master CPU 301 via the buffers 403 and 404. These are all performed exceptionally at the CPU connection timing described later, and only in this case, the buffers 403 and 404 are opened simultaneously. In this case, for example, the NAND gate 40 described below
An OR gate is provided between the inverter 7 and the inverter 405,
A control signal from the master CPU 301 is input to the OR gate.

A clock signal φ2 is supplied to the buffers 401 and 403 via a NAND gate 406 as a gate signal. Thus, when the clock signal φ2 is at a high level, the master CPU 301 and each bus 115,
The transfer of information to / from the IC card 116 becomes possible. The clock signal φ2 is supplied as a gate signal to the buffers 402 and 404 via the inverter 405 and the NAND gate 406, and the clock signal φ4 is supplied as a gate signal via the NAND gate 407 to the buffers 402 and 404.
Thus, when the clock signal φ2 is at a low level and the clock signal φ4 is at a high level, information can be transferred between the tone generator 303 and each of the buses 115 and 116.

The NAND gate 406 is supplied with a master / slave signal. The master / slave signal is at a high level in the master tone generator 105 and at a low level in the slave tone generator 105. As a result, in the slave tone generator 105, the buffers 401 and 403 are always closed, and the CPU is disabled. It is enabled.

The clock signals φ2 and φ4 are not signals from the clock generator 204 described above, but from the clock generator 408 in the bus timing controller 302. The clock generator 408 has the same configuration as the clock generator 204. This clock generator 408 includes a master reset signal M-RST and a slave reset signal S-RS.
T is given with one cycle of the clock signal φ3 (half cycle of φ4), that is, shifted by a division time of a half channel. Therefore, the connection time between the buses 115 and 116 and the tone generator 303 of the slave tone generator 106 does not overlap with the connection time between the buses 115 and 116 and the master CPU 301 / tone generator 303 of the master tone generator 105. As a result, the address bus 11
5 and the data bus 116 can be commonly used by the master tone generator 105 and the slave tone generator 106.

The time when the buffers 401 and 403 are opened corresponds to "C" of the master (M) in FIG. 7 described below, and the time when the buffers 402 and 404 are opened in FIG. Of the master (M) and “T” of the slave (S), and all the buffers 401
When 404 is closed, it corresponds to "Z" of the master (M) in FIG. 7 described below, and the tone generator 303 and the master CPU 301 are disconnected from the address bus 115 and the data bus 116.

At the time of "C", the master CPU 301
Of the event data EV, the upper read address data RA to the extended address generator 205, the master / slave bit signal M / S, the time division channel number data CN, and the like are set. At the time of “T”, the tone waveform data M in the ROM 107 by the tone generator 303 / slave tone generator 106
Reading of W is performed. Tone generator 303 for frequency number data / slave tone generator 1
The setting to 06 is executed in the above “C”.

<7> Time Chart of Various Signals FIG. 7 shows a time chart of various signals in the electronic musical instrument. The clock signal φ2 is equal to the master clock signal MC.
K is obtained by dividing the frequency by 16. The clock signal φ4 is
The clock signal φ2 is obtained by dividing the frequency by 4.

The master (M) shown in FIG.
5 shows the circuit of the master tone generator 105 connected to the data bus 116 and the data bus 116. “C” indicates that the master CPU 301 of the master tone generator 105
"T" indicates that the tone generator 303 of the master tone generator 105 is connected to the buses 115 and 11;
6 is connected. “Z” indicates a high impedance state in which no connection is made. Such connection switching is performed in the address bus controller 304 and the data bus controller 305 by the bus timing controller 302 based on the clock signals φ2 and φ4 and the master reset signal M-RST as described above.

The slave (S) shown in FIG.
15 shows a connection state between the data bus 15 and the data bus 116 and the tone generator 303 of the slave tone generator 106. “T” and “Z” are as described above. As shown in the upper part of FIG. 7, when a reset signal is applied to the master tone generator 105 and the slave tone generator 106 at the same timing, both the tone generators 105,
Since 106 has the same configuration, the connection time between the buses 115 and 116 and the tone generator 303 of the slave tone generator 106 and the connection time between the buses 115 and 116 and the master CPU 301 / tone generator 303 of the master tone generator 105 are: Overlap.

On the other hand, as shown in the middle stage of FIG. 7, the master reset signal M-RST and the slave reset signal S-
If the RST is shifted by one cycle of the clock signal φ3 (φ4 half cycle), that is, by a division time of a half channel, the following is obtained. That is, the buses 115 and 116 and the tone generator 303 of the slave tone generator 106
And the connection time between the buses 115 and 116 and the master CPU 301 / tone generator 303 of the master tone generator 105 does not overlap. Therefore,
The address bus 115 and the data bus 116 can be commonly used by the master tone generator 105 and the slave tone generator 106.

The clock signal φ 4 is supplied to the connection (high level) of the tone generator 303 of the master tone generator 105 and to the slave tone generator 106
(Low level). The clock signal φ2 corresponds to the connection (high level) of the master CPU 301 and the connection (low level) of the tone generator 303.

Therefore, the switching of connection / disconnection of "C", "T", and "Z" of the master (M) and the slave (S) is periodically performed based on the clock signals φ2, φ3, φ4 and the like. It is performed in a time-sharing manner. Also, the time lag between the master reset signal M-RST and the slave reset signal S-RST is equal to the switching time of each connection / disconnection of “C”, “T” and “Z” of the master (M) and the slave (S). 4 times. If the division time of “C” and “Z” is omitted, the quadruple can be doubled and quadrupled.

The tone generators 105/106
May be two or more. In this case, the division time for one channel is 3 of one cycle of the clock signal φ3.
The division time is divided into three, four,..., And connection / non-connection of each tone generator is performed. The above connection / non-connection switching control is performed by the tone generators 105/106 and the bus lines 115, 1
CPU, address generator,
An assignment memory, envelope generator, key assigner, tone controller, touch response controller, quantize controller, modulation controller, effect controller, sequencer, program controller (counter), interface, sound system, bus line, etc. may be used.

The clock signals φ5 and φ6 are obtained by dividing the frequency of the clock signal φ4 by three. Both signals φ5, φ6
Indicates that the high-level section is shifted. The clock signal φ7 is
The clock signal φ6 is obtained by dividing the frequency by two. The clock signal φ8 is obtained by dividing the frequency of the clock signal φ7 by two.

"Channel (OSC)" in FIG. 7 indicates the number of the time division channel processed in the tone generator 303 of the master tone generator 105 and the slave tone generator 106. The channel numbers correspond to the clock signals φ5, φ6, φ7,
Each of φ8 is the first bit, the second bit, the third bit,
Corresponding to the fourth bit of the 4-bit data, the channel switching of the time-division processing is controlled based on the clock signals φ5, φ6, φ7, φ8.

<< 8 >> Clock Generator 204 FIG. 8 shows the clock generator 204. The master clock signal MCK is input to the clock terminal of the D-type flip-flop 601, and the inverted Q terminal is connected back to the D terminal. Therefore, the master clock signal M
Each time CK goes high, flip-flop 601
Is output, and the sub-master clock signal SMCK obtained by dividing the master clock signal MCK by 2 is output from the Q terminal of the flip-flop 601. The inverted signal of the sub master clock signal SMCK from the inverted Q terminal of the flip-flop 601 is also supplied to the buffers 602 and 60.
2 is input to the clock terminal CK of the counter 603.

The counter 603 counts the inverted signal of the sub master clock signal SMCK, and outputs the inverted signal of the sub master clock signal SMCK 2, 4, 8, 16
The divided clock signals φ0, φ1, φ2, φ3
Then, an inverted signal of each clock signal is output.

The carry-out signal C of the counter 603
OUT is a signal which becomes one pulse every one cycle of the clock signal φ3.
The signal is input to the J terminal and the K terminal of the K-type flip-flop 605. Further, the sub master clock signal SM
The inverted signal of CK is input to the clock terminal of the flip-flop 605. Therefore, the carry-out signal CO
Each time the UT goes high, the flip-flop 605
Is inverted, and the clock signal φ3 obtained by dividing the clock signal φ3 by 2 is output from the Q terminal of the flip-flop 605.
4 is output, and an inverted signal of the clock signal φ4 is output from the inverted Q terminal.

The clock signal φ4 and the carry-out signal COUT are supplied to AND gates 609 and 61, respectively.
0, 611. For this reason, the AND gate 60
From 9, 610, and 611, signals that become one pulse are output every one cycle of the clock signal φ4. However, since a clock signal φ6 described later is also input to the AND gate 609, the one-pulse signal is output only when the clock signal φ6 is at a high level. As a result, the one-pulse signal is output every cycle of the clock signal φ6. Is output.

Since the inverted signal of clock signal φ6 is also input to AND gate 610, the one-pulse signal is output only when clock signal φ6 is at a low level. Further, the output of the NAND gate 608 is also input to the AND gate 611. This NAND gate 60
8, the inverted signals of the clock signals φ5 and φ6 are input. Therefore, the one-pulse signal is output from the AND gate 611 only when the clock signal φ5 or φ6 is at a high level.

The signal from the AND gate 610 is J
The inverted signal of the sub master clock signal SMCK is input to the J terminal and the K terminal of the K type flip-flop 606, and is input to the clock terminal of the flip-flop 606. Therefore, when the clock signal φ6 is at a low level, the output of the flip-flop 606 is inverted every cycle of the clock signal φ4, and as a result, the flip-flop 6
A clock signal φ5 obtained by dividing the clock signal φ4 by 3 is output from the Q terminal 06, and an inverted signal of the clock signal φ5 is output from the inverted Q terminal.

The signal from the AND gate 611 is J
The inverted signal of the sub master clock signal SMCK is input to the J terminal and the K terminal of the K type flip-flop 607, and is input to the clock terminal of the flip-flop 607. Therefore, when the clock signal φ5 or φ6 is at a high level, the output of the flip-flop 607 is inverted every cycle of the clock signal φ4, and as a result, the clock signal φ4 becomes 3 from the Q terminal of the flip-flop 607.
The divided clock signal φ6 is output, and an inverted signal of the clock signal φ6 is output from the inverted Q terminal.

The signal from the AND gate 609 is input to a T terminal of the counter 604, and an inverted signal of the sub master clock signal SMCK is input to a clock terminal. Therefore, counting is permitted for each cycle of the clock signal φ6, and the clock signals φ7, φ8, φ9, φA obtained by dividing the clock signal φ6 by 2, 4, 8, 16 are:
An inverted signal of each clock signal is output.

The counters 603 and 604 and the flip-flops 601, 605, 606 and 607 have an internal reset signal RST from the reset controller 206.
Is supplied and reset. This internal reset signal R
ST is output in response to an external reset signal RESET from the external reset circuit 117.

<9> Extended Address Generator 205 FIGS. 9 to 13 show the extended address generator 2 of negative logic.
05 is shown. The extended address generator 205 receives, from the assignment memory 306 of the RAM 108, the higher-order read address data RA of the tone waveform data MW of the ROM 107, the time division channel number data CN for reading the tone waveform data MW, and the master / Slave bit signal M / S is supplied via data bus 116.

The time division channel number data CN
Indicates a channel of the time division processing system formed in the tone generator 105/106. In the master / slave bit signal M / S, as described above, the tone generation source is the master tone generator 105 (“0”) or the slave tone generator 106 (“1”).
, That is, indicates the distinction of the circuit.

The upper read address data RA, the time division channel number data CN, and the master / slave bit signal M / S are transmitted to the master CPU 301 by the master CPU 301.
It is read from the assignment memory 306 of M108. In the extended address generator 205, the higher-order read address data RA is output and sent to the ROM 107 during the switching division time according to the time-division channel number data CN and the master / slave bit signal M / S, and the tone waveform data MW is read. It is.

The upper read address data RA, the time division channel number data CN, and the master / slave bit signal M / S may be output from the tone generator 303 or the slave tone generator 106 of the master tone generator 105. In this case, the above assignment memory is provided in the tone generator 303 or the slave tone generator 106. The time-division channel number data CN and the master / slave bit signal M / S correspond to the clock signals φ5 to φ8 and φ4 when data from a channel counter (not shown) or upper read address data RA is sent. May be diverted.

Information D20-D on data bus 116
27, the upper two bits D26 and D27 (DB6, D
B7), the upper read address data RA is supplied, and the lower four bits D20 to D23 (DB0 to D23)
B3), the time-division channel number data CN
Is supplied. The fifth bit D24 (DB4) is a master / slave bit signal M / S and the like.

The upper read address data RA (D
B6, DB7) are latched by any of the 24 2-bit latches 801a to 1101f shown in FIGS. Of these 24, 2-bit latches 801a-9
Twelve 01f are slave tone generators 106
, The higher read address data RA from
In the twelve 2-bit latches 1001a to 1101f, higher-order read address data RA from the slave tone generator 106 is set.

Each of the twelve 2-bit latches corresponds to twelve time-division channels.
The higher-order read address data RA of the tone waveform data MW is set in a 2-bit latch corresponding to the W time-division channel. The 2-bit latch to be set is designated by the time-division channel number data CN (D
B0 to DB3).

The time division channel number data CN and the master / slave bit signal M / S (DB0 to D
B4) represents five D-type flip-flops 701a.
701e are input to and stored in the D terminal. The Q outputs and inverted Q outputs of the flip-flops 701a to 701e are supplied to the latch signals MEA0 to MEA via the NAND gate 703 and the OR gate 704 of the decoder circuit 702.
AB and SEA0 to SEAB are supplied to the 2-bit latches 801a to 1101f.

The inverted signal of the write signal W generated from the master CPU 301 and a part of the address data on the address bus are converted by a decode (not shown),
It is output as a time division channel designation signal WRA. The inverted signal of the time division channel designation signal WRA is supplied to the clock terminals C of the flip-flops 701a to 701e.
K is supplied as a latch signal. Thus, when the master CPU 301 writes to a specific address,
The number of the time-division channel into which the extension address data is to be written is automatically designated, and as a result, the time-division channel number data CN and the master / slave bit signal M /
S is stored.

The inverted signal of the write signal W generated from the master CPU 301 and a part of the address data on the address bus are converted by a decode (not shown) and output as an extended address write signal WRD. The inverted signal of the extended address write signal WRD is supplied to the OR gates 704.

A circle in the decoder circuit 702 is an abbreviation symbol indicating that a horizontal line is input to the AND gate 703 along a vertical line. For example, the time division channel number data CN and the master / slave bit signal M / S (D
B0 to DB4) are the channel “0” and the master “0”
Then, the above-mentioned 24 latch signals MEA0-SEAB
Among them, only the latch signal MEA0 becomes low level,
The upper read address data RA is a 2-bit latch 80
Set to 1a.

The time-division channel number data CN and the master / slave bit signal M / S (DB0 to DB
4) If the channel is “10” and the slave is “1”, of the 24 latch signals MEA0 to SEAB, only the latch signal SEAA is at the low level, and the upper read address data RA is the 2-bit latch 1101.
Set to e.

As described above, the higher-order read address data RA set in the 2-bit latches 801a to 1101f corresponding to the time-division channel number data CN and the master / slave bit signal M / S are supplied to the selector 8
02a to 802d, 902a to 902d, 1002a to
1002d, 1101a to 1101d, 803a, 80
3b, 903a, 903b, 1003a, 1003b,
1103a, 1103b, 804a, 804b, 100
4a and 1004b are selectively output at the switching division time according to the time division channel number data CN.

The clock signals φ5 to φ8 are supplied to the selectors 802a to 1104b as select switching signals. The clock signals φ5 to φ8 are
As shown in FIG. 7, the time division channel number data CN
It corresponds to. Therefore, each higher-order read address data RA is selectively output in the switching division time according to the time division channel number data CN.

For example, in the high-order read address data RA of the 2-bit latch 801a, the time division channel number data CN corresponds to the channel “0”, and the clock signals φ5 to φ8 are “0000”, that is, the time division channel “ Output when it is 0 ". Also, the upper read address data RA of the 2-bit latch 1101e
Indicates that the time-division channel number data CN corresponds to the channel “10”, and the clock signals φ5 to φ8
Is "1010", that is, the time division channel "10".

The high-order read address data RA selected in accordance with the time-division channel in this manner is selected and output by the selectors 805a and 805b at a division time corresponding to the master / slave bit signal M / S. The clock signal φ4 is supplied to the selectors 805a and 805b as a select switch signal. The clock signal φ4 is connected to the master tone generator 105 (“1”) and the slave tone generator 106 as shown in FIG. ("0").
Therefore, the higher-order read address data RA is selectively output in the switching division time according to the master / slave bit signal M / S.

Further, the selectors 805a and 805b
From the address bus 11 via AND gates 806a and 806b.
5 are output as upper bits A18 and A19 of the ROM
The data is sent to 107 and the tone waveform data MW is read. The clock signal φ2 is inverted and supplied to the AND gates 806a and 806b. The clock signal φ2 is connected to the master CPU 301 (“1”) and the tone generator 303 (“1”) as shown in FIG. 0 "). Therefore, the upper read address data RA is output in the switching division time according to the tone generator 303.

Thus, master tone generator 10
5 / Even if the number of bits of the address data of the slave tone generator 106 is smaller than the number of bits of the address data for the ROM 107, the missing bit data can be output from the data bus 116 to the address bus 115 via the extended address generator 205. it can. In this case, it is possible to synchronize the switching division time of the output of each divided address data.

The internal reset signal RST from the reset controller 206 is supplied to the flip-flop 701
a to 701e are supplied to the 2-bit latches 801a to 1101f and reset. This internal reset signal RS
T is output in response to an external reset signal RESET from the external reset circuit 117.

The number of bits of the upper read address data RA, the time division channel number data CN, and the master / slave bit signal M / S are not limited to 2, 4, and 1, but can be variously changed. Accordingly, the number of types of information to be read, the number of time-division channels, and the number of circuits to be controlled change. Further, the read musical tone waveform data MW is read out.
Means semiconductor memory such as RAM, CD-R
It may be stored in an optical memory such as an OM / RAM or the like, or may be stored in a plurality of memories. The number of tone generators may be one or more than two in addition to two for the master / slave.

The information read by the read address data RA includes, in addition to the musical tone waveform data MW, information such as envelope data, modulation data, effect data, rhythm data, automatic performance data, and programs read in a time-division or circuit-by-circuit manner. Anything is fine. Further, the divided and controlled data includes, in addition to the read address data RA, write address data, tone waveform data, envelope data, pitch data, timbre data, touch data, volume data, tempo data, quantize data, Any type of information, such as modulation data, effect data, rhythm data, automatic performance data, programs, etc., may be used as long as it is controlled in a time-division or circuit-specific manner.

As the data to be divided and controlled, the plurality of types of data are sent from a plurality of circuits or one circuit, or the plurality of types of data are transmitted to a plurality of circuits or one circuit.
May be sent to one circuit. Further, the generation sources of the divided and controlled data are, in addition to the master tone generator 105 / slave tone generator 106,
Any of a CPU, an address generator, an assignment memory, an envelope generator, a key assigner, a tone controller, a touch response controller, a quantize controller, a modulation controller, an effect controller, a sequencer, a program counter, an interface, and a sound system may be used.

<< 10 >> Reset Controller 206 FIG. 14 shows the reset controller 206. An external reset signal RESET from the external reset circuit 117
Is input to a D terminal of a D-type flip-flop 1201 via a buffer 1204. The Q output of the flip-flop 1201 is input to the D terminal of the flip-flop 1202.

The flip-flops 1201 and 1202
And the external reset signal RESET from the buffer 1204 are output as the internal reset signal RST via the AND gate 1203. On the other hand, the clock signal φ8 is supplied to clock terminals of the flip-flops 1201 and 1202. Therefore,
When the rising edge of the clock signal φ8 is supplied twice from the output of the external reset signal RESET, the internal reset signal RST is output.

This internal reset signal RST is input to the D terminal of a D type flip-flop 1206. On the other hand, an inverted signal of the sub master clock signal SMCK and clock signals φ0, φ1, φ
2, φ3, φ6, φ7, φ8 and an inverted signal of the clock signal φ4 are input. Thereby, NAND gate 1
205, the half cycle of the clock signal φ4 from the down edge of the clock signal φ8 and the submaster clock signal SM
At the moment when a half cycle of CK returns, the submaster clock signal S
An inverted pulse signal having a width of a half cycle of MCK is output.

This inverted pulse signal is input to the clock terminal of the flip-flop 1206. Therefore, at the moment when the clock signal φ4 returns a half cycle from the down edge of the clock signal φ8, the internal reset signal RST is held at the Q output of the flip-flop 1206.

The Q output of the flip-flop 1206 is input to a D terminal of a D-type flip-flop 1207, and a clock signal φ3 is input to a clock terminal of the flip-flop 1207. Therefore, the internal reset signal RST held at the Q output of the flip-flop 1206 is held at the Q output of the flip-flop 1207 with a delay of one cycle of the clock signal φ3.

The Q output of the flip-flop 1207 is input to the D terminal of the D-type flip-flop 1208, and the clock signal φ3 is also input to the clock terminal of the flip-flop 1208. Therefore, the internal reset signal RST held at the Q output of the flip-flop 1207 is held at the Q output of the flip-flop 1208 with a delay of one cycle of the clock signal φ3.

The Q output of the flip-flop 1207 is output as the slave reset signal S-RST via the buffers 1209 and 1209 and sent to the slave tone generator 106. The Q output of the flip-flop 1208 is connected to a buffer 1209,
1209, the master reset signal M-RST
And the master tone generator 105
Sent to

Thus, master reset signal M-RST
Are output one clock cycle of the clock signal φ3 (half cycle of φ4), that is, a half channel divided time later than the slave reset signal S-RST. Therefore, the bus 115,
Connection time between the tone generator 303 and the tone generator 303 of the slave tone generator 106;
And master CPU 30 of master tone generator 105
The connection time with the 1 / tone generator 303 does not overlap. Therefore, the address bus 115 and the data bus 1
16 can be commonly used by the master tone generator 105 and the slave tone generator 106.

Note that the master reset signal M-RST
The slave reset signal S-RST may be output periodically. In this case, the detection signal of the rising edge of the clock signal φ4 becomes the master reset signal M-RST, and the detection signal of the falling edge of the clock signal φ4 becomes the slave reset signal S-RST. The inverted signal of the internal reset signal RST is supplied to the flip-flop 120
1, 1202, 1206, 1207, and 1208 are reset.

<< 11 >> Register group (RAM 102, 10
8) FIG. 15 shows a register group provided in the RAM 102 and the RAM 108. Stack point data SP, sp are stored in the stack point registers S, s.
The stack point data SP and sp are stored in the RAM 10
2, the latest address of the RAM 108 where various processing data is stored.

The transmission registers X and x store event data EV to be transmitted and command data CM to be transmitted. The received registers A and a store the received command data CM and the received event data EV. The communication buffer BUF, buf stores four event data EV to be transmitted or four event data EV received. In the order register Y, order data OD indicating each designated address of the communication buffer BUF is set. On the RAM 108 side, the transmission register x plays the same role as the order register Y.

Return value registers RTV, rtv, communication register CDM, and temporary register AL store various intermediate processing data. In the timer counter T,
A time count is performed, thereby detecting a timeout.

<< 12 >> Main Routine of Main CPU 103 FIG. 16 is a flowchart of a main routine executed by the main CPU 103. First, the main CPU
The operation mode of 103 is set to hexadecimal (step S
101), the stack point data SP of the point register S is reset to "0FFн" (step S10).
2) The input / output circuit 100, the RAM 102, the interface unit 203, and other circuits are initialized (step S103).

Next, the event data EV is read from the event queue register EQ of the input / output circuit 100, and written into the return value register RTV (step S1).
04). If the event data EV is a no event of "0н" (step S105), the above-mentioned step S10
Returning to No. 4, if it is not a no event, the event data E
V is sent to master tone generator 105 / slave tone generator 106 to execute event processing (step 106).

<< 13 >> Event Processing (Step S10)
6) FIG. 17 shows a flowchart of the event processing of step S106 executed by the main CPU 103. First, the event data EV of the return value register RTV
Is set in the transmission register X, and the event data E
The command data portion of V is returned to the return value register RTV (step S201), and the command data portion of the event data EV is transferred to the transmission register X (step S202).

Then, the command data portion of the event data EV of the transmission register X is identified (step S2).
03). If the event data EV indicates a panel event of “2 н”, panel event processing is executed (step S204). If the event data EV indicates a key event of “4 н”, key event processing is executed (step S205). If the event data EV indicates a reception event of “6н”, reception event processing is executed (step S206). If the event data EV is a no event of "0н", nothing is executed.

<< 14 >> Panel event processing, key event processing, reception event processing (steps S204 to S20)
6) FIG. 18 shows a flowchart of the panel event processing, key event processing, and reception event processing of steps S204 to S206 executed by the main CPU 103. First, the event data EV is converted into the data format shown in FIG. 4 (step S301),
The data is written into the communication buffer BUF (step S30).
2). Then, the converted event data EV in the communication buffer BUF is sent to the master tone generator 105 or the slave tone generator 106 via the transmission / reception control circuit 104 (step S303). The processing described above is the same in any of the panel event processing, the key event processing, and the reception event processing.

<< 15 >> Event Transmission Processing (Step S3
03) FIG. 19 shows a flowchart of the event data EV transmission process of step S303 executed by the main CPU 103. First, interface unit 2
The command data CM from the master CPU 301 of the buffer 503 of No. 03 is read and written to the reception register A (step S401). When the command data CM of the reception register A is "0FFн", that is, the master CP
If the command is not a command for terminating normal communication from U301, the interface unit 203 in step S401 described above.
Is repeated (step S402).

If the command data CM indicating the normal end of the communication of "0FFн" has been sent, the order register Y is cleared (step S403), and the first event data in the communication buffer BUF corresponding to the order data OD of the order register Y is cleared. The EV is read and the interface unit 203
(Step S404).

Next, the interface unit 203
Command data CM of the buffer 504 is read out,
The received command data CM is written into the reception register A (step S405), and the received command data CM
Is compared with the command data CM (step S40).
6). If they do not match with each other and a read error occurs, the interface unit 2 of steps S404 and S405 is again executed
The process of taking out the command data CM from step 03 is repeated.

If they match, the received command data CM of the receiving register A is equal to the order data OD of the order register Y, that is, the event data EV is transmitted without error, and the transmission of the next event data EV is requested. It is determined whether or not it has been performed (step S407).
If the request has been made, the order data OD of the order register Y is incremented by 1 (step S410), and the transmission processing of the event data EV in steps S403 to S407 described above is repeated. When one block, that is, four event data EVs are sent and the order data OD of the order register Y becomes “4４”, this event data EV
Is returned.

In step S407, if the command data CM of the receiving register A is not equal to the order data OD of the order register Y, or if the command data CM of the receiving register A is "0E0н", that is, a command interpretation error (step S407). S408) If the command data CM is “0EE н”, that is, if it is time-out (step S409), the transmission processing of the event data EV in steps S403 to S407 is repeated from the beginning. In steps S408 and S409, if the command data CM is neither a command interpretation error nor a timeout, other processing is performed (step S408).
412).

Note that, in addition to the above-described processing, the main CPU 103 also executes an interval interrupt routine and a reception interrupt routine. This interval interruption routine is performed periodically, and detection of ON / OFF of a key and a panel switch is performed, and event data EV corresponding to the detection is set in an event queue register EQ of the input / output circuit 100.

The reception interrupt routine is executed when serial data such as MIDI data is received via the input / output circuit 100. The serial data is decoded, converted into event data EV shown in FIG. It is set in the event queue register EQ of the input / output circuit 100.

<< 16 >> Main Routine of Master CPU 301 FIG. 20 is a flowchart of a main routine executed by the master CPU 301. First, the master CP
The arithmetic mode of U301 is set to hexadecimal (step T101), the stack point data sp of the stack point register s is reset to "0FFн" (step T102), and the RAM 108, the interface unit 203, and other circuits are initialized. (Step T103).

Next, a handshake process is performed to match the input / output timing with the main CPU 103 (step T104), and the command data CM of the normal communication end of "0FFн" is set in the communication register COM (step T105). . And
An event reception process for reading out the event data EV from the buffer 502 of the interface unit 203 is executed (step T106), and the event data EV of the return value register rtv is set in the reception register a (step T107).

The event data EV of the reception register a
Is not a no event of “0н” (step T10
8) A process corresponding to the event data EV is executed (step T109). If the event data EV is "0"
If the event is "н", the process of step T109 is not performed.

Next, the communication register CO
The M command data CM is sent to the latch 504 of the interface unit 203 (step T110),
The event data EV of the communication buffer buf is sent to the tone generator 303 and the slave tone generator 106 of the master tone generator 105 (step T111), and priority conditions for channel assignment are set (step T112).
To T112 are repeated.

<< 17 >> Event Reception Processing (Step T1)
06) FIG. 21 shows a flowchart of the event data EV reception process of step T106 executed by the master CPU 301. First, the return value register rtv is set to “0”.
н "(step T201), the event data EV in the buffer 502 of the interface unit 203 is read out and set in the reception register a (step T202), and the event data EV and the event data EV in the buffer 502 are compared. If they do not match, and if there is a read error, the event data EV in the above steps T202 and T203 is again performed.
Is performed.

If they match, the logical product of the event data EV of the reception register a and "80", that is, the most significant bit data of the event data EV is extracted and set in the temporary register AL (step T204). ).
If the event data EV of the reception register a is not “0 н”, that is, if there is received data (step T205), the initial value of the time count data TM is set in the timer counter T (step T206), and the transmission register x is Cleared to "0н" (Step T2
07).

Next, the order data OD of the transmission register x
, The most significant bit data of the event data EV of the temporary register AL is set in the area of the communication buffer buf (step T208), and the order data OD of the transmission register x is "3н", that is, one block-all four. If the event data EV has not been sent yet (step T209), the order data OD of the transmission register x is sent to the latch 504 of the interface unit 203, and the transmission of the next event data EV is requested (step T212). .

If the time count data TM of the timer counter T has not yet reached "0н" and has not timed out (step T213), the event data EV in the buffer 502 of the interface unit 203 is read out and the reception register is read out. a (step T215), and the event data EV is compared with the event data EV in the buffer 502 (step T216).

If they match, the event data EV of the reception register a is set in the interface unit 203 (step T217), and the most significant bit data of the event data EV of the communication buffer buf according to the order data OD of the transmission register x. Is exclusive-ORed with the event data EV of the reception register a, only the most significant bit data of the event data EV is cleared and set in the reception register a (step T218).

Next, if they match, the reception register a
Of the event data EV and "80н", that is, the most significant bit data of the event data EV is extracted and set in the temporary register AL (step T21).
9), the event data EV of the reception register a is "0н"
, That is, if there is received data (step T22
0), the order data OD of the transmission register x is incremented by 1 (step T221), and the event data EV of the reception register a is transferred to the communication buffer buf via the temporary register AL.
It is set to.

In the step T209, the transmission register x
Is the order data OD of “3н”, that is, 4
If one event data EV has already been sent, the order data OD of the transmission register x is sent to the latch 504 of the interface unit 203 (step T21).
0), “1н” is set in the return value register rtv (step T211), and the main CPU 103 is notified that the transmission of the event data EV for one block has been completed. Also, in step T213, the timer counter T
If the time count data TM of "0EE" has reached "0н" and a timeout has occurred, "0EE" indicating a timeout has occurred.
н "command data CM is set in the communication register COM (step T214).

<< 18 >> Event execution processing (step T1)
09) FIG. 22 shows a flowchart of the event execution process of step T109 executed by the master CPU 301. First, the event data EV stored in the communication buffer buf is decrypted and set in a return value register rtv (step T301).
The decoded event data EV of v is set in the transmission register x (step T302).

Then, the event data EV of the transmission register x is identified (step T303). If the event data EV is "0н", "0E0" is stored in the reception register a.
The command data CM of the command decoding error of “н” is set (step T311).
Is further set in the communication register COM (step T318).

The event data EV is "2２".
Key-on / key-off event, key-on / key-off event
A key-off process is performed (step T304). If the event data EV is a tone color change event of "4н", tone color change processing is performed (step T305).
If the event data EV is a volume change event of "6н", a volume change process is performed (step T30).
6). If the event data EV is a pitch change event for each tone of "8н", a pitch change process for each tone is performed (step T307).

In step T304, the frequency number data corresponding to the key number data in the event data EV is set in the tone generator 303 or the slave tone generator 106 by the master CPU 301. Further, the upper read address data RA corresponding to the tone color data indicated by the tone channel in the event data EV and the lower read address data are set in the assignment memory 306 of the RAM 108 by the master CPU 301, or 2-bit latch 80 of extended address generator 205
1a to 1101f are set.

At this time, the time-division channel number data CN is transferred to the flip-flops 701a to 701 of the extension address generator 205 by the master CPU 301.
At the same time, the master / slave bit signal M / S is set in the flip-flop 701e by the master CPU 301. Step T305 above
Then, the tone color data corresponding to the tone channel is changed, and in step T306, the volume data is changed. In step T307, the frequency number data of the time-division channel being sounded in the tone channel is changed.

If the event data EV is an event for changing the entire pitch of "Aн", the entire pitch is changed (step T308). The above event data E
If V is the event of reinitialization of "Cн",
Re-initialization processing is performed (step T309),
Initialization processing of the RAM 108 and the interface unit 203 is performed (step T310). After each of the processes from T304 to T310, the command data CM of the communication end of “0FF” ”is set in the reception register a (steps T312 to T317), and the command data CM is further set in the communication register COM. (Step T318).

<19> Event Decryption Processing (Step T3)
FIG. 23 shows a flowchart of the event decoding process in step T301 executed by the master CPU 301. First, the first event data EV of the communication buffer buf is set in the reception register a (step T4).
01), if the event data EV of the reception register a is “80н”, that is, the event data EV of reinitialization (step T402), the reception register a
Event data EV for reinitialization of "0Cн"
Is set (step T403), and the event data EV is also set in the return value register rtv (step T408).

In the step T402, if the event data EV is not "80” ", the communication buffer buf
The event data EV indicating the type of the second event is set in the reception register a (step T404), and the logical product of the event data EV and “70н”, that is, the upper second to fourth bits of the event data EV Are extracted and set in the reception register a (step T405). Further, the event data EV of the reception register a is shifted to the lower side by 4 bits and set in the transmission register x (step T406). The event data EV is converted and set in the reception register a (step T407). This conversion is “000” →
“2н”, “011” → “4н”, “100” → “6
н ”,“ 110 ”→“ 8н ”,“ 111 ”→“ Aн ”, and these“ 2н ”,“ 4н ”,“ 6н ”,“ 8н ”
н "is identified in step T303 described above.

In addition to the above-mentioned processing, the processing of the interval interrupt routine is also executed by the master CPU 301. This interval interrupt routine is performed periodically, and is decremented unless the value of the time count data TM of the time counter T is negative. The present invention is not limited to the above embodiment, and can be variously modified without departing from the spirit of the present invention. For example, the extended address generator 205 is a RAM, and this RAM has a memory area for 12 channels for each master / slave, and stores the timbre number data (upper read address data RA) in the master CPU.
At 301, the data is written to the corresponding channel memory area. Then, as the read / write address data of the RAM, the clock signals φ4, φ5,
φ6, φ7, and φ8 are used, and the clock signal φ2 is used as the write / read signal W / R.
Embodiments of the present invention are as follows. [A] transmitting means for transmitting the music data and communication control information relating to the communication of the music data in parallel, and a first data bus through which the music data and the communication control information transmitted by the transmitting means are transmitted in parallel. Communication control means for receiving music data and communication control information sent in parallel via the first data bus, and for sending out the received music data and communication control information in parallel; and A second data bus to which music data and communication control information sent in parallel are sent in parallel; and music data and communication control information sent in parallel through this second data bus, Receiving means for performing music processing according to the communication control information and performing communication control according to the communication control information. Characteristic music information processing system.
[B] The music information processing system according to claim A, wherein the transmitting means is a CPU. [C] The music information processing system according to claim A, wherein the receiving means is a CPU. [D] The music information processing system according to claim B, wherein the processing of sending out the music data and the communication control information by the sending means is included in a main routine of music processing of the sending means.
[E] The music information processing system according to claim C, wherein the receiving process of the music data and the communication control information by the receiving unit is included in a main routine process of music processing of the receiving unit. [F] The music information processing system according to claim A, wherein the music data is divided and communicated a plurality of times, and the communication control information indicates the plurality of times. [G] The communication control means is a buffer.
The music information processing system as described.

[0139]

As described above in detail, according to the present invention, music data and communication control information relating to the communication of the music data are transmitted from the transmitting means via the data bus and the communication control means.
It was sent to the receiving means in parallel. Therefore, since the music data and the communication control information are transmitted in parallel, there are no useless empty bits in the data communication bits, and the whole system can be used effectively. Further, since the music data and the communication control information are transmitted at the same time, the processing according to the communication control information and the processing according to the music data are performed simultaneously or within a short time, and the entire processing is quickly and smoothly executed. And so on.

[Brief description of the drawings]

FIG. 1 is an overall circuit diagram of an electronic musical instrument.

FIG. 2 is a circuit diagram showing a transmission / reception control circuit 104;

FIG. 3 is a circuit diagram showing an interface unit 203.

FIG. 4 is a diagram showing the format of event data EV and command data CM.

FIG. 5 is a circuit diagram showing a master tone generator 105 and its peripheral circuits.

FIG. 6 illustrates a bus timing controller 302, an address bus controller 304, and a data bus controller 3.
It is a circuit diagram which shows 05.

FIG. 7 is a diagram showing a time chart of various signals in the electronic musical instrument. FIG. 3 is a circuit diagram showing an extended address generator 205.

FIG. 8 is a circuit diagram showing a clock generator 204.

FIG. 9 is a circuit diagram showing an extended address generator 205.

FIG. 10 is a circuit diagram showing an extended address generator 205.

FIG. 11 is a circuit diagram showing an extended address generator 205.

FIG. 12 is a circuit diagram showing an extended address generator 205.

FIG. 13 is a circuit diagram showing an extended address generator 205.

FIG. 14 is a circuit diagram showing a reset controller 206.

FIG. 15 is a diagram showing registers in RAMs 102 and 108.

FIG. 16 is a diagram showing a flowchart of a main routine executed by the main CPU 103.

FIG. 17 is a diagram showing a flowchart of an event execution process (step S106) executed by the main CPU 103.

FIG. 18 is a diagram showing a flowchart of panel event processing, key event processing, and reception event processing (steps S204 to S206) executed by the main CPU 103.

FIG. 19 is a view illustrating a flowchart of event data EV transmission processing (step S303) executed by the main CPU 103.

FIG. 20 is a diagram showing a flowchart of a main routine executed by the master CPU 301.

FIG. 21 is a view illustrating a flowchart of event data EV reception processing (step T106) executed by the master CPU 301.

FIG. 22 is a diagram showing a flowchart of an event execution process (step T109) executed by the master CPU 301.

FIG. 23 is a diagram showing a flowchart of an event decoding process (step T301) executed by the master CPU 301.

[Explanation of symbols]

100: input / output circuit, 103: main CPU, 10
Reference numeral 4: transmission / reception control circuit, 105: master tone generator, 106: slave tone generator, 109: master clock generator, 117: external reset circuit, 203: interface unit, 204, 40
8 Clock generator, 205 Extended address generator, 206 Reset controller, 301 Master CPU, 302 Bus timing controller, 3
03: tone generator, 304: address bus controller, 305: data bus controller, 306:
Assignment memory, 501, 504 ... latch, 40
1 to 404, 402, 503, 602, 1204, 12
09 ... buffer, 406, 407, 505-508 ... NAND gate, 608-611, 703, 704, 806
a, 806b, 1203 ... AND gate, 601, 60
5-607, 701a-701e, 1201, 120
2, 1206 to 1208... Flip-flop, 603,
604: counter, 702: decoder circuit, 801a-
1101f... 2-bit latch, 802a to 805b, 9
02a to 1103b: selector, S, s: stack point register, RTV, rtv: return value register, EQ ...
Event queue register, T… Timer counter, AL…
Temporary register, X, x ... transmission register, BUF, buf
... Communication buffer, A, a ... reception register, Y ... order register, COM ... communication register.

Claims (2)

(57) [Claims] A transmitting means for transmitting in parallel a plurality of divided pieces of music data and communication control information indicating an order of each of the divided pieces of music data; A first data bus to which each piece of communication control information is sent in parallel; a music data and each piece of communication control information sent in parallel via the first data bus; Communication control means for transmitting the respective pieces of communication control information in parallel; a second data bus through which the music data and the respective pieces of communication control information sent in parallel from the communication control means are transmitted; and a second data bus. , Each of the music data and the communication control information sent in parallel are received, and according to the respective communication control information, A music information processing apparatus comprising: a receiving unit that performs music processing. 2. A plurality of divided music data and communication control information indicating an order of each divided music data are sequentially sent out in parallel through a first data bus. Via the second data bus, receives each music data and each piece of communication control information sent in parallel through the second data bus, Music, which receives music data and communication control information sent in parallel via a data bus, and performs music processing according to the music data before division according to the communication control information. Information processing method.