JP2834866B2 - Manufacturing method of hybrid integrated circuit - Google Patents
Manufacturing method of hybrid integrated circuitInfo
- Publication number
- JP2834866B2 JP2834866B2 JP2196576A JP19657690A JP2834866B2 JP 2834866 B2 JP2834866 B2 JP 2834866B2 JP 2196576 A JP2196576 A JP 2196576A JP 19657690 A JP19657690 A JP 19657690A JP 2834866 B2 JP2834866 B2 JP 2834866B2
- Authority
- JP
- Japan
- Prior art keywords
- integrated circuit
- hybrid integrated
- manufacturing
- electron beam
- cured
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/01—Manufacture or treatment
- H10W72/0198—Manufacture or treatment batch processes
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/071—Connecting or disconnecting
- H10W72/073—Connecting or disconnecting of die-attach connectors
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/071—Connecting or disconnecting
- H10W72/075—Connecting or disconnecting of bond wires
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/851—Dispositions of multiple connectors or interconnections
- H10W72/874—On different surfaces
- H10W72/884—Die-attach connectors and bond wires
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W90/00—Package configurations
- H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
- H10W90/731—Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors
- H10W90/734—Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors between a chip and a stacked insulating package substrate, interposer or RDL
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W90/00—Package configurations
- H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
- H10W90/751—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires
- H10W90/754—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires between a chip and a stacked insulating package substrate, interposer or RDL
Landscapes
- Electric Connection Of Electric Components To Printed Circuits (AREA)
- Die Bonding (AREA)
Description
【発明の詳細な説明】 （イ）産業上の利用分野 本発明は混成集積回路の製造方法、特に電子線硬化型
の導電ペーストを用いた混成集積回路の製造方法に関す
る。The present invention relates to a method for manufacturing a hybrid integrated circuit, and more particularly to a method for manufacturing a hybrid integrated circuit using an electron beam-curable conductive paste.
（ロ）従来の技術 従来の混成集積回路の製造方法を第２図Ａ乃至第２図
Ｄを参照して詳述する。(B) Prior Art A conventional method for manufacturing a hybrid integrated circuit will be described in detail with reference to FIGS. 2A to 2D.
先ず第２図Ａに示す如く、アルミニウム等の金属基板
（11）の表面に陽極酸化により酸化アルミニウム薄層
（12）を設け、この酸化アルミニウム薄層（12）上に銅
箔を全面に貼り付け、所望のパターンにエッチングして
導電路（13）を形成している。First, as shown in FIG. 2A, an aluminum oxide thin layer (12) is provided on the surface of a metal substrate (11) made of aluminum or the like by anodic oxidation, and a copper foil is adhered on the entire surface of the aluminum oxide thin layer (12). The conductive path (13) is formed by etching into a desired pattern.
次に第２図Ｂに示す如く、所定の半導体素子を載置す
る位置の導電路（13）上に銀ペースト等の導電ペースト
（14）をスクリーン印刷して付着している。この導電ペ
ースト（14）はエポキシ樹脂ベースに潜在性硬化剤と銀
粒子を混ぜて形成され、150℃、２時間で熱硬化され
る。Next, as shown in FIG. 2B, a conductive paste (14) such as a silver paste is screen-printed and adhered on the conductive path (13) at a position where a predetermined semiconductor element is mounted. This conductive paste (14) is formed by mixing a latent curing agent and silver particles in an epoxy resin base, and is thermally cured at 150 ° C. for 2 hours.
更に第２図Ｃに示す如く、導電ペースト（14）上に半
導体素子（15）をダイボンディングする。Further, as shown in FIG. 2C, a semiconductor element (15) is die-bonded on the conductive paste (14).
更に第２図Ｄに示す如く、導電ペースト（14）を150
℃、２時間で熱硬化した後、所望の電極と導電路（13）
とをボンディング細線（16）で接続している。Further, as shown in FIG.
After thermosetting at 2 ℃ for 2 hours, desired electrodes and conductive paths (13)
And are connected by a thin bonding wire (16).
（ハ）発明が解決しようとする課題 斯上した従来の混成集積回路の製造方法では、導電ペ
ースト（14）の熱硬化に２時間も要し、工程の合理化が
できない問題点がある。(C) Problems to be Solved by the Invention In the above-described conventional method for manufacturing a hybrid integrated circuit, it takes two hours to thermally cure the conductive paste (14), and the process cannot be rationalized.
またこの導電ペースト（14）の熱硬化は必ず恒温槽内
で行う必要があり、連続生産を行うことができない問題
点があった。In addition, thermal curing of the conductive paste (14) must be performed in a constant temperature bath, and there is a problem that continuous production cannot be performed.
（ニ）課題を解決するための手段 本発明の斯上した諸々の問題点に鑑みてなされ、電子
線硬化樹脂ペースト（以下EBキュアペーストという。）
を用いることにより、従来の問題点を大幅に改善した混
成集積回路の製造方法を実現するものである。(D) Means for Solving the Problems In view of the above various problems of the present invention, an electron beam curing resin paste (hereinafter referred to as an EB cure paste) is provided.
The present invention realizes a method of manufacturing a hybrid integrated circuit, in which the conventional problems are greatly improved.
（ホ）作用 本発明に依れば、EBキュアペーストを電子線を用いて
硬化しているので、電子線の透過力が強く短時間に硬化
できる様になる。(E) Function According to the present invention, since the EB cure paste is cured by using an electron beam, the electron beam has a high penetrating power and can be cured in a short time.
（へ）実施例 本発明に依る混成集積回路の製造方法を第１図Ａ乃至
第１図Ｄを参照して詳述する。(F) Embodiment A method of manufacturing a hybrid integrated circuit according to the present invention will be described in detail with reference to FIGS. 1A to 1D.
先ず第１図Ａに示す如く、ポリイミドあるいはポリエ
ステル等の可撓性樹脂絶縁フィルム（１）の少なくとも
一面に銅箔を貼り付け、この銅箔を所望のパターンにエ
ッチングして導電路（２）を形成している。First, as shown in FIG. 1A, a copper foil is attached to at least one surface of a flexible resin insulating film (1) such as polyimide or polyester, and the copper foil is etched into a desired pattern to form a conductive path (2). Has formed.
次に第１図Ｂに示す如く、この導電路（２）上にEBキ
ュア銀ペースト（３）をスクリーン印刷等で付着してい
る。このEBキュア銀ペースト（３）は銀粒子のラジカル
重合型樹脂で形成され、電子線のエネルギー強度が紫外
線より十分に大きいため重合開始剤は添加されていな
い。Next, as shown in FIG. 1B, an EB-cured silver paste (3) is attached on the conductive path (2) by screen printing or the like. This EB-cured silver paste (3) is formed of a radical polymerization type resin of silver particles, and has no electron beam initiator because the energy intensity of the electron beam is sufficiently larger than that of ultraviolet rays.
更に第１図Ｃに示す如く、EBキュア銀ペースト（３）
上に半導体素子（４）をダイボンディングする。半導体
素子（４）はチップ状であり、その上面にはアルミニウ
ムの電極（５）が形成されている。Further, as shown in FIG. 1C, EB cured silver paste (3)
The semiconductor element (4) is die-bonded thereon. The semiconductor element (4) has a chip shape, and an aluminum electrode (5) is formed on the upper surface thereof.
更に第１図Ｄに示す如く、電子線（６）を照射する導
電路（２）のある絶縁フィルム（１）の裏側にアルミニ
ウム等の金属板（７）を当接させ、EBキュア銀ペースト
（３）に半導体素子（４）側から電子線（６）を１〜数
秒間照射してEBキュア銀ペースト（３）の硬化を行う。
照射条件は不活性雰囲気中で加速電圧150KeV以上、照射
線量３〜20Mradに設定している。電子線が照射される
と、EBキュア銀ペースト（３）の硬化が始まるが、この
とき電子線は金属弁（７）にも相当のエネルギー（加速
電圧×ビーム電流×照射時間）を与え、これがジュール
熱となり金属板（７）を瞬時に加熱する。この熱が絶縁
フィルム（１）側からEBキュア銀ペースト（３）にも加
えられ、電子線によりEBキュア銀ペースト（３）が急速
に硬化する際に発生するその中心方向に縮む応力歪をア
ニーリングして緩和している。Further, as shown in FIG. 1D, a metal plate (7) made of aluminum or the like is brought into contact with the back side of the insulating film (1) having the conductive path (2) for irradiating the electron beam (6), and the EB cured silver paste ( The EB-cured silver paste (3) is cured by irradiating 3) with an electron beam (6) from the semiconductor element (4) side for one to several seconds.
The irradiation conditions are set to an acceleration voltage of 150 KeV or more and an irradiation dose of 3 to 20 Mrad in an inert atmosphere. When the electron beam is irradiated, the curing of the EB-cured silver paste (3) starts. At this time, the electron beam also applies considerable energy (acceleration voltage × beam current × irradiation time) to the metal valve (7), which The metal plate (7) is instantaneously heated by Joule heat. This heat is also applied to the EB-cured silver paste (3) from the side of the insulating film (1) to anneal the stress strain that shrinks in the direction of its center, which is generated when the EB-cured silver paste (3) is rapidly cured by an electron beam. And relaxed.
また本発明では第１図Ａ乃至第１図Ｄの右側に右方向
の矢印を表示しているが、これば絶縁フィルム（１）を
ロール状に長くすれば、フィルムキャリア方式の製造方
法を適用できる。そしてEBキュア銀ペースト（３）の採
用により硬化を短時間で実現できるので、この硬化工程
をもフィルムキャリア方式に組み入れることが可能とな
った。In the present invention, a rightward arrow is displayed on the right side of FIGS. 1A to 1D. In this case, if the insulating film (1) is elongated in a roll shape, a film carrier type manufacturing method is applied. it can. Since the curing can be realized in a short time by employing the EB cured silver paste (3), it has become possible to incorporate this curing step into the film carrier method.
（ト）発明の効果 本発明に依れば、EBキュア銀ペースト（３）の採用に
より硬化をUVキュアペーストより短時間で確実に行な
え、工程の合理化を行なえる。(G) Advantages of the Invention According to the present invention, the use of the EB-cured silver paste (3) allows the curing to be performed more reliably and in a shorter time than the UV-cured paste, and the process can be rationalized.
また本発明に依れば、電子線照射時に金属板（７）も
加熱してEBキュア銀ペースト（３）の硬化時の応力歪を
除去でき、導電路（２）と半導体素子（４）との良好な
固着を行なえる。Further, according to the present invention, the metal plate (7) is also heated at the time of electron beam irradiation, so that the stress strain at the time of curing the EB-cured silver paste (3) can be removed, and the conductive path (2) and the semiconductor element (4) can be removed. Good fixation.
第１図Ａ乃至第１図Ｄは本発明による混成集積回路の製
造方法を説明するための断面図、第２図Ａ乃至第２図Ｄ
は従来の混成集積回路の製造方法を説明するための断面
図である。 （１）は絶縁フィルム、（２）は導電路、（３）はEBキ
ュア銀ペースト、（４）は半導体素子、（５）はアルミ
ニウム電極、（６）は電子線、（７）は金属板である。1A to 1D are cross-sectional views for explaining a method of manufacturing a hybrid integrated circuit according to the present invention, and FIGS. 2A to 2D.
FIG. 3 is a cross-sectional view for explaining a conventional method for manufacturing a hybrid integrated circuit. (1) is an insulating film, (2) is a conductive path, (3) is EB-cured silver paste, (4) is a semiconductor element, (5) is an aluminum electrode, (6) is an electron beam, and (7) is a metal plate. It is.
───────────────────────────────────────────────────── フロントページの続き (72)発明者 小林 義幸 大阪府守口市京阪本通２丁目18番地 三 洋電機株式会社内 (72)発明者 石原 純夫 群馬県山田郡大間々町大間々414―１ 東京アイシー株式会社内 (72)発明者 高橋 清 群馬県山田郡大間々町大間々414―１ 東京アイシー株式会社内 (56)参考文献 特開 平２−298041（ＪＰ，Ａ) 特開 昭54−51779（ＪＰ，Ａ) 特開 昭58−3238（ＪＰ，Ａ) 特開 平３−276650（ＪＰ，Ａ) (58)調査した分野(Int.Cl.6，ＤＢ名) H01L 21/52 C──────────────────────────────────────────────────続 き Continued on the front page (72) Inventor Yoshiyuki Kobayashi 2-18-18 Keihanhondori, Moriguchi-shi, Osaka Sanyo Electric Co., Ltd. (72) Inventor Sumio Ishihara 414-1 Oma, Omamachi, Yamada-gun, Gunma Prefecture (72) Inventor Kiyoshi Takahashi 414-1 Oma Omachi, Yamada-gun, Gunma Prefecture Tokyo Icy Co., Ltd. (56) References JP-A-2-298041 (JP, A) JP-A-54-51779 (JP, A) JP-A-58-3238 (JP, A) JP-A-3-276650 (JP, A) (58) Fields investigated (Int. Cl. 6 , DB name) H01L 21/52 C
Claims (2)
属箔の導電路を形成する工程と、 前記導電路上に電子線硬化型の導電ペーストを付着する
工程と、 前記導電ペースト上に半導体素子をダイボンドする工程
と、 前記絶縁フィルム基板の裏面に金属板を当接させ、前記
半導体素子側から電子線を照射して前記導電ペーストを
前記金属板を発熱させながら硬化させる工程とを具備す
ることを特徴とする混成集積回路の製造方法。A step of forming a conductive path of a metal foil having a desired pattern on an insulating film substrate; a step of attaching an electron beam-curable conductive paste on the conductive path; and a step of mounting a semiconductor element on the conductive paste. Die bonding, and a step of bringing a metal plate into contact with the back surface of the insulating film substrate, irradiating an electron beam from the semiconductor element side, and curing the conductive paste while heating the metal plate. A method for manufacturing a hybrid integrated circuit.
電路を形成し、前記基板を移動させて所定の前記導電ペ
ーストの硬化を行うことを特徴とする請求項１記載の混
成集積回路の製造方法。2. The hybrid integrated circuit according to claim 1, wherein said conductive path is continuously formed on said insulating film substrate, and said predetermined conductive paste is cured by moving said substrate. Production method.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2196576A JP2834866B2 (en) | 1990-07-24 | 1990-07-24 | Manufacturing method of hybrid integrated circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2196576A JP2834866B2 (en) | 1990-07-24 | 1990-07-24 | Manufacturing method of hybrid integrated circuit |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH0482232A JPH0482232A (en) | 1992-03-16 |
| JP2834866B2 true JP2834866B2 (en) | 1998-12-14 |
Family
ID=16360042
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2196576A Expired - Fee Related JP2834866B2 (en) | 1990-07-24 | 1990-07-24 | Manufacturing method of hybrid integrated circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2834866B2 (en) |
-
1990
- 1990-07-24 JP JP2196576A patent/JP2834866B2/en not_active Expired - Fee Related
Also Published As
| Publication number | Publication date |
|---|---|
| JPH0482232A (en) | 1992-03-16 |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| LAPS | Cancellation because of no payment of annual fees |