JP2836145B2 - Field effect transistor and method of manufacturing the same - Google Patents

Description

The present invention relates to a structure of a field effect transistor and a method for manufacturing the same.

[Conventional technology]

A two-dimensional electron gas field-effect transistor (hereinafter, referred to as 2DEGFET) utilizing the excellent transport properties of two-dimensional electron gas generated at the interface of a selectively doped heterojunction will be used for low-noise, high-power, and ultra-high-speed digital integration in ultra-high frequency bands. It is expected as a basic element of a circuit. In recent years, Okada et al. Proposed a prototype of a quasi-one-dimensional electron gas FET in a 2DEGFET in which the direction of movement of the two-dimensional electron gas was restricted to only one direction from the source to the drain to achieve higher performance. Extended Adstracts of the 20th International Consortium
50 on ference on Solid State Devices and Materials)
Reported on page 3.

FIGS. 3 (a) and 3 (b) are schematic views of the planar and cross-sectional structures of this FET. The cross section of FIG. 3B shows a cross section taken along line CC of FIG. 3A.

This FET includes a channel layer composed of an undoped GaAs layer 6 formed on a semi-insulating GaAs substrate 8, an electron supply layer composed of an n-type AlGaAs layer 5 formed on the channel layer, It is composed of a high-concentration n-type GaAs stripe layer 4 divided into a plurality of stripes on the layer, and a source electrode 1, a drain electrode 2, and a gate electrode 3.

This FET is composed of a semi-insulating GaAs substrate 8 and an undoped GaAs
The s layer 6, the n-type AlGaAs layer 5, and the high-concentration n-type GaAs layer are sequentially epitaxially grown, and a plurality of high-concentration n-type GaAs stripe layers 4 are formed by selective dry etching. 2. The required FET structure is obtained by forming the gate electrode 3.

In this conventional quasi-one-dimensional electron gas FET, when a negative voltage is applied to the gate electrode 3, the two-dimensional electron gas is depleted in a region where the high-concentration n-type GaAs stripe layer 4 does not exist. A quasi-one-dimensional electron gas 7 is formed below the region where the type GaAs stripe layer 4 exists.

[Problems to be solved by the invention]

As described above, in the conventional quasi-one-dimensional electron gas FET using the high-concentration n-type GaAs stripe layer, the quasi-one-dimensional electron gas FET is literally in an operating range where the gate length is relatively long and the electric field strength applied to the channel region is sufficiently small. FET operation that reflects gas transport characteristics can be expected. However, in this FET, if an attempt is made to achieve excellent characteristics even in a high-frequency region by shortening the gate length, electrons traveling in the channel region are accelerated by a high electric field, and the energy of the electrons increases. Direction is 1
It spreads two-dimensionally, two-dimensionally, and even three-dimensionally, and the mobility of conduction electrons decreases.

Therefore, in the conventional quasi-one-dimensional electron gas FET structure, excellent high-frequency operation in a high electric field region cannot be expected. This is a conventional pseudo one-dimensional electron gas FET
In, the quasi-one-dimensional electron gas induced under the high-concentration n-type GaAs stripe layer does not have a steep potential barrier in any of the direction parallel to the growth layer and the direction of the substrate. This is because under a high electric field operation, it spreads easily two-dimensionally and further three-dimensionally.

An object of the present invention is to solve the above-described problems and to provide a field-effect transistor that can expect one-dimensional electron conduction even under a high electric field region, and a method for manufacturing the same.

[Means for solving the problem]

A field effect transistor according to the present invention includes: a first electron supply layer made of an n-type first semiconductor formed by dividing a semiconductor device into a plurality of stripes on a semi-insulating substrate; A channel layer made of a second semiconductor having a narrower forbidden band width than the impurity-free first semiconductor formed thereon; and a n-type first semiconductor formed on the channel layer. An electron supply layer, an insulating layer made of an impurity-free first semiconductor formed on the second electron supply layer, an upper surface of the semi-insulating substrate, and side surfaces of the first electron supply layer And a gate electrode formed in contact with a side surface of the channel layer, a side surface of the second electron supply layer, and a side surface and an upper surface of the insulating layer.

A method for manufacturing a field-effect transistor according to the present invention includes the steps of: forming a first electron supply layer made of an n-type first semiconductor on a semi-insulating substrate; and adding no impurity to the first electron supply layer. Forming a channel layer made of a second semiconductor having a narrower forbidden band width than the first semiconductor; and forming a second layer made of an n-type first semiconductor on the channel layer.
Forming an electron supply layer, forming an insulating layer made of an impurity-free first semiconductor on the second electron supply layer, forming the first electron supply layer, the channel layer, and the Selectively etching the stacked structure including the second electron supply layer and the insulating layer into a plurality of stripe structures; and contacting the surface of the semi-insulating substrate exposed by the selective etching and the upper and side surfaces of the stripe structure. Forming a gate electrode.

[Action]

According to the present invention, a quasi-one-dimensional electron gas FET in which a quasi-one-dimensional electron gas generated at a stripe-shaped selectively doped heterojunction interface can be effectively controlled by gate electrodes provided on both side surfaces is obtained. Therefore, even when the acceleration electric field in the stripe direction increases, these quasi-one-dimensional electron gases do not spread in the lateral direction. Also in the direction perpendicular to the substrate surface, the potential barrier layers having a larger forbidden band width than the channel layer are provided on both the upper and lower surfaces of the channel layer in contact with the channel layer. Spreading in the vertical direction can be minimized. Therefore, even when the energy of electrons increases under a high electric field, one-dimensional electron conduction can be maintained.

Further, in the quasi-one-dimensional electron gas FET of the present invention, since electrons are supplied to the channel layer from the upper and lower two electron supply layers with the channel layer interposed therebetween, a large current operation is possible.

Furthermore, regarding the expansion of the depletion layer due to the application of the gate voltage, the device structure is designed so that the component spreading laterally between both sides of the stripe structure is more dominant than the component expanding toward the substrate from the upper surface. Since it can be designed easily, quasi-one-dimensional electron conduction is guaranteed even at a gate voltage near the threshold voltage.

At this time, it is possible to use a selective etching technique to form a plurality of stripe-shaped selective doping structures. After forming the stripe structure, a quasi-one-dimensional electron gas FET is manufactured by depositing a gate electrode metal. Can be.

〔Example〕

Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.

1 (a), 1 (b) and 1 (c) are views showing the structure of an embodiment of the field effect transistor of the present invention, wherein FIG. 1 (a) is a schematic plan view and FIG. FIG. 1B is a schematic cross-sectional structure along the line AA along the channel region, and FIG. 1C is a schematic cross-sectional structure along the line BB.

This embodiment is a field-effect transistor using a heterojunction of GaAs and AlGaAs, and includes a semi-insulating GaAs substrate 8,
An n-type AlGaAs layer (lower layer) 9 formed on the semi-insulating GaAs substrate 8 and divided into a plurality of stripes;
Impurity-free GaAs layer 6 formed on type AlGaAs layer 9
And n-type Al formed on the impurity-free GaAs layer 6.
GaAs layer (upper layer) 10, undoped AlGaAs layer 11 formed on n-type AlGaAs layer 10, and undoped AlGaAs layer 11.
Top and side surfaces of As layer 11, side surfaces of n-type AlGaAs layer 10, side surfaces of undoped GaAs layer 6, and n-type AlGaAs layer 9.
And a source electrode 1 and a drain electrode 2 formed apart from each other with the gate electrode 3 interposed therebetween. I have.

That is, this field-effect transistor has a semi-insulating Ga
A first electron supply layer 9 made of n-type AlGaAs formed on an As substrate 8 by dividing it into stripes;
Channel layer 6 made of GaAs having a narrower band gap than AlGaAs without impurities formed on the electron supply layer 9 of FIG.
A second electron supply layer 10 of n-type AlGaAs formed on the channel layer 6, an insulating layer 11 of undoped AlGaAs formed on the second electron supply layer 10,
Upper surface of semi-insulating GaAs substrate 8, side surface of first electron supply layer 9, side surface of channel layer 6, and second electron supply layer
A gate electrode 3 formed in contact with each of the side surface 10 and the side surface and the upper surface of the insulating layer 11; and a source electrode 1 and a drain electrode 2 formed separately from each other with the gate electrode 3 interposed therebetween. ing.

Next, a method for manufacturing the field-effect transistor of this embodiment will be described with reference to FIG. FIG. 2 is a schematic cross-sectional structure diagram in each manufacturing process, and FIG.
(D) shows a cross section corresponding to the cross section taken along the line BB of FIG. 1 (a), and FIG. 2 (e) shows a cross section corresponding to the cross section taken along the line AA of FIG.

First, as shown in FIG. 2A, a semi-insulating GaAs substrate 8 is formed.
An n-type AlGaAs layer (lower layer) 9 in which silicon (Si) is added at a concentration of 2.5 × 10 ¹⁸ cm ⁻³ , for example, having a thickness of about 100 nm
Further, the undoped GaAs layer 6 has a thickness of about 60 nm, followed by, for example, an n-type AlGaAs layer (upper layer) 10 in which Si is added to a concentration of 2.5 × 10 ¹⁸ cm ^-3 , and AlGa
The As layer 11 is sequentially grown over the entire surface with a thickness of about 50 nm. Here, the Al composition of each AlGaAs layer is 0.3, but is not necessarily limited to this composition. The above crystal structure can be formed by using, for example, a molecular beam epitaxial growth method or a metal organic chemical vapor deposition method.

Next, as shown in FIG. 2 (b), for example, using an electron beam exposure technique, the thin line width is 0.1 to 0.3 μm and the ratio of the thin line to thin line distance (line and space) is about 1: 2. A plurality of stripe-shaped photoresist patterns 12 are formed, and using this photoresist pattern as a mask, a crystal part having no pattern is formed on a semi-insulating GaAs substrate 8 and an n-type AlGaAs as shown in FIG. The layer 9 is etched away to the vicinity of the interface. Selective etching for forming the plurality of stripe structures includes solution etching using a phosphoric acid (H ₃ PO ₄ ) -based etchant or dry etching using a chlorine (Cl ₂ ) -based gas. A method can be used.

Next, as shown in FIG. 2 (d), a Ti line with a line width of about 0.25 μm
Forming a gate electrode 3 made of Al (titanium-aluminum);

Finally, as shown in FIG.
AuGe-Ni (gold germanium-nickel) on both sides
Source and drain electrodes 1 and 2 consisting of
By performing the heat treatment to the extent, the field-effect transistor of this embodiment is completed.

The field-effect transistor of this embodiment having a gate length of 0.25 μm and a stripe width of 0.2 μm, and a high-concentration n-type GaAs stripe layer 4 formed with the same gate size and the same size
As a result of comparing the current gain cutoff frequency when a voltage of 2 V is applied between the source and the drain with the field effect transistor having the conventional structure of FIG.
From about 60 GHz to about 60 GHz, and the effect of the present invention was demonstrated.

In the above embodiment, the gate, source and drain electrodes 1, 2, and 3 are formed directly on the undoped AlGaAs layer 11. After growing an n-type GaAs layer doped with about × 10 ¹⁸ cm ^-3 , the gate, source and drain electrodes 1, 2, and 3 can be formed on the n-type GaAs layer by performing stripe processing. In addition, it is possible to further reduce the contact resistance and the parasitic resistance of the source and drain electrodes.

In the above embodiments, the field effect transistor using the GaAs and AlGaAs heterojunction has been described as an example. However, other heterojunction materials, such as InP / InGaAs and AlInAs / I
Needless to say, the same principle can be applied to nGaAs.

〔The invention's effect〕

As described above, according to the present invention, the quasi-one-dimensional electron gas generated at the stripe-shaped selectively-doped heterojunction interface can be effectively controlled by the gate electric field extending laterally from both sides of the stripe structure. FET is obtained. Therefore, one-dimensional electron conduction is possible even in a high electric field operation, and has a large transconductance and a high current gain cut-off frequency under a wide bias condition, reflecting the excellent electron transport characteristic which is a characteristic of one-dimensional electron conduction. FET is obtained.

Further, the FET of the present invention can be manufactured by a relatively easy process, and can be applied to a wide range of fields from a low-noise element in an ultra-high frequency band to a basic element of an ultra-high-speed digital integrated circuit.

[Brief description of the drawings]

FIG. 1 is a schematic view showing a plane and a cross section of an embodiment of the field effect transistor of the present invention. FIG. 2 is a schematic cross sectional view showing each step of the method for manufacturing the field effect transistor shown in FIG. FIG. 3 is a schematic view showing a plane and a cross section of a conventional field effect transistor. DESCRIPTION OF SYMBOLS 1 ... Source electrode 2 ... Drain electrode 3 ... Gate electrode 4 ... High concentration n-type GaAs stripe layer 5 ... n-type AlGaAs layer 6 ... Impurity-free GaAs layer 7 ... Quasi-one-dimensional electron gas 8 ... ... Semi-insulating GaAs substrate 9 ... n-type AlGaAs layer (lower layer) 10 ... n-type AlGaAs layer (upper layer) 11 ... AlGaAs layer without impurity 12 ... photoresist pattern

Claims (2)

(57) [Claims] 1. A first electron supply layer made of an n-type first semiconductor formed by being divided into a plurality of stripes on a semi-insulating substrate, and formed on the first electron supply layer. A channel layer made of a second semiconductor having a narrower bandgap than the doped first semiconductor, and a second electron made of an n-type first semiconductor formed on the channel layer A supply layer, an insulating layer formed on the second electron supply layer and made of an impurity-free first semiconductor, an upper surface of the semi-insulating substrate, a side surface of the first electron supply layer, and the channel A field effect transistor comprising: a gate electrode formed in contact with a side surface of the layer, a side surface of the second electron supply layer, and a side surface and an upper surface of the insulating layer. 2. A step of forming a first electron supply layer made of an n-type first semiconductor on a semi-insulating substrate, and a step of forming an impurity-free first semiconductor on the first electron supply layer. Forming a channel layer made of a second semiconductor having a narrow forbidden band width; forming a second electron supply layer made of an n-type first semiconductor on the channel layer; Forming an insulating layer made of an impurity-free first semiconductor on the second electron supply layer; comprising the first electron supply layer, the channel layer, the second electron supply layer, and the insulation layer Selectively etching the stacked structure into a plurality of stripe structures, and forming a gate electrode in contact with the surface of the semi-insulating substrate exposed by the selective etching and the top and side surfaces of the stripe structure. Method of manufacturing a field effect transistor to.