JP2836235B2 - Clock generation control circuit - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a clock generation control circuit that supplies a clock signal to a dynamic circuit that operates at high speed, and particularly relates to a CMOS.
The present invention relates to a clock generation control circuit that generates or controls a clock signal supplied to a dynamic circuit having a configuration.

FIG. 7 shows an example of a high-speed dynamic circuit which operates in response to an external clock signal. In this conventional example, an input terminal group 1, an output terminal group 2, an internal circuit 3, and an external clock input terminal 4 are shown. And a two-phase clock driver 5. The external clock input terminal 4 is connected to the input of a two-phase clock driver 5. The two-phase clock driver 5 receives an external clock as shown in the time chart of FIG. And the high-speed dynamic circuit 6 operates under the control of the two-phase clocks C1 and C2.

FIG. 7 shows a dynamic shift register circuit 3 as an example of an internal circuit of the high-speed dynamic circuit.
The source electrode of the N-channel MOS transistor 7 is used as an input (node a), the gate electrode is connected to the clock C1, the drain electrode is connected to the input of the first inverter 8 (node b), and the second N-channel MOS The source electrode of the transistor 9 is connected to the output of the first inverter 8 (node c), the gate electrode is connected to the clock C2,
The drain electrode is connected to the input of the second inverter 10 (d node), and the output of the second inverter 10 is the output (e node).

The operation of the dynamic shift register circuit 3 is referred to as a tenth
This will be described with reference to the time chart in FIG. A, B, C, D,
Z is data of logical value “1” or logical and “0”.

When the external clock signal is at low level (section t0), the output C1 becomes high level by the two-phase clock driver,
Since the output C2 goes low, the first N-channel MOS
The transistor 7 is turned on, the input (node b) of the first inverter 8 is at the same level (A) as the input (node a), and the output (node c) of the first inverter 8 is the inverted value () of the input. Is output. Also, the second N channel
The MOS transistor 9 is turned off, the input (d node) of the second inverter 10 holds the level () immediately before the second N-channel MOS transistor 9 is turned off, and the output (e node) is the inverted level (Z node). ) Is output.

Next, when the external clock signal changes from the low level to the high level (point T1), C1 changes to the low level and C2 changes to the high level, so that the first N-channel MOS transistor 7 is turned off, and the first inverter is turned off. The input 8 (node b) holds the level (A) immediately before the first N-channel MOS transistor 7 turns off, and the output (node c) of the first inverter 8 outputs the inverted value (A) of the input. Output. Also,
The second N-channel MOS transistor 9 turns on, and the second
The input (d node) of the inverter 10 becomes the same level () as the output (c node) of the first inverter 8,
The output (e node) of the inverter 10 is the inverted value (A)
Is output.

Next, when the external clock signal changes from low level to high level again (point T2), C1 changes to high level and C2 changes to low level.
Turns on, the input (node b) of the first inverter 8 is at the same level (B) as the input (node a), and the output (node c) of the first inverter 8 is the inverted value () of the input.
Is output. Further, the second N-channel MOS transistor 9 is turned off, and the input of the second inverter 10 (node a)
Holds the level () before the second N-channel MOS transistor 9 is turned off, and the output (e node) outputs the inverted level (A).

As described above, the dynamic shift register circuit 3 sequentially shifts input data by an external clock signal.

[Problems to be Solved by the Invention] In this type of dynamic circuit, since the storage unit does not have a feedback loop, when the clock frequency decreases, the retained charge escapes due to leakage between the source electrode and the drain electrode of the MOS transistor, The input of the inverter becomes the intermediate potential.
When the inverter is constituted by a CMOS circuit composed of a P-channel transistor 14 and an N-channel transistor 15 connected in series between a power supply 13 and a ground 16, as shown in FIG.
The input voltage (VIN) of the CMOS inverter and the current I flowing from the power supply 13 to the ground 16 are, as shown in FIG.
However, almost no current flows near the power supply level or the ground level, but a large current flows near the intermediate potential of the input 17. Therefore, when the clock frequency becomes lower than the lower limit frequency (usually about 100 KHz to 1 MHz in CMOS) or when the clock stops, there is a problem that the retained charge is lost due to leakage and a large current flows through the dynamic circuit.

Means for Solving the Problems The gist of the present invention is to provide a clock generation control circuit that supplies an operation clock signal to a dynamic circuit that realizes a predetermined function in response to the operation clock signal, A clock detection circuit that detects whether or not the number is equal to or greater than a predetermined number and outputs a detection signal indicating a detection result; a clock generation circuit that generates the second clock signal having the predetermined number or more; A selection circuit that uses the first clock signal as the operation clock signal when the signal represents one clock signal, and uses the second clock signal as the operation clock signal when the detection signal represents less than a predetermined number of the first clock signals. That is.

[Operation of the Invention] If the first clock signal has a frequency equal to or higher than a predetermined number, the selection circuit supplies the first clock to the dynamic circuit as an operation clock.

If the first clock signal has a frequency less than a predetermined number, the selection circuit supplies the second clock signal output from the clock generation circuit to the dynamic circuit.

[Example] Next, an example of the present invention will be described with reference to the drawings.

FIG. 1 shows a clock generation control circuit according to the present invention. This clock generation control circuit includes an input terminal group 1, an output terminal group 2,
It is attached to a dynamic circuit 6 composed of an internal circuit 3, an external clock input terminal 4, and a two-phase clock driver 5. When the external clock terminal 4 has a high control input, the first input is at a low level. If there is, the first input (A) of the selector circuit 101 for selecting and outputting the second input, and the level of the frequency of the external clock signal is detected using a fixed frequency as a threshold value. The output (0) of the clock detection circuit 102 is connected to the input (CK1) of the clock detection circuit 102 that outputs the level.
01 is connected to the control input (G) of the clock generation circuit 103 for generating and outputting a clock if the control input is low and fixing the clock to a low level if the control input is high. The output (CK2) of the circuit 103 is connected to the second input (B) of the selector circuit 101. In this embodiment, the external clock signal functions as the first clock, and the output of the clock generation circuit 103 functions as the second clock.

The selector circuit 101 has the configuration shown in FIG.
If the control input 108 (G) is high, the first input 106
If (A input) is at a low level, the second input 107 (B input) is selected and output from the output terminal 109 (Y).

The clock generation circuit 103 has a ring oscillator configuration as shown in FIG. 3, and generates a clock when the control input 110 (F) is at a low level and outputs the clock from an output terminal 111. Fixed to.

The clock generation circuit 102 has the configuration shown in FIG.
A clock signal is input from the input terminal 113 (CK1), and the frequency of the clock signal is detected by using a fixed frequency as a threshold. The high level is output from the output terminal 119 (0) and the low level is output from the output terminal 119 (0). I do.

The operation of the clock generation circuit 102 will be described with reference to the circuit diagram of FIG. 4 and the time chart of FIG. Clock input terminal 11
The clock signal input from 3 is the rising differentiation circuit 112
, And is differentiated into a low level width TL which is a fixed value, and output to the h node. The high level width TH of the node h depends on the clock input frequency, and becomes longer as the frequency becomes lower. The P-channel MOS transistor 115 is turned on by receiving a low level pulse of the h node at the gate electrode, and the
And the potential of the node i rises. Node h
Is at a high level, the P-channel MOS transistor 115 is turned off and the N-channel MOS transistor 117 is turned on, so that the electric charge charged in the capacitor 116 is discharged to the ground and the potential of the node i falls. The input of the gate 118 whose threshold value is VT is connected to the node i, and the output is taken out as the output of the clock detection circuit. P channel
Assuming that the ON resistance of the MOS transistor 115 is RP and the ON resistance of the N-channel MOS transistor is RN, TL / RP becomes T
When it is larger than H / RN, the potential of the node i rises, and when it is reversed, it falls and the output of the gate 118 changes at VT.

 Therefore, the threshold value TTH of the clock cycle to be detected is TTH = (1 + RN / RP) .TL.

Therefore, if the frequency of the external clock is higher than 1 / TTH, the output 119 of the clock detection circuit 102 goes high, the selector circuit 101 outputs an external clock signal, and the dynamic circuit 6 supplies the external clock. If the external clock frequency is lower than 1 / TTH due to an external clock abnormality or the like, the output of the clock detection circuit 102 goes low, the clock generation circuit 103 generates a clock signal, and the selector 101 generates the clock signal. The clock signal of the circuit 103 is selected, and a clock is supplied to the dynamic circuit 6.

 Next, a second embodiment of the present invention will be described.

FIG. 6 shows a second embodiment of the present invention. In addition to the configuration of the first embodiment, each output of the dynamic circuit is connected to an AN.
The clock generation circuit 102 is connected to a first input of the D circuit
Is connected to the second input of the AND circuit 120.

In the present embodiment, the output signal of the clock detection circuit 102 is used to cut off erroneous data output from the dynamic circuit 6 in an abnormal state where the frequency of the external clock signal decreases or stops, and To a fixed value,
It has a configuration that does not adversely affect the subsequent circuits, and provides information on abnormal conditions to the alarm output terminal 12 to the outside.
Output from 1.

[Effects of the Invention] As described above, according to the present invention, if the first clock is less than the predetermined frequency, the second clock signal is supplied to the dynamic circuit, so that a large current due to a low frequency can be prevented. can get.

[Brief description of the drawings]

1 is a circuit diagram of a first embodiment, FIG. 2 is a circuit diagram of a selector circuit, FIG. 3 is a circuit diagram of a clock generation circuit, FIG. 4 is a circuit diagram of a clock detection circuit, and FIG. 6 is a time chart for explaining the operation of the clock detection circuit in the embodiment, FIG. 6 is a circuit diagram showing a second embodiment of the present invention, FIG. 7 is a circuit diagram of a conventional example, and FIG. FIG. 9 is a graph showing the relationship between the input voltage of the CMOS inverter and the current flowing between the power supply ground, and FIG. 10 is a time chart for explaining the operation of the dynamic shift register. 1 ... input terminal group, 2 ... output terminal group, 3 ... dynamic shift register, 4 ... external clock terminal, 5 ... two-phase clock driver, 6 ... dynamic circuit, 7, 9, 15, 117 ... N-channel MOS transistor, 8,10,11,12,105 ... Inverter, 13 ... Power supply terminal, 14,115 ... P-channel transistor, 16 ... Ground, 17,106,107,108,110,113 ... Input terminal, 18,109,111,119 ... Output terminal, 101 ... Selector Circuit 102: Clock detection circuit 103: Clock generation circuit 104: NAND gate 112: Differentiation circuit 114: Power supply terminal 116: Capacitance 118: Gate circuit

Claims (1)

(57) [Claims] A clock generation control circuit for supplying an operation clock signal to a dynamic circuit for realizing a predetermined function in response to the operation clock signal, wherein the clock generation control circuit detects whether the frequency of the first clock signal is equal to or more than a predetermined number. A clock detection circuit that outputs a detection signal indicating a detection result; a clock generation circuit that generates the predetermined number or more of the second clock signals; and a clock generation circuit when the detection signal indicates the predetermined number or more of the first clock signals. A selection circuit that uses one clock signal as an operation clock signal and uses the second clock signal as the operation clock signal when the detection signal represents less than a predetermined number of first clock signals.