JP2836709B2 - Printer alarm detection device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an alarm detection device, and more particularly to an alarm detection device suitable for use in a printer in which power supply to an actuator is turned off when an abnormality occurs in drive operation.

[0002]

2. Description of the Related Art As is well known, a recent serial printer is provided with a central processing unit (hereinafter referred to as a CPU), and the CPU controls the operation of the entire printer. FIG. 6 is a block diagram showing an example of a conventional serial printer. In FIG. 6, 1 is CP
U and 2 are bus lines for transmitting and receiving data between the CPU 1 and peripheral elements, and 3 is a read only memory (hereinafter referred to as ROM).
A program and data for controlling the operation of U1 are stored.

[0005] Next, reference numeral 4 denotes a random access memory, which is used for storing received data provided from the interface driver 6 and for a work area of the CPU 1. Reference numeral 5 denotes a gate array for reducing the load on the CPU 1 and controlling the space motor 8, the paper feed motor 9, the print head 10, and the like. Reference numeral 7 denotes a drive circuit for driving the space motor 8, the paper feed motor 9, the print head 10, and the like. Also, 11
Is an alarm circuit that determines that an alarm has occurred when the drive time of actuators such as the space motor 8, the paper feed motor 9, and the print head 10 exceeds a certain period of time, and disconnects the fuse of the power supply unit 12.

[0004] The operation of the alarm detection device in the serial printer configured as described above will be described with reference to the circuit diagram of FIG. First, when the actuator drive signal DV is inverted to "H" level, the transistors Tr1 and Tr2 are turned on, and the actuators 8, 9,
10 is driven. When the transistor Tr2 is turned on, a current flows into the capacitor C1 through the diode D1 and the resistor R5.

On the other hand, when the actuator drive signal DV goes low, the transistors Tr1 and Tr
2 turns off, the electric charge stored in the capacitor C1 is discharged through the route of the diode D2 and the resistor R4.
Since the charging and discharging of the capacitor C1 are performed in this way, if the actuator drive signal DV repeats on / off at a predetermined cycle, the voltage across the capacitor C1 does not increase beyond a certain fixed voltage value.

However, the actuator drive signal DV
Continuously goes to "H" level, the capacitor C
1 will continue to rise. In this case, when the voltage across the capacitor C1 exceeds the reference voltage V _REF of the comparator CMP1, the comparator CMP1
Turns on. When the comparator CMP1 is turned on, the base current is drawn, so that the transistor Tr3
Is turned on, and an alarm signal ALM for notifying a drive abnormality is output from the collector of the transistor Tr3. Therefore, by blowing the fuse of the power supply unit 12 or operating the alarm buzzer by the alarm signal ALM, it is possible to prevent the printer from being damaged due to a drive failure.

[0007]

In the case of the conventional alarm detecting device, the alarm of drive failure of the actuator is detected by the constant of the time constant circuit of the comparator CMP1. There is a problem that it is troublesome to determine a constant to be performed, and it is difficult to set a constant accurately. Further, the configuration of the conventional alarm detection device is complicated, and therefore, there is a problem that providing the alarm detection device results in a significant increase in cost. SUMMARY OF THE INVENTION The present invention has been made in consideration of the above-described problems, and has as its object to easily set a time until it is determined that an alarm state has occurred and to simplify a circuit configuration.

[0008]

According to the present invention, there is provided an alarm detecting apparatus for a printer, comprising: a pulse edge detecting circuit for detecting a rising edge and a falling edge of a drive pulse for driving an actuator of the printer; The counting operation is controlled by the pulse edge detection signal output from the circuit unit. If the pulse edge detection signal is an odd number, the time measurement operation is started, and if the pulse edge detection signal is an even number, measurement is in progress. Timer means for clearing the timer value of, a driving means for receiving a time-out signal derived from the timer means when the timer value reaches a set value, operating to activate an alarm signal generation circuit, and the driving means It operates based on the alarm signal given from the It has and a device operation stop means for so no.

[0009]

The edge of the drive pulse for driving the actuator of the printer is detected, the timer means is started with the odd-numbered detection output to start time measurement, and the timer during the measurement is started with the even-numbered detection output. By resetting the value, if the drive operation is normal, the drive pulse repeats on / off,
The timer value of the timer means is always smaller than a predetermined value.
However, when the drive pulse is continuously turned on, the count value of the timer means is not reset, and thus becomes larger than the set value. Therefore, when a time-out signal is output from the timer means, it is determined that an alarm state has occurred, and an alarm signal is output to turn off the output of the power supply circuit.

[0010]

FIG. 1 is a block diagram of an alarm detecting device according to an embodiment of the present invention. In FIG. 1, 1 is a CPU, 2
Is a bus line for transmitting and receiving data between the CPU 1 and peripheral elements, and 3 is a ROM. The ROM 3 stores programs and data for controlling the operation of the CPU 1.

Reference numeral 4 denotes a RAM for storing data received from the interface driver 6 and for controlling the CPU 1
Used for the work area. Reference numeral 5 denotes a gate array for reducing the load on the CPU 1 and controlling the space motor 8, the paper feed motor 9, the print head 10, and the like. Reference numeral 7 denotes a drive circuit for driving the space motor 8, the paper feed motor 9, the print head 10, and the like. Reference numeral 16 denotes a circuit that cuts a fuse 17a provided in the power supply unit 12 as a device operation stop unit 17 and generates an alarm signal for cutting off an output voltage in response to a command from the CPU 1. Next, reference numeral 13 denotes a pulse edge detection circuit for detecting an edge of the actuator drive signal DV.

Next, a description will be given of an alarm detecting device in the serial printer of the present embodiment configured as described above.
FIG. 2 is a circuit diagram illustrating an example of a specific configuration of the alarm detection device according to the present embodiment. In FIG. 2, a portion shown by a broken line is a pulse edge detection circuit unit 13 for detecting an edge of the actuator drive signal DV.

Next, the operation of the pulse edge detection circuit section 13 of this embodiment will be described with reference to the time chart of FIG. FIG. 3A shows a system synchronization clock SYSC.
LK, which is supplied from the CPU 1. When the actuator drive signal DV is input to the pulse edge detection circuit section 13, it is applied to the data input terminal D of the first flip-flop FF1, and the clock input terminal CLK
Synchronization clock SYSCLK given to
Is latched in synchronization with. As a result, the latch signal SQ is output from the Q1 terminal and the Q1B terminal of the first flip-flop FF1 as shown in (c) and (d) of FIG.
1, SQ1B are output.

The latch signal SQ1 is supplied to the data input terminal D of the second flip-flop FF2 and latched in synchronization with the system synchronization clock SYSCLK also supplied to the clock input terminal CLK.
As shown in FIGS. 3E and 3F, the latch signal S
Q2 and SQ2B are obtained. Further, by supplying these latch signals SQ1 and SQ2B the first AND circuit AND1, the pulse rise detecting signal P _U is generated. On the other hand, by supplying a latch signal SQ1B and SQ2 to the second AND circuit AND2, the pulse falling edge detection signal P _D is generated.

The pulse rising detection signal P _U and the pulse falling detection signal P _D thus generated are supplied to an OR circuit OR1 to generate a pulse edge detection signal P _E. Then, the pulse edge detection signal P _{E is set} to CP
An input is made to the external interrupt terminal IPTO of U1 to cause the CPU 1 to perform an external interrupt operation.

FIG. 4 is a time chart showing the external interrupt processing performed inside the CPU 1. As apparent from FIG. 4, the pulse edge detection signal P _E is the external interrupt pin IPTO
, The process proceeds to an external interrupt process in step P1. In this external interrupt process, in order to count the number of times the interrupt process has been passed, the counter value of the interrupt process pass counter is incremented in step P2. Next, in step P3, it is checked whether the counter value of the interrupt processing passage number counter is "1" or "2". In this case, if "1", the edge detection is a rising edge detection.
Start.

If the result of the check in step P3 is that the counter value is "2", the edge detection has been detected as falling, so the process proceeds to step P5 to clear the timer value of the timer means 14. After the processing of Step P4 or the processing of Step P5, the process proceeds to Step P6, and it is determined whether or not the value of the interrupt processing passage number counter is “2”. If the count value is "2", the process proceeds to step P7, where the count value is cleared and the process returns. If the result of determination in step P6 is that the count value is not "2", the process directly returns from step P6.

The alarm detection device of this embodiment detects a drive abnormality in this manner. Therefore, if the drive pulse is normally turned on / off, the timer value is cleared before reaching a preset value. Timer means 1
4 never times out. However, if the drive time becomes abnormally long for some reason, the timer means 14 times out, and the processing shifts to timer interrupt processing.

As shown in the timer interrupt operation flowchart of FIG. 5, when the process proceeds to the timer interrupt process in step P1,
The time-out signal S is sent from the timer means 14 to the driving means 15.
_OUT is output. As a result, the driving unit 15 operates to invert the potential of the port A of the CPU 1 to the “L” level. As shown in FIG. 2, an alarm signal generation circuit 16 including resistors R4, R5, R6 and a PNP transistor Tr3 is connected to the port A of the CPU 1.
Is applied to the base of the transistor Tr3. Therefore, when the potential of the port A becomes "L" level, the base potential becomes "L", so that the PNP transistor Tr3 is turned on, and the alarm signal ALM is output from its collector.

When the alarm signal ALM is generated in this way, as shown in FIG. 1, the alarm signal ALM is led out to the device operation stopping means 17 to immediately stop the operation of the printer. The example of FIG. 1 shows an example in which a fuse 17a is provided in the power supply unit 12 to constitute the device operation stopping means 17, and the operation of the printer is immediately stopped by blowing the fuse 17a with an alarm signal ALM. The device is prevented from being destroyed due to a drive error. The structure of the device operation stopping means 17 is not limited to the above-described fuse 17a, but may be constituted by other means. For example, the power supply voltage may be cut off when the alarm signal ALM is provided by using a program of the CPU 1.

[0021]

As described above, the present invention detects the edge of the drive pulse, starts the timer means with the odd-numbered detection output, starts time measurement, and starts the time measurement with the even-numbered detection output. Since the timer value during the measurement is reset, when the drive pulse is continuously turned on, the time-out signal is output from the timer means because the count value of the timer means is not reset. You can make it. Therefore, when the time-out signal is output, it can be determined that an alarm state is present, and an alarm signal is generated to stop the operation of the apparatus. Thus, the time until the timeout signal is output can be freely set by changing the value set in the timer means, so that the time until the alarm state is determined can be easily set. And the time constant circuit by the comparator circuit can be eliminated. Further, the circuit configuration can be simplified by eliminating the need for the time constant circuit by the comparator circuit, and the cost can be reduced.

[Brief description of the drawings]

FIG. 1 is a block diagram showing an embodiment of an alarm detection circuit according to the present invention.

FIG. 2 is a circuit diagram illustrating a specific configuration example of a pulse edge detection circuit unit.

FIG. 3 is a time chart for explaining the operation of the pulse edge detection circuit unit.

FIG. 4 is a flowchart for explaining processing of a CPU;

FIG. 5 is a flowchart illustrating a timer interrupt operation.

FIG. 6 is a block diagram showing a conventional example of an alarm detection device.

FIG. 7 is a circuit diagram showing a conventional example of an alarm detection device.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 CPU 2 Bus line 3 ROM 4 RAM 5 Gate array 6 Interface driver 7 Drive circuit unit 11 Alarm signal generation circuit 12 Power supply unit 13 Pulse edge detection circuit unit 14 Timer means 15 Driving means 16 Alarm signal generation circuit 17 Device operation stop means S _OUT time-out signal P _E pulse edge detection signal ALM alarm signal

Claims (1)

(57) [Claims] 1. A pulse edge detection circuit for detecting a rising edge and a falling edge of a drive pulse for driving an actuator of a printer, and a counting operation based on a pulse edge detection signal output from the pulse edge detection circuit. A timer means for starting a time measurement operation if the pulse edge detection signal is an odd number, and a timer means for clearing a timer value being measured if the pulse edge detection signal is an even number; and A drive unit that operates upon receiving a timeout signal derived from the timer unit when the set value is reached, and starts an alarm signal generation circuit; and operates based on an alarm signal given from the drive unit, and operates from a power supply circuit. A device operation stopping means for preventing output of driving power. Alarm detection device.