JP2837670B2 - Semiconductor integrated circuit device - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit device, and is used, for example, in a semiconductor integrated circuit device having a plurality of output circuits (output buffers) which are simultaneously operated. And effective technology. 2. Description of the Related Art There is a semiconductor integrated circuit device such as a gate array integrated circuit having a plurality of output circuits that are simultaneously operated. There is also a push-pull type output circuit used for such an output circuit. For the above push-pull type output circuit, for example,
1979, Robert E. Krieger Publishing Company (ROBE)
RT E.KRIEGER PUBLISHING COMPANY), “MOS Integrated Circuits (MOS Integrated Circuits)”, pp. 246-249. [Problems to be Solved by the Invention] FIG. 4 shows an example of a circuit diagram of a standard tristate output circuit including the push-pull type output circuit described above. This output circuit has an output control signal φ
oe includes n + 1 data output buffers DOB0 to DOBn which are simultaneously activated. Each data output buffer includes N-channel type output MOSFETs Q8 and Q9 provided in series between the power supply voltage Vcc of the circuit and the ground potential of the circuit.
Respectively. The gates of output MOSFETs Q8 and Q9 are supplied with corresponding inverted output data signals {circle around (1)} to {circle over (1)} and an internal signal selectively formed in accordance with output control signal φoe. That is, the output MOSFET Q8 outputs the inverted control signal φoe to the high level and the corresponding inverted output data signal ▲ ▼ to ▲
When ▼ is set to the low level of logic “1”, it is selectively turned on, and a high level output signal is sent to the corresponding output terminal. At this time, the output MOSFET Q8 is
Construct a source follower circuit with ETQ9 as a load. On the other hand, when the output control signal φoe is at the high level and the corresponding inverted output data signals
When ▼ is set to the high level of logic “0”, it is selectively turned on, and sends a low-level output signal to the corresponding output terminal. At this time, the output MOSFET Q9 constitutes a source-grounded amplifier circuit with the output MOSFET Q8 as a load. Incidentally, the data output buffers DOB0 to DOBn are connected to resistive, inductive and capacitive loads which are coupled to output signal lines via the data output terminals D0 to Dn.
The data output buffers DOB0 to DOBn are connected to the ground potential line GN.
The ground potential of the circuit is supplied via D, and this ground potential line G
Similarly, ND has a resistive load Rs and an inductance load Ls
Are combined. Further, in the semiconductor integrated circuit device including the output circuit as described above, the operation speed is increased, and the output MOSF is increased.
ET tends to be formed by increasing the size and reducing its conductance, that is, the on-resistance. Therefore, when a plurality of data output buffers are simultaneously operated, a plurality of output MOSFETs are simultaneously turned on, and a rapid current change occurs in the power supply voltage line and the ground potential line GND. This change is remarkable especially on the ground potential line GND.
Noise due to Ls occurs. That is, when the output MOSFETs Q8 of the data output buffers DOB0 to DOBn are turned on at the same time, the load capacitances coupled to the respective output signal lines are discharged at the same time, and the discharge current is discharged to the ground potential line GND.
Flows to For this reason, when the parasitic inductance is Ls and the ground potential line current is Ig, noise of ΔV = Ls × Ig / Δt is generated in the ground potential line GND. The noise on the ground potential line GND causes a malfunction of other output circuits and input circuits arranged close to each other. In order to deal with this, the present inventors output
An attempt was made to suppress the change in the output signal by making the rising of the output data signal supplied to the gate of the MOSFET gentle. However, in the case of the output MOSFET Q8 forming the source follower circuit, the effect can be obtained because the amplification factor is substantially 1, but in the case of the output MOSFET Q9, the amplification factor is large, so that the output MOSFET Q8 after the threshold is exceeded. It has been found that the change in the output signal is still steep, and no effect can be obtained. Further, the present inventors have considered adding a mirror capacitance C as shown by a dotted line in FIG. 4, but the layout efficiency of the semiconductor integrated circuit device is reduced in order to realize a relatively large mirror capacitance. However, this resulted in inhibiting the high integration. SUMMARY OF THE INVENTION An object of the present invention is to provide a semiconductor integrated circuit device having an output circuit for reducing noise and preventing malfunction without lowering layout efficiency. The above and other objects and novel features of the present invention will become apparent from the description of this specification and the accompanying drawings. [Means for Solving the Problems] The outline of a typical invention among the inventions disclosed in the present application is briefly described as follows. That is, a feedback path selectively formed when the output MOSFET is turned on is provided between the gate of the output MOSFET provided between the output terminal of the output circuit and the ground potential of the circuit and the output terminal. Things. [Operation] According to the above means, the amplification factor of the output MOSFET provided between the output terminal and the ground potential of the circuit is reduced by the negative feedback effect via the feedback path, and the amplification factor is supplied to the gate of the output MOSFET. By making the output data signal a little gentler, the change of the output signal can be made gentler, the noise of the ground potential line can be reduced, and the malfunction of other circuits arranged close can be prevented. Embodiment 1 FIG. 1 is a circuit diagram showing an embodiment of a tri-state output circuit of a gate array integrated circuit to which the present invention is applied. Each circuit element in the figure is formed on a single semiconductor substrate such as single crystal silicon, though not particularly limited, by a known CMOS integrated circuit manufacturing technique. In the following figures, the MOSFETs described are all N-channel MO
SFET. The gate array integrated circuit of this embodiment includes n + 1 data output buffers DOB0 to DOBn. These data output buffers have corresponding inverted output data signals from other circuits (not shown) of the gate array integrated circuit.
▼ to ▲ ▼ are supplied. The data output buffers DOB0 to DOBn are simultaneously activated according to an output control signal φoe supplied from a timing control circuit (not shown), and output to corresponding inverted output data signals ▲ ▼ to ▲ ▼ via data output terminals D0 to Dn. The corresponding output signal is transmitted. In FIG. 1, an output control signal φoe is commonly supplied to one input terminal of a NAND gate circuit NAG1 of data output buffers DOB0 to DOBn. The output control signal φoe is
After being inverted by the inverter circuit N1, it is commonly supplied to one input terminal of the NOR gate circuit NOG1 of the data output buffers DOB0 to DOBn. NOR gate circuit NOG1 for data output buffers DOB0 to DOBn
And the other input terminal of the NAND gate circuit NAG1 are commonly connected, and the corresponding inverted output data signal
To ▲ ▼ are supplied. These inverted output data signals ▼ to ▼ are at a high level when the data to be output is logic “0”, and are at a low level when the data to be output is logic “1”. From the above, the output signal of the NOR gate NOG1 of the data output buffers DOB0 to DOBn is the inverted output data signal ▲ ▼ to ▲ ▼ corresponding to the output control signal φoe being high level, that is, the output signal of the inverter circuit N1 being low level.
Is at a low level, that is, when it is at logic "1", it is at a high level. The output signal of the NAND gate NAG1 of the data output buffers DOB0 to DOBn is at a low level when the output control signal φoe is at a high level and the corresponding inverted output data signal 信号 to ▲ is at a high level, that is, logic “0”. . Although there is no particular limitation between the power supply voltage Vcc of each data output buffer and the ground potential line GND of the circuit,
Channel type two output MOSFET Q1 (first output MOSFET
T) and Q2 (second output MOSFET) are provided in series. The commonly connected drains of the output MOSFETs Q1 and Q2 are
It is coupled to corresponding data output terminals D0 to D7, respectively.
Of these, the above-mentioned NOR gate is connected to the gate of output MOSFET Q1.
The output signal of NOG1 is supplied. Therefore, the output MOSFET
Q1 is turned on when the output signal of the NOR gate circuit NOG1 is at a high level, that is, when the output control signal φoe is at a high level and the corresponding inverted output data signals ▲ ▼ to ▲ ▼ are at logic “1”. Become. As a result, the corresponding output MOSFET is connected to the data output terminals D0 to D7.
A high-level output signal such as the power supply voltage Vcc is transmitted via Q1. On the other hand, the inverted signal of the output signal of the NAND gate NAG1 by the inverter circuit N2 is supplied to the gate of the output MOSFET Q2 of each data output buffer. These output MOSFETs
Between the gate of Q2 and the corresponding data output terminals D0-D7, although not particularly limited, an N-channel MOSFET
ETQ3 (third MOSFET) and Q4 (fourth MOSFET) are provided. The gate of the MOSFET Q3 is connected to the above-mentioned NAND gate circuit NA.
An inverted signal from the inverter circuit N3 of G1 is supplied. Further, a delay signal of the output signal of the NAND gate circuit NAG1 by the inverter circuits N4 and N5 is supplied to the gate of the MOSFET Q4. Here, the MOSFET constituting the inverter circuit N2
Is designed to have a conductance slightly smaller than that of the MOSFET forming the inverter circuit N3. Also,
The sizes of the MOSFETs constituting the inverter circuits N4 and N5 are designed such that their delay times are, for example, several nanoseconds (ns). FIG. 2 shows the data output buffers DOB0 to DOBn of FIG.
3 are signal waveform diagrams of respective parts of FIG. The operation of the data output buffers DOB0 to DOBn when logic "0" is output will be described with reference to this signal waveform diagram and FIG. In a non-selected state of the gate array integrated circuit, the output control signal φoe is at a low level, and the NAND gate circuit NAG1
Becomes high level. Thus, the output signals n2 and n3 of the inverter circuits N2 and N3 are both at the low level, and the MOSFET Q3 is turned off. On the other hand, when the output signal of the NAND gate circuit NAG1 is set to a high level,
The output signal n5 of the inverter circuit N5 becomes high level,
SFETQ4 is turned on. When the gate array integrated circuit is in the selected state and the output control signal φoe is at the high level, and the corresponding inverted output data signals ▲ ▼ to ▲ ▼ are at the logic “0” high level, the output signal n1 of the NAND gate circuit NAG1 becomes It becomes low level. As a result, first, a relatively large size MOSFET
The output signal n3 of the inverter circuit N3 becomes high level and the output signal of the inverter circuit N2 is slightly delayed.
n2 goes high. Further, with a slight delay, the output signal n5 of the inverter circuit N5 changes from the high level to the low level. When the output signal n3 of the inverter circuit N3 goes high, the MOSFET Q3 is turned on, and when the output signal n5 of the inverter circuit N5 goes low, the MOSFET Q4 is turned off. Therefore, after MOSFET Q3 is turned on,
Until the MOSFET Q4 is turned off, the data output terminals D0 to Dn corresponding to the output MOSFET Q2 are short-circuited via the MOSFETs Q3 and Q4. Therefore, the output signals of the corresponding data output terminals D0 to Dn are negatively fed back to the gate of the MOSFET Q2,
The amplification factor of SFETQ2 is temporarily reduced. For this reason, the output signals output to the data output terminals D0 to Dn are relatively slowly pulled down to the low level according to the characteristics of the inverter circuit N2 having a relatively small driving capability. Data output terminal corresponding to the gate of output MOSFET Q2
D0 to Dn are short-circuited after the output signal n3 of the inverter circuit N3 becomes high level after the inverter circuit N5
Is substantially the same as the time Tf until the output signal n5 of FIG. The short-circuit time Tf is determined by the conductance of the MOSFET constituting the inverter circuit N3 and the inverter circuits N4 and N5.
Is determined by the conductance of the MOSFET that constitutes. As described above, the short-circuit time Tf may be on the order of several nanoseconds. As described above, in the data output buffers DOB0 to DOB of the gate array integrated circuit of this embodiment, the output provided between the corresponding data output terminals D0 to Dn and the ground potential of the circuit is provided.
A series-type MO is connected between the gate of the MOSFET and the output terminal.
SFETs Q3 and Q4 are provided. These MOSFETs Q3 and Q4
Are simultaneously turned on for a predetermined time when the corresponding output MOSFET Q2 is turned on. This allows MO
The output signal of the data output terminal corresponding to the predetermined time is negatively fed back to the gate of the SFET Q2, and the amplification factor is kept low. For this reason, the output signal of the data output terminal is gently extracted, so that noise on the ground potential line GND is suppressed, and malfunction of other data output buffers and data input buffers disposed close to each other is prevented. Embodiment 2 FIG. 3 is a circuit diagram showing another embodiment of an output circuit of a gate array integrated circuit to which the present invention is applied. FIG. 3 exemplarily shows a data output buffer DOB0 among the above output circuits. Other data output buffers DOB1 to DOBn (not shown) have the same configuration as the data output buffer DOB0. In the following description, the description of the same parts as those in FIG. 1 will be omitted. In FIG. 3, the data output buffer DO of this embodiment is shown.
B0 includes output MOSFETs Q5 (first output MOSFET) and Q6 (second output MOSFET) corresponding to the output MOSFETs Q1 and Q2 of the embodiment of FIG. Also, these output MOSFETs Q5 and Q6
The output signals of the NOR gate circuit NOG2 and the inverter circuit N6 corresponding to the NOR gate circuit NOG1 and the inverter circuit N2 in FIG. The NAND gate circuit NAG2 corresponds to the NAND gate circuit NAG1 in FIG. Between the gate of output MOSFET Q6 and the corresponding data output terminal D0, the inverted output data signal
N-channel feedback MOSFET Q7 (fifth MOSF
ET) is provided. The feedback MOSFET Q7 is selectively turned on when the corresponding inverted output data signal Do0 is at a high level of logic "0", regardless of the output control signal φoe. As a result, the inverted output data signal ▲ ▼ becomes high level and the output MO
When SFET Q6 is turned on, the output signal of corresponding data output terminal D0 is negatively fed back to the gate of MOSFET Q6, and the amplification factor is reduced. Therefore, the data output terminal
The output signal of D0 is pulled out relatively slowly, and
GND noise is suppressed. In the case of this embodiment, when the MOSFET Q6 is turned on, the output signal of the inverter circuit N6 becomes high level.
High-level output MOSFET and output MOSFET of inverter circuit N6
A through current flows through Q6. Therefore, this embodiment is an effective method when the amount of negative feedback is small, that is, when the conductance of the feedback MOSFET Q7 is relatively small, since the circuit configuration is simple. As shown in the present embodiment, when the present invention is applied to an output circuit of a semiconductor integrated circuit device such as a gate array integrated circuit, the following effects can be obtained. That is, (1) between the output terminal and the gate of the output MOSFET provided between the output terminal of the output circuit and the ground potential of the circuit;
By providing a feedback MOSFET that is selectively turned on when the output MOSFET is turned on, the amplification factor of the output MOSFET provided between the output terminal and the ground potential of the circuit can be selectively reduced. Is obtained. (2) In the above item (1), two MOSFETs which are simultaneously turned on for a predetermined time when the output MOSFET is turned on are provided between the gate of the output MOSFET and the corresponding output terminal. By preventing through current,
The effect that the amplification factor of the output MOSFET can be reduced can be obtained. (3) According to the above items (1) and (2), the level change of the output signal at the output terminal can be made relatively gentle,
An effect is obtained that noise such as a ground potential line can be suppressed. (4) According to the above items (1) to (3), an effect is obtained that malfunction of another output circuit, input circuit, or the like arranged close to the output circuit can be prevented. (5) Since the feedback MOSFETs of the above items (1) and (2) can be formed within a relatively small area on the semiconductor substrate, there is an effect that they can be realized without sacrificing layout efficiency. Although the invention made by the inventor has been specifically described based on the embodiments, the invention is not limited to the above-described embodiments, and various changes can be made without departing from the gist of the invention. Nor. For example, the data output buffers of FIGS. 1 and 3 may use P-channel MOSFETs instead of MOSFETs Q1 and Q5. Further, in this embodiment, each data output buffer is a tri-state output buffer, but may be a CMOS buffer or the like in which two output MOSFETs are complementarily turned on. The feedback path provided between the gate of the output MOSFET Q1 or Q5 and the corresponding output terminal may be, for example, a resistor made of polysilicon or a P-channel MOSFET. In FIG. 1, the inverter circuit N4
And the delay circuit constituted by N5 and N5 is not limited to this. Further, the specific circuit configuration of the output circuit shown in FIGS. 1 and 3 can take various embodiments. In the above description, the case where the invention made by the present inventor is applied to the output circuit of the gate array integrated circuit, which is the application field in the background, has been mainly described. However, the present invention is not limited thereto. The present invention can be applied to a semiconductor memory device and various microcomputers. The present invention can be applied to a semiconductor integrated circuit device having a plurality of output circuits that are at least activated simultaneously. [Effects of the Invention] The effects obtained by typical ones of the inventions disclosed in the present application will be briefly described as follows. That is, a feedback path selectively formed when the output MOSFET is turned on is provided between the gate of the output MOSFET provided between the output terminal of the output circuit and the ground potential of the circuit and the output terminal. Thus, the amplification factor of the output MOSFET provided between the output terminal and the ground potential of the circuit can be selectively reduced, and noise such as a ground potential line can be suppressed without sacrificing layout efficiency. This can prevent malfunction of other output circuits and input circuits arranged close to the output circuit.

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a circuit diagram showing one embodiment of a tri-state output circuit to which the present invention is applied, and FIG. 2 is for explaining the operation of the tri-state output circuit of FIG. FIG. 3 is a circuit diagram showing another embodiment of a tri-state output circuit to which the present invention is applied, and FIG. 4 is a circuit diagram showing an example of a conventional tri-state output circuit. DOB0 to DOB7: Data output buffer, Q1 to Q9: N-channel MOSFET, NOG1 to NOG3: NOR gate circuit, NAG1 to
NAG3: NAND gate circuit, N1 to N8: Inverter circuit, C: Miller capacitance, Rs: Parasitic resistance, Ls: Parasitic inductance.

Claims (1)

(57) [Claims] Output MOSFET with drain electrode connected to output terminal
A control circuit disposed between the gate electrode of the output MOSFET and the drain electrode; and a drive circuit for providing a gate drive signal to the gate electrode of the output MOSFET. An input signal is supplied to a gate electrode of the output MOSFET from an output coupling point, and the control circuit has a control MOSFET, and a source / drain path of the control MOSFET is connected between a gate electrode and a drain electrode of the output MOSFET. Then, a control signal based on the signal of the drive circuit is input to the gate electrode of the control MOSFET, and in conjunction with the switching of the gate drive signal, the control circuit controls the gate electrode of the output MOSFET for a fixed time. A feedback circuit is formed between the output electrode and the drain electrode, and an output buffer circuit configured to control a gate drive signal applied to the gate electrode of the output MOSFET from the drive circuit. Ete becomes possible semiconductor integrated circuit device according to claim. 2. The control circuit includes first and second MOs arranged in series.
The first MOSFET is switch-controlled to operate at the same timing as the output MOSFET, and the second MOSFET inverts a control signal supplied to the gate electrode of the first MOSFET. 2. The semiconductor integrated circuit device according to claim 1, wherein the switch is controlled by a delayed control signal. 3. 2. The semiconductor integrated circuit according to claim 1, wherein said control circuit comprises a third MOSFET, and said third MOSFET is turned on in accordance with an on-state of said output MOSFET. apparatus.