JP2838599B2 - Test facilitation circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a circuit for facilitating the test of a digital logic circuit, and more particularly to a technique for extracting and testing a signal inside the digital logic circuit.

[0002]

2. Description of the Related Art As digital logic circuits have become larger and more complex, it has become more difficult to test the operation of the digital logic circuits. Therefore, the necessity of the test facilitation technology is increasing. FIG. 3 shows an example of a conventional test facilitation circuit. Conventionally, as shown in FIG. 3, together with the operation result output 8 of the functional circuit 9, a logic circuit which is difficult to verify only with the operation result output 8, that is, the AND circuit 1 and the operation circuit 8, as shown in FIG.
3. The outputs of the NOR circuits 2 and 4 were input via the signal line 7, respectively.

[0003]

In the above prior art, it is necessary to provide a large number of signal lines 7 for the operation verification circuit 5 for testing only, and furthermore, in proportion to the number of the signal lines 7, There is a problem that the scale of the operation verification circuit 5 becomes large.

An object of the present invention is to reduce the number of signal lines 7 connected to the operation verification circuit 5.

[0005]

To achieve the above object, the present invention provides an operation result of a logic circuit constituting a functional circuit.
Using the output as input, the operation of the functional circuit is checked by the operation verification circuit.
In a test facilitation circuit for testing, an OR circuit
Or a logic having an AND circuit and constituting the functional circuit
Of the circuits, the output terminal of the logic circuit used for testing is
Connect to the input of R circuit or AND circuit,
And the output of the AND circuit is connected to the input of the operation verification circuit .

According to another aspect of the present invention, an operation result output of a logic circuit constituting a functional circuit is input.
And the operation of the functional circuit is tested by an operation verification circuit.
In the case of test facilitation circuit, OR circuit
Of the logic circuits that make up the functional circuit, used for testing
The AND circuit output terminal and the NOR circuit output terminal are connected by the OR
Connection to the input of the
It is connected to the input of the circuit .

Further, in order to achieve the above object, the present invention provides an operation result output of a logic circuit constituting a functional circuit.
The operation of the functional circuit is tested by an operation verification circuit.
In the test facilitation circuit for
Of the logic circuits constituting the functional circuit,
The output terminal of the NAND circuit and the output terminal of the OR circuit
Connect to the input of the AND circuit and connect the output of this AND circuit to the
It is connected to the input of the operation verification circuit .

[0008]

DESCRIPTION OF THE PREFERRED EMBODIMENTS One embodiment of the present invention will be described with reference to FIG.

In FIG. 1, a functional circuit 9 corresponds to a package on which electronic components (IC, LSI, etc.) are mounted or a dedicated LSI, and an operation verification circuit 5 corresponds to a tester. The operation result of the functional circuit 9 is output to the operation result output 8 and the operation verification circuit 5 verifies whether the operation result is correct. AND which is a logic circuit
The circuits 1 and 3 and the NOR circuits 2 and 4 are circuits that cannot sufficiently verify whether or not the operation is correct only by verifying the operation result output 8, and these logic circuits have outputs whose logic is “1”. Frequency is low. For example, if the input value is random, the frequency of logic "1" is 1/2 to the fourth power, that is, 1/16, and two or more outputs of these four logic circuits simultaneously output "1". ] Is about 1/16 × 3/16 = 3 / 256.Therefore, the outputs of these four logic circuits are added to the input terminal of the OR circuit 6, and the signal which is the output terminal of the OR circuit 6 is output. Even if the logical sum is taken out from the line and verified by the operation verification circuit 5,
We can verify enough. (Two or more “1” s are input to the OR circuit 6
When it is above, its output is the same as when there is only one "1" input.
Since it is "1", it cannot be distinguished and sufficient verification
I can't. However, two or more "1" are input to the input of the OR circuit 6.
If the frequency is low, there is no problem in practice
Thus, sufficient verification can be performed by using the OR circuit 6 in this manner.
Can be In this case, which input of the OR circuit 6 is defective
Obviously, there is no need to have the resolution to determine the obstacle.
You. ) As a result, the number of signal lines connected to operation verification circuit 5, so that the decreased from four to one.

Next, a second embodiment of the present invention will be described with reference to FIG.

In FIG. 2, a functional circuit 9 corresponds to a package on which electronic components (IC, LSI, etc.) are mounted or a dedicated LSI, and an operation verification circuit 5 corresponds to a tester. The operation result of the functional circuit 9 is output to the operation result output 8, and the operation verification circuit 5 verifies whether the operation result is correct. NAND as a logic circuit
The circuits 11 and 13 and the OR circuits 12 and 14 are circuits that cannot sufficiently verify whether the operation is correct only by verifying the operation result output 8, and these logic circuits are:
The frequency at which the output becomes logic "0" is low. For example, assuming that the input value is random, it is the same as in the first embodiment of the present invention. The outputs of these four logic circuits are added to the input terminal of the AND circuit 16, and the signal output from the AND circuit 16 is output. The logical product is taken out from the line and the operation verification circuit 5
Even if it is verified by, it can be verified sufficiently. (Input of AND circuit 16
If there are two or more "0" in the force, the output is "0" input
Is "0" as in the case of one, and cannot be distinguished.
Cannot be verified enough. However, the AND circuit 16
If the frequency of two or more “0” in the input is low,
In practical terms, there is no problem.
It can be verified sufficiently by using. ) As a result, the number of signal lines connected to operation verification circuit 5, so that the decreased from four to one.

As described above, the first and second embodiments of the present invention have the effect of reducing the number of signal lines connected to the operation verification circuit 5 from four to one.

[0013]

According to the present invention, the theory for constructing a functional circuit
Of the logical circuits, the output terminal of the logical circuit used for the test is OR
Connected to the input of a circuit or AND circuit
Or connect the output of the AND circuit to the input of the operation verification circuit
Therefore, the effect is obtained that the number of signals connected to the input of the operation verification circuit can be reduced by adding only a very small number of circuits .

[Brief description of the drawings]

FIG. 1 is a circuit diagram showing a first embodiment of the present invention.

FIG. 2 is a circuit diagram showing a second embodiment of the present invention.

FIG. 3 is a diagram showing a conventional test facilitation circuit.

[Explanation of symbols]

 REFERENCE SIGNS LIST 1 AND circuit 2 NOR circuit 3 AND circuit 4 NOR circuit 5 Operation verification circuit 6 OR circuit 8 Operation result output 9 Function circuit 11 NAND circuit 12 OR circuit 13 NAND circuit 14 OR circuit 16 AND circuit

Claims (3)

(57) [Claims] 1. An operation result output of a logic circuit constituting a functional circuit.
The operation of the functional circuit is tested by an operation verification circuit.
A test facilitating circuit having an OR circuit or an AND circuit, wherein the functional circuit comprises
Logic circuit output terminal used for testing
Is connected to the input of the OR circuit or the AND circuit.
The output of the OR circuit or AND circuit is output to the operation verification circuit.
A test facilitation circuit characterized by being connected to an input of a road . 2. An operation result output of a logic circuit constituting a functional circuit.
The operation of the functional circuit is tested by an operation verification circuit.
In a test facilitation circuit for a test , a logic circuit comprising an OR circuit and constituting the functional circuit is provided.
The output terminal of the AND circuit and the output of the NOR circuit used for the test
And the other end to the input of the OR circuit.
A test facilitating circuit, wherein an output is connected to an input of the operation verification circuit. 3. An operation result output of a logic circuit constituting a functional circuit.
The operation of the functional circuit is tested by an operation verification circuit.
In the test facilitation circuit for the case where the logic circuit constituting the functional circuit has an AND circuit,
Of which, the NAND circuit output terminal and OR circuit output
Connected to the input of the AND circuit.
A test facilitating circuit, wherein an output of the circuit is connected to an input of the operation verification circuit.