JP2838834B2 - Pattern interval reduction method for automatic design system - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Table of Contents] Overview Industrial application field Conventional technology (FIG. 5) Problems to be solved by the invention Means for solving the problem (FIG. 1) Action Embodiment (i) Embodiment 1 (FIGS. 2 and 3) (ii) Embodiment 2 (FIG. 4) Effects of the Invention [Summary] Pattern spacing reduction method of LSI automatic design system, especially L
Regarding a method of moving and reducing the interval between a mask and a chip-level layout figure in automatic SI design, the method directly and indirectly applies the longest path method between a fixed pattern of the layout figure and a pattern to be moved. In the pattern interval reduction method of the LSI automatic design system that automatically creates the LSI pattern layout with the purpose of moving the pattern to be reduced to the reduction destination desired by the designer, in the direction orthogonal to the reduction movement direction. A dummy pattern having a variable size is provided at an arbitrary position between a plurality of movement target patterns arranged in the same row and one or a plurality of fixed patterns facing the movement target pattern in the reduction direction, A first interval reference is set between the movement target pattern and the dummy pattern, and the dummy pattern and the fixed pattern are set. A second interval reference is set between the turn and the turn, the position of the fixed pattern is fixed, the interval between the dummy pattern and each movement target pattern maintains the first interval reference, and the fixed pattern and the fixed pattern are fixed. The method includes moving the dummy pattern and each moving target pattern so as to maintain the distance between the dummy pattern and the second distance standard to reduce the distance between the fixed pattern and each moving target pattern.

[Industrial applications]

The present invention relates to a pattern reduction method of an LSI automatic design system, and more particularly, to a method of moving and reducing a mask and a chip-level layout figure in an LSI automatic design.

In recent years, with the demand for higher functionality and higher performance of semiconductor devices, in the field of LSI design, a pattern reduction technology for automatically reducing a layout figure (hereinafter referred to as compaction) based on design rules has been used.

According to this, there is a demand for a pattern reduction method capable of compacting a plurality of graphic elements arranged in the same column while holding the column.

[Conventional technology]

FIGS. 5A and 5B are explanatory diagrams relating to a pattern reduction method of a conventional LSI automatic design system.

FIG. 1A shows a layout diagram related to a chip level before compaction of an LSI automatic design system for automatically creating an LSI pattern layout.

In the figure, the function module patterns 31a and 31b automatically created based on the design data have pad pattern groups 32a.
When compacting ~ 32e, as a pattern reduction algorithm, a constraint graph is extended from the function module patterns 31a, 31b to the pad pattern groups 32a ~ 32e,
The longest path method that determines the position after compaction by analyzing the graph is used.

Here, the concept of “stretching a constraint graph” is based on the concept that an arbitrary point (x1, y1) on one side of the functional module patterns 31a and 31b facing the movement reduction direction A and the individual pad pattern groups 32
Any point on one side of (x2, y2), (x3, y3), (x4, y4)
.. Are specified, the two points are connected by an arbitrary line segment, and a reduction constraint rule is set between the two points.

For example, when a constraint graph of a 1 μm rule is set as a design rule from the functional module patterns 31a and 31b to the pad pattern group 32, and the pad pattern group 32 is moved to the position P of the reduction destination desired by the designer, FIG. As shown in the layout diagram relating to the chip level after compaction in (b), the pad pattern group 3 is located at a position close to the functional module pattern 31b from the position P of the reduction destination desired by the designer.
2d and 32e are moved.

This is because the pattern 31b is retracted from the functional module pattern 31a in the reduced movement direction A. That is, as a result of analyzing the constraint graph extending from the function module pattern 31b to the pad patterns 32d and 32e, the pad patterns 32d and 32e are moved to positions separated by 1 μm from the pattern 31b.

[Problems to be solved by the invention]

By the way, according to the conventional example, the longest path method is directly applied between the functional module patterns 31a and 31b which are fixed patterns and the pad pattern 32 which is a movement target pattern.

Therefore, as a result of analyzing the constraint graph between the functional module pattern 31b and the pad patterns 32d and 32e, as shown in FIG. 5B, the pad pattern 32 is located at the position P of the reduction destination desired by the designer. Not moved. As a result, there is a problem that the compaction cannot be performed while the pad patterns 32 in the same column in the initial arrangement intended by the designer are maintained.

The present invention has been made in view of the problems of the conventional example, and directly applies the longest path method between a fixed pattern of a layout figure and a movement target pattern without applying the longest path method. It is another object of the present invention to provide a pattern interval reducing method for an LSI automatic design system that enables a target pattern to be moved to a reduction destination desired by a designer.

[Means for solving the problem]

FIGS. 1 (a) and 1 (b) show a principle diagram relating to a pattern interval reducing method of the LSI automatic design system of the present invention.

The pattern reduction method includes a plurality of movement target patterns 2 arranged in the same row in a direction orthogonal to the reduction movement direction A in a pattern interval reduction method of an LSI automatic design system for automatically creating an LSI pattern layout. A dummy pattern 3 made of a line of a specific length or a pattern of a specific size is provided at an arbitrary position between the target pattern 2 and one or a plurality of fixed patterns 1 facing the reduction direction A, A first interval reference is set between the movement target pattern 2 and the dummy pattern 3, and the dummy pattern 3
A second interval reference is set between the fixed pattern 1 and the fixed pattern 1, the position of the fixed pattern 1 is fixed, and the interval between the dummy pattern 3 and each movement target pattern 2 maintains the first interval reference. Then, the dummy pattern 3 and each moving target pattern 2 are moved so that the distance between the fixed pattern 1 and the dummy pattern 3 maintains the second distance reference, and the fixed pattern 1 and each moving target pattern 2 are moved. The above-mentioned object is achieved by reducing the interval between.

[Action]

According to the present invention, the variable size dummy pattern 3 corresponding to the moving target pattern 2 is provided between the fixed pattern 1 and the moving target pattern 2.

Therefore, the longest path method is indirectly applied between the fixed pattern 1 and the movement target pattern 2 with the dummy pattern 3 interposed therebetween. That is, compaction is performed based on the second interval criterion between the fixed pattern 1 and the dummy pattern 3 in a state where the first interval criterion between the dummy pattern 3 and the moving target 2 is set. As a result,
The dummy pattern 3 serves as a fence, and compaction can be performed while maintaining the initial arrangement state of the plurality of movement target patterns 2 arranged in the same row.

This makes it possible to arrange the movement target pattern 2 at a position intended by the designer.

〔Example〕

Next, an embodiment of the present invention will be described with reference to the drawings.

2 to 4 are diagrams for explaining a pattern interval reducing method of the LSI automatic design system according to the embodiment of the present invention, and FIG. 2 is a configuration diagram relating to the LSI automatic design system of each embodiment of the present invention. Is shown.

In the figure, reference numeral 4 denotes a keyboard (input terminal device) to which a designer inputs input data D1. Reference numeral 5 denotes a main storage device for storing basic design data D2, program data, and the like necessary for automatic LSI design. Reference numeral 6 denotes a file memory for storing data during design and design file data D3.

7 is a microprocessor unit (hereinafter referred to as MPU)
The automatic design control of the LSI pattern layout is performed by the input data D1 of the designer, the design basic data of the main storage device 5, and the creation processing data D5 based on the microprogram data D2.

A printer device 8 prints out a layout drawing based on drawing data D4 relating to an automatically designed LSI pattern layout.

Reference numeral 9 denotes a display device for displaying a layout pattern in the course of automatic design on a screen based on the display data D6. The designer performs a compaction process while observing the layout pattern so that, for example, the functional module pattern and the pad pattern group comply with the design rules.

Reference numeral 10 denotes a system bus, which includes a keyboard 4, a main storage device 5,
A file memory 6, an MPU 7, a printer device 8, a display device 9, etc. are connected to transmit input data D1, design basic data D2, design file data D3, drawing data D4, creation processing data D5, and display data D6. is there.

Thus, an LSI automatic design system for automatically creating an LSI pattern layout is configured.

(I) Description of First Embodiment FIGS. 3 (a) to 3 (c) are illustrations of a method of reducing a pattern interval according to a first embodiment of the present invention, and FIG. 3 (a) shows a pattern before compaction. 1 shows a layout diagram of an LSI chip level.

In FIG. 1A, first, an LSI pattern layout is displayed on the display device 9 based on the design basic data D2 and the input data D1. At this time, the function module patterns 11a to 11d and the pad pattern group 12 are displayed on the display device 9. Also, the function module pattern 11a
Is larger than other module patterns 11b to 11c,
The side facing the reduction movement direction A is in a state of protruding, for example, about 1 μm before the sides of the patterns 11b to 11c.

Here, the designer performs compaction while keeping the initial arrangement state of the pad pattern group 12 so as to comply with a design rule that defines the approach limit distance between the functional module pattern group 11 and the pad pattern group 12, for example, the 1 μm rule. Suppose you tried to do so.

At this time, input data D1 for inserting the dummy pattern 13 between the pad pattern 12 and the function module patterns 11a to 11d is input to the keyboard 4. The dummy pattern 13 employs a straight line in the embodiment of the present invention, and its insertion position is set at an arbitrary position between the functional module pattern group 11 and the pad pattern group 12. Further, the length of the dummy pattern 13 is set according to the length of the pad pattern group 12. Next, a first constraint graph according to the 0 μm rule is set between the dummy pattern 13 and the pad pattern group 12 as a first constraint criterion.

In addition, as a second interval criterion, a second constraint graph according to the 1 μm rule is set between the dummy pattern 13 and the functional module patterns 11a to 11d. Note that the rules given as the first and second interval references may be 0.5 μm rules, 0.5 μm rules, and the like, respectively.

Based on the first and second interval criteria, as in the related art,
Analyze the constraint graph by the longest path method and execute compaction.

FIG. 1B shows a chip-level layout diagram after compaction.

In FIG. 2B, by performing compaction,
The pad pattern group 12 is reduced to an interval of 1 μm with the dummy pattern 13 interposed with respect to the functional module pattern 11a, and is reduced to an interval of 2 μm with respect to the functional module patterns 11b to 11d. That is, the pad pattern group 12 is compacted while maintaining the initial arrangement state.

FIG. 4C shows a layout diagram at a chip level in which the dummy pattern 13 is deleted.

In FIG. 1C, the pad pattern 12 is compacted at a position intended by the designer.

Thus, according to the first embodiment, the dummy pattern 13 is provided between the functional module patterns 11a to 11d and the pad pattern 12 group.

Therefore, the longest path method is indirectly applied between the functional module patterns 11a to 11d and the pad pattern with the dummy pattern 13 interposed therebetween. That is, with the first constraint graph between the dummy pattern 13 and the pad pattern group 12 stretched, the function module patterns 11a to 11a
The compaction is performed by analyzing the second constraint graph between 1d and the dummy pattern 13 by the longest path method. As a result, the dummy pattern 13 functions as a fence, and compaction can be performed while maintaining the initial arrangement state of the pad pattern groups 12 arranged in the same row.

This allows the pad pattern to be placed at the position intended by the designer.
12 can be arranged.

(Ii) Description of Second Embodiment FIGS. 4 (a) to 4 (c) are explanatory diagrams of a pattern interval reduction method according to a second embodiment of the present invention.
Shows a layout diagram at the LSI mask level before compaction.

FIGS. 7A to 7C are different from the first embodiment in that, in the second embodiment, the compaction movement of the contact hole pattern to be moved is performed together with the execution of compaction.

That is, in FIG. 1A, first, based on the design basic data D2 and the input data D1, the display device 9
Displays the LSI pattern layout. At this time, the gate pattern 21 and the contact hole patterns 22a to 22
2c, the area boundary lines a1, a2 and the area definition lines b1, b2 are displayed on the display device 9.

Here, the contact hole 22b is surrounded by the region boundary lines a1 and a2 as compared with the contact hole 22c, and the region boundary lines a1 and a2 are opposed to the contact hole 22b in the reduction movement direction A.
It is assumed that there is an access restriction to.

Under such a reduction condition, the designer can use the gate pattern 21
Is fixed and compaction is performed.

In this case, a dummy pattern 23 is inserted between the region boundary lines a1, a2 and the contact hole patterns 22b, 22c. The input data D1 related thereto is input via the keyboard 4. Next, a first constraint graph is extended between the dummy pattern 23 and the contact hole patterns 22b and 22c.

Further, a second constraint graph is extended between the area boundary lines a1 and a2 and the dummy pattern 23. Further, unlike the first embodiment, a third constraint graph is also provided between the gate pattern and the contact hole 22a and the region defining line 2b located to the left of the gate pattern 21.

The first to third constraint graphs are analyzed by the longest path method, and compaction is performed.

FIG. 1B shows a layout diagram of a mask level after compaction.

In FIG. 2B, by performing compaction,
The contact hole pattern group 22a includes the gate pattern 21
And the individual width of the pattern group 22a is also 1
μm → 0.5 μm. Further, the contact hole pattern 22b moves to the gate pattern 21 while maintaining the distance from the region boundary line a, and the width of the contact pattern 22b is reduced from 1 μm to 0.5 μm. Further, the contact hole pattern 22c is moved to the gate pattern 21 while keeping the same row as the other contact hole patterns 22b initially arranged, and the width thereof is reduced from 1 μm to 0.5 μm.

FIG. 3C shows a layout diagram of a mask level in which the dummy pattern 23 is deleted.

Thus, according to the second embodiment, the dummy pattern 23 is provided between the region boundary line a and the contact hole patterns 22b and 22c.

Therefore, similar to the first embodiment, the dummy patterns 23
The longest path method is indirectly applied between the gate pattern 21 and the contact hole patterns 22b, 22c and the area defining line b1 with the intervening. Also, the gate pattern
21 and area boundaries a1, a2, contact hole pattern group 22a
The direct longest path method is applied between the area definition line b2 and the conventional method.

As a result, the dummy pattern 23 functions as a fence as in the first embodiment, and the initial arrangement state of the contact hole patterns 22b and 22c arranged in the same row is maintained.
Can be compacted.

Thus, similarly to the first embodiment, the contact hole pattern 22c can be reduced and arranged at a position intended by the designer.

Although straight lines are used as the dummy patterns 13 and 23 in the embodiment of the present invention, the same effect can be obtained with a rectangular pattern.

〔The invention's effect〕

As described above, according to the present invention, it is possible to move a plurality of movement target patterns arranged in the same row to a position close to a fixed pattern by using a dummy pattern as a fence.

For this reason, it is possible to compact the movement target pattern at a position intended by the designer while maintaining the initial arrangement.

This greatly contributes to the improvement of the compaction function of the LSI automatic design system.

[Brief description of the drawings]

FIG. 1 is a principle diagram of a pattern reduction method of an LSI automatic design system according to the present invention, FIG. 2 is a configuration diagram of an LSI automatic design system according to each embodiment of the present invention, and FIG. FIG. 4 is an explanatory diagram of a pattern reducing method according to a first embodiment, FIG. 4 is an explanatory diagram of a pattern reducing method according to a second embodiment of the present invention, and FIG. 5 is a diagram of an LSI automatic design system according to a conventional example. FIG. 4 is an explanatory diagram of a pattern reduction method. (Explanation of reference numerals) 1... Fixed pattern 2... Movement target pattern 3... Dummy pattern A...

──────────────────────────────────────────────────続 き Continued on the front page (58) Field surveyed (Int.Cl. ⁶ , DB name) H01L 21/82 G06F 17/50

Claims (1)

(57) [Claims] An LSI for automatically creating an LSI pattern layout
In the pattern interval reducing method of the automatic design system, a plurality of moving target patterns (2) arranged in the same row in a direction orthogonal to the reducing moving direction (A), and the moving direction is reduced with respect to these moving target patterns (2). 1 opposite to (A)
Alternatively, a dummy pattern (3) composed of a line of a specific length or a pattern of a specific size is provided at an arbitrary position between the plurality of fixed patterns (1), and the movement target pattern (2) and the dummy A first interval reference is set between the fixed pattern (3) and a second interval reference is set between the dummy pattern (3) and the fixed pattern (1). The position is fixed, the distance between the dummy pattern (3) and each movement target pattern (2) maintains the first distance reference, and the distance between the fixed pattern (1) and the dummy pattern (3) is The distance between the fixed pattern (1) and each movement target pattern (2) is reduced by moving the dummy pattern (3) and each movement target pattern (2) so as to maintain the second distance reference. LSI automatic design featuring Pattern interval reduction method of the stem.