JP2842464B2 - Bias circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a bias circuit in a CMOS (complementary metal oxide semiconductor) circuit, and more particularly to a bias circuit which is less affected by fluctuations in manufacturing process conditions, temperature, power supply voltage and the like.

[0002]

2. Description of the Related Art It is particularly important for CMOS circuit design to create a bias condition that is free from fluctuations in bias current due to fluctuations in manufacturing process conditions, temperature, power supply voltage, and the like. In an integrated circuit composed of an amplifier, a level shifter, and an output buffer as shown in FIG. 2, a gate of a P-channel (ch) transistor serving as a current source is provided with a constant voltage bias circuit (FIG. 4). (A),
(B) and (c)) must be individually provided, and there is a problem that the circuit scale becomes large.

As a conventional bias circuit, the circuits (a), (b) and (c) of FIG. 4 are used. Circuit of Figure 4 has a large influence due to variations in manufacturing process, no fluctuation due to the manufacturing process, the bias current I _'10 at typical conditions is expressed by the following equation. I ′ ₁₀ = (V _DD −I ′ ₁₀ .Z2) / Z1 (1) Next, assuming that the impedance Z1 is subjected to a variation due to the manufacturing process of + 30%, the bias current I _'1 is expressed by the following equation. Here, V _DD is the power supply voltage, Z1,
Z2 is the impedance of the portion shown in FIG. I ′ ₁ = (V _DD −I ′ ₁ .Z2) / (Z1 × 1.3)

Here, assuming that I ′ ₁ = I ′ ₁₀ −ΔI ′, the bias current I ′ ₁ is as follows. I ′ ₁ = {V _DD − (I ′ ₁₀ −ΔI ′) Z2} / (Z1 × 1.3) = I ′ ₁₀ /1.3+(V _DD + ΔI ′ · Z2) / (Z1 × 1.3) (2) According to this, not only the influence of the process variation of the impedance Z1 (the first term of the equation (2)) but also the increase and decrease of the influence of the second term of the equation (2) are added. There is a problem that the output level of the connected circuit is affected.

[0005]

In addition to the above problems, the conventional bias circuit has a problem that the power supply noise rejection ratio is small. Therefore, an object of the present invention is to minimize the influence of manufacturing process fluctuations, stabilize the output of the bias circuit with a small-scale circuit, and increase the power supply noise rejection ratio. As a result, this bias circuit is used. An object of the present invention is to suppress fluctuations in circuit operation in an integrated circuit.

[0006]

According to the present invention, FIG.
, A first series circuit including a first diffusion resistance element R1 and a second diffusion resistance element R2 connected to the power supplies V _DD and GND, a first diffusion resistance element R1 and a second And a CMOS transistor element Q1, Q2 or Q1 in which a control electrode (gate) and one electrode (drain) are respectively connected to the operational amplifier 1 in which the connection point of the diffusion resistance element R2 is connected to the non-inverting input terminal. , Q4
Series circuit or CMOS transistor element Q1 and third
At least two from the third series circuit with the diffusion resistance element R, and two CMs of the second and third series circuits, respectively.
A third CMOS transistor Q3 connected between the OS elements Q1, Q2; Q1, Q4; Q1, R; the second and third series circuits are connected in parallel with the first series circuit; The sources of the third CMOS transistor Q3 are connected to each other and to the inverting input terminal of the operational amplifier 1,
The control electrodes (gates) of the CMOS transistor Q3 are connected to each other and to the output terminal of the operational amplifier 1,
Is configured to obtain a bias voltage from the drain of the CMOS transistor Q3.

In another embodiment of the present invention, the circuit further includes a connection point between a first diffusion resistance element R1 and a second diffusion resistance element R2, as exemplified by a broken line in FIG. It is configured to connect a capacitor C between the power supply and one GND.

[0008]

When the above-mentioned bias circuit is used, even if the impedance Z1 fluctuates, the voltage across the both ends is fixed at V _B (the voltage at the connection point between the resistors R1 and R2) and becomes constant. The variable element of the second term is removed, and the influence of the process fluctuation is reduced. Further, when another embodiment of the present invention is used, power supply noise is reduced as illustrated in FIG.

[0009]

FIG. 1 shows a bias circuit according to an embodiment of the present invention.
Is shown in This bias circuit includes a first diffused resistor R
1, second diffused resistor R2, operational amplifier 1, P-channel transistor Q1 (Q1-1, Q1-2, Q1-3) and N
Channel transistor Q2, N-channel transistor Q
3 (Q3-1, Q3-2, Q3-3), a P-channel transistor Q4, and a third diffused resistor R.

The resistors R1 and R2 are connected between the power supply V _DD and GND.
Are connected in series, and connected to the non-inverting terminal (+) of the operational amplifier 1 from the connection point of the resistors R1 and R2. The transistors Q1-1, Q3-1, and Q2 are connected in series between the power supply _VDD and GND, and the transistors Q1-2, Q3-2,
Q4 is connected in the same manner, and the transistors Q1-3 and Q3
-3 and the resistor R are similarly connected. Transistor Q1
-1 to Q1-3, Q2, and Q4 are each called diode connection in which the drain and the gate (control terminal) are connected. Transistors Q1-1, Q1-2, Q1
The source of -3 is connected to the power supply _VDD .

The transistors Q1-1, Q1-2, Q1-
3 have transistors Q3-1 and Q3-
2, Q3-3, and outputs of biases 1, 2, and 3 are obtained from this connection point. Transistor Q3
The gates of -1, Q3-2 and Q3-3 are all connected to the output terminal of the operational amplifier 1. Transistors Q3-1, Q
All sources of 3-2 and Q3-3 are connected to the inverting input terminal (-) of the operational amplifier 1. The source of the transistor Q2 is connected to the ground GND, which is the other side of the power supply, and the drain of the transistor Q4 is also connected to GND. The source of transistor Q3-1 and the drain of transistor Q2 are connected, and the source of transistor Q3-2 is connected to the source of transistor Q4. One end of the resistor R is connected to GND and the other end is connected to the source of the transistor Q3-3.

Under typical conditions without process variation, the current flowing through the transistors Q2 and Q4 and the resistor R is I ₁₀ = V _B / Z1...... …………… (3) Here V _B a voltage at the non-inverting terminal of the operational amplifier 1, which is equal to the voltage at the inverting terminal. Z
1 is the impedance of the transistors Q2, Q4 and the resistor R.

[0013] Here, the bias current I ₁ in the case where the impedance Z1 is subjected to + 30% of the process _{variations, I 1 = V B /Z1×1.3=I 10} /1.3 ..................... ... (4), and does not include the element of the second term of Expression (2). Voltage V
_B is a resistor R1, R2 which is not affected by process variations.
Of the power supply voltage V _DD , which is usually about ± 5% to about ± 10%, and generally has a variation of ± 30%. Is smaller than the variation of the drain current value of −50% to + 200% due to the threshold voltage variation of FIG.

The biases 1 to 3 in FIG. 1 are selectively used depending on the application depending on the balance of a circuit connected in the subsequent stage, for example, the N-channel transistor and the P-channel transistor in FIG. In addition, based on the point A, the impedance Z1 can be connected in multiple stages to each of the bias circuits formed by the N-channel transistor, the P-channel transistor, and the resistor R. Although the three-output bias circuit has been described in the above-described embodiment, the number of outputs can be any number. That is, the circuit of Q1, Q2, Q3, Q1,
Any number of Q3, Q4 circuits and Q1, Q3, R circuits can be provided.

A modification of the embodiment of the present invention is shown with the addition of the circuit shown in dashed lines in FIG. In this bias circuit, a power supply noise rejection ratio of 20 dB is secured.
It can also be used as a measure against VRR (Supply Voltage Noise Rejection Ratio). Compared with a conventional bias circuit, an improvement in the rejection ratio of about 10 dB can be expected. This aspect is shown in FIG. 3 by calculation by a computer.
That is, when the capacitor 10 μF is used as C (broken line), an improvement of 10 dB or more (about 13 dB at low frequency) is possible as compared with the case without C (solid line).

[0016]

According to the present invention, the influence of fluctuations in the manufacturing process can be minimized and the output of the bias circuit can be stabilized with a small-scale circuit. According to another embodiment of the present invention, the power supply noise rejection ratio can be increased. In addition, fluctuations in circuit operation can be suppressed in an integrated circuit using this bias circuit.

[Brief description of the drawings]

FIG. 1 is a circuit diagram of a bias circuit as one embodiment of the present invention.

FIG. 2 is a circuit diagram of an integrated circuit to which the present invention is applied.

FIG. 3 is a characteristic diagram showing a calculation result by a computer for explaining an increase in a power supply noise rejection ratio in a modification of the embodiment of the present invention.

FIG. 4 is a circuit diagram showing a conventional bias circuit.

[Explanation of symbols]

Reference Signs List 1 operational amplifier Q1-1, Q1-2, Q1-3 P-channel transistor Q2 N-channel transistor Q3-1, Q3-2, Q3-3 N-channel transistor Q4 P-channel transistor R, R1, R2 R11, R12: diffusion resistance R13: resistance C: capacitor

────────────────────────────────────────────────── ─── Continued on the front page (72) Inventor Yasuaki Takeuchi 2-1-1 Kita-Jo Nishi, Chuo-ku, Sapporo-shi, Hokkaido Fujitsu Hokkaido Digital Technology Co., Ltd. (58) Field surveyed (Int.Cl. ⁶ , DB name) G05F 1/00

Claims (2)

(57) [Claims] 1. A first diffused resistance element (R1) and a second diffused resistance element (R1) connected to a power supply (V _DD , GND).
2) a first series circuit, and an operational amplifier (1) having a connection point between the first diffusion resistance element (R1) and the second diffusion resistance element (R2) connected to a non-inverting input terminal. , Two Cs each having a control electrode and one electrode connected
MOS transistor element (Q1, Q2 or Q1, Q2
4) at least two of the second series circuit or the third series circuit of the CMOS transistor element (Q1) and the third diffusion resistance element (R), and each of the second and third series circuits. And a third CMOS transistor (Q3) connected between the two CMOS devices (Q1, Q2; Q1, Q4; Q1, R). And the sources of the third CMOS transistor (Q3) are connected to each other, connected to the inverting input terminal of the operational amplifier (1), and connected to the control electrode of the third CMOS transistor (Q3). Are connected to each other and to the output terminal of the operational amplifier (1), and the third CMOS transistor (Q3)
A bias circuit that obtains a bias voltage from the drain of the bias circuit. 2. The first diffusion resistance element (R1) and a second diffusion resistance element (R1).
And one of the power supplies (GN)
2. A bias circuit according to claim 1, wherein a capacitor (C) is connected between the bias circuit and D).