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JP2844259B2 - Manufacturing method of flat electronic components - Google Patents
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JP2844259B2 - Manufacturing method of flat electronic components - Google Patents

Manufacturing method of flat electronic components

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Publication number
JP2844259B2
JP2844259B2 JP33573990A JP33573990A JP2844259B2 JP 2844259 B2 JP2844259 B2 JP 2844259B2 JP 33573990 A JP33573990 A JP 33573990A JP 33573990 A JP33573990 A JP 33573990A JP 2844259 B2 JP2844259 B2 JP 2844259B2
Authority
JP
Japan
Prior art keywords
electrode
electronic component
chip
insulating substrate
drying
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
JP33573990A
Other languages
Japanese (ja)
Other versions
JPH04206762A (en
Inventor
正明 川地
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
AOI DENSHI KK
Original Assignee
AOI DENSHI KK
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by AOI DENSHI KK filed Critical AOI DENSHI KK
Priority to JP33573990A priority Critical patent/JP2844259B2/en
Publication of JPH04206762A publication Critical patent/JPH04206762A/en
Application granted granted Critical
Publication of JP2844259B2 publication Critical patent/JP2844259B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

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  • Apparatuses And Processes For Manufacturing Resistors (AREA)
  • Details Of Resistors (AREA)

Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明は、高密度な面実装の可能な平型電子部品の製
造方法に関する。
The present invention relates to a method of manufacturing a flat electronic component capable of high-density surface mounting.

〔従来の技術〕[Conventional technology]

従来平型電子部品として、電子部品の電極にリード線
を接続して横方向に取り出し、電子部品及びリード線の
一部に樹脂モールドを施したものが知られている。
2. Description of the Related Art Conventionally, a flat electronic component is known in which a lead wire is connected to an electrode of an electronic component and taken out in a lateral direction, and a part of the electronic component and the lead wire is subjected to resin molding.

しかし、従来のモールド電子部品は、リード線が横方
向に延長しているために、プリント基板に面実装する
際、前記リード線が横に延長した分だけ面実装面積が広
くなり、それだけ高密度な面実装が困難になるという問
題点があった。
However, in conventional molded electronic components, since the lead wires extend in the horizontal direction, when surface-mounted on a printed circuit board, the surface mounting area is increased by an amount corresponding to the horizontal extension of the lead wires, and the high density There is a problem that it is difficult to mount the device on a surface.

〔発明が解決しようとする課題〕[Problems to be solved by the invention]

本発明は、高密度な面実装が可能な平型電子部品を提
供できる製造方法に関する。
The present invention relates to a manufacturing method capable of providing a flat electronic component capable of high-density surface mounting.

〔課題を解決するための手段〕[Means for solving the problem]

絶縁基板に貫通孔を設け、1次電極がその2つの端子
にそれぞれ接着された電子部品を前記孔内の電子部品保
持部に装着し、前記絶縁基板の表面に形成した電極取り
出し導体を前記両1次電極に接続した構造をとることに
より前記問題点を解決するもので、本発明は、前記構造
の電子部品を提供する製造方法であって以下詳細に説明
する。
A through hole is provided in the insulating substrate, an electronic component having a primary electrode bonded to its two terminals is mounted on an electronic component holding portion in the hole, and the electrode extraction conductor formed on the surface of the insulating substrate is connected to the two terminals. This problem is solved by adopting a structure connected to a primary electrode, and the present invention is a manufacturing method for providing an electronic component having the above structure, and will be described in detail below.

〔実施例〕〔Example〕

本発明の製造工程を以下図に基づいて説明する。 The manufacturing process of the present invention will be described below with reference to the drawings.

スリット2を縦横に施した分割可能なアルミナ・セラ
ミック基板1のシートに金型等で、表裏に貫通した穴加
工をした絶縁基板を用意する。孔3の形状は、電子部品
の外形に対応した形状、例えば矩形や丸状に形成すると
ともに電子部品保持部となる段差部4を設ける。(第1
図) 次に、前記アルミナ・セラミック基板1の孔3の段差
部4に、一方の1次電極となる、Fe−NiシートにPb−Sn
等のメッキを施した第1の電極チップ5を載置し、真空
吸引により段差部4に保持するとともに、前記第1の電
極チップ5上にダイオードチップDを載せ、さらにダイ
オードD上に他方の1次電極となるFe−NiシートにPb−
Sn等のメッキを施した第2の電極チップ6を載せる。
(第2図) 次に、前記状態で、アルミナ・セラミックス基板1を
250〜300℃にヒータブロック7又はオーブン炉(図示せ
ず)で加熱し、前記両電極チップにメッキしたPb−Snを
溶解し、ダイオードチップの裏面側8とバンプ側9を半
田付けする。(第3図) 次に、上記半田付けされた状態のダイオードチップを
下方の孔より真空吸着で段差部4に保持し、第2の電極
チップ6及びアルミナ・セラミック基板1の表面に厚膜
スクリーン印刷により、第1の電極取り出し導体10及び
後述する2次電極を形成するメッキ工程の下地となる導
体11を、低温乾燥用銀ペーストを施して形成し、150〜1
80℃にオーブン炉で加熱し乾燥する。(第4図) 次に、絶縁体保護膜12を前記第1の電極取り出し導体
10の一部及びアルミナ・セラミック基板上1に、低温乾
燥用ガラスペースト材を用いてスクリーン印刷にて施
し、150〜180℃にオーブン炉で加熱し乾燥させる。(第
4図) 次に、段差部4を形成する径の小さい孔13に、銀ペー
ストが埋め込まれると同時にアルミナ・セラミック基板
上に銀ペーストを厚膜スクリーン印刷にて施し、電極取
り出し用埋め込み導体14と第2の電極取り出し導体15を
形成し、150〜180℃にオーブン炉で加熱し乾燥させる。
このとき、前述と同様2次電極の下地となる導体16も同
時に形成する。(第5図) 次に、絶縁保護膜17を前記第2の電極取り出し導体15
の一部及びアルミナ・セラミック基板1上に、低温乾燥
用ガラスペースト材を用いてスクリーン印刷にて施し、
150〜180℃にオーブン炉で加熱し乾燥させる。(第5
図) 次に、アルミナ・セラミック基板1をスリット部より
短冊状に分割し、端面に印刷又はディップ方式により前
記各電極取り出し導体と同じ銀ペースト材を使用して端
面の電極18、19を施し、150〜180℃にオーブン炉で加熱
し乾燥させる。(第6図) 次に、前記分割した短冊状のアルミナ・セラミック基
板を、さらにスリット部より分割し、チップ状にしたも
のにバレルメッキ等でコ字状の2次電極20、21を形成す
る。(第7図) 以上の工程を経て前記問題点を解決できる平型電子部
品を製造できるが、その後、特性の測定チェックを行
い、特性の方向を示すマーキングを施すことにより完成
する。
An insulative substrate is prepared by punching holes on the front and back sides of a dividable alumina ceramic substrate 1 sheet having slits 2 formed vertically and horizontally by using a mold or the like. The shape of the hole 3 is formed in a shape corresponding to the outer shape of the electronic component, for example, a rectangular or round shape, and a step portion 4 serving as an electronic component holding portion is provided. (First
Next, Pb-Sn is added to the Fe-Ni sheet, which serves as one primary electrode, at the step 4 of the hole 3 of the alumina-ceramic substrate 1.
The first electrode chip 5 plated with, for example, is placed and held on the step portion 4 by vacuum suction, the diode chip D is placed on the first electrode chip 5, and the other is placed on the diode D. Pb- on Fe-Ni sheet to be primary electrode
The second electrode chip 6 plated with Sn or the like is mounted.
(FIG. 2) Next, in the above state, the alumina-ceramic substrate 1 was removed.
Heating is performed at 250 to 300 ° C. in a heater block 7 or an oven furnace (not shown) to melt the Pb—Sn plated on the two electrode chips, and solder the back surface 8 and the bump side 9 of the diode chip. (FIG. 3) Next, the diode chip in the soldered state is held on the step portion 4 by vacuum suction from a lower hole, and a thick film screen is formed on the surface of the second electrode chip 6 and the alumina ceramic substrate 1. By printing, a first electrode extraction conductor 10 and a conductor 11 serving as a base for a plating step for forming a secondary electrode described later are formed by applying a low-temperature drying silver paste,
Heat and dry in an oven at 80 ° C. (FIG. 4) Next, the insulator protective film 12 is placed on the first electrode extraction conductor.
A portion of 10 and on the alumina ceramic substrate 1 are screen-printed using a glass paste material for low-temperature drying, and heated to 150 to 180 ° C. in an oven furnace to be dried. (FIG. 4) Next, the silver paste is buried in the hole 13 having a small diameter forming the stepped portion 4 and, at the same time, the silver paste is applied on the alumina ceramic substrate by thick-film screen printing, and the buried conductor for taking out the electrode is formed. 14 and the second electrode lead-out conductor 15 are formed, heated to 150 to 180 ° C. in an oven furnace and dried.
At this time, the conductor 16 serving as the base of the secondary electrode is formed at the same time as described above. (FIG. 5) Next, the insulating protection film 17 is placed on the second electrode lead-out conductor 15.
Is applied by screen printing using a glass paste material for low-temperature drying on a part of the
Heat in oven furnace to 150-180 ° C and dry. (Fifth
Next, the alumina-ceramic substrate 1 is divided into strips from the slits, and the electrodes 18 and 19 on the end faces are applied to the end faces by printing or dipping using the same silver paste material as the electrode extraction conductors. Heat in oven furnace to 150-180 ° C and dry. (FIG. 6) Next, the strip-shaped alumina-ceramic substrate thus divided is further divided from the slit portion, and the chip-shaped one is formed with U-shaped secondary electrodes 20 and 21 by barrel plating or the like. . (FIG. 7) A flat electronic component that can solve the above-mentioned problems can be manufactured through the above steps. However, after that, the characteristics are measured and checked, and marking is performed to indicate the direction of the characteristics.

〔発明の効果〕〔The invention's effect〕

本発明製造方法により高密度な面実装の可能な平型電
子部品の製造が可能となり、さらに低温乾燥用ガラスペ
ーストにより絶縁保護膜を形成できるから、電子部品製
造時において、ダイオード等の電子部品を高温で加熱す
ることがないため、高温加熱による電子部品の破損を免
れ、製造歩留まりを向上することができる。
The manufacturing method of the present invention makes it possible to manufacture a flat electronic component capable of high-density surface mounting, and furthermore, it is possible to form an insulating protective film with a glass paste for low-temperature drying. Since heating is not performed at a high temperature, breakage of electronic components due to high-temperature heating can be avoided, and the production yield can be improved.

【図面の簡単な説明】[Brief description of the drawings]

第1図乃至第7図は、本発明製造方法の工程を説明する
図である。 1……絶縁基板、2……スリット、3……孔、4……段
差部、5、6……1次電極チップ、D……ダイオードチ
ップ、7……ヒータブロック、10、15……電極取り出し
導体、14……埋め込み導体、12、17……絶縁保護膜、1
8、19……端面電極、20、21……2次電極
1 to 7 are views for explaining the steps of the manufacturing method of the present invention. DESCRIPTION OF SYMBOLS 1 ... Insulating substrate, 2 ... Slit, 3 ... Hole, 4 ... Step part, 5, 6 ... Primary electrode chip, D ... Diode chip, 7 ... Heater block, 10, 15 ... Electrode Take-out conductor, 14 ... embedded conductor, 12, 17 ... insulating protective film, 1
8, 19 ... End face electrode, 20, 21 ... Secondary electrode

Claims (2)

(57)【特許請求の範囲】(57) [Claims] 【請求項1】以下の工程からなる平型電子部品の製造方
法。 分割可能なスリットを縦横に施した絶縁基板を用意する
工程、 前記絶縁基板の前記スリットで囲まれた各基板部分に、
表裏に貫通し、電子部品を保持できる孔を形成する工
程、 前記電子部品を保持できる孔に、一方の1次電極とな
る、半田メッキを施した第1の1次電極チップを装着
し、真空吸着により保持する工程、 前記第1の1次電極チップ上に電子部品を載せ、さらに
その上に他方の1次電極となる、半田メッキを施した第
2の1次電極チップを載せる工程、 前記絶縁基板を加熱し、前記電極チップにメッキした半
田を溶解し、電子部品の端子部に電極チップを半田付け
する工程 前記電極チップが半田付けされた電子部品を真空吸着に
より前記電子部品保持部に保持し、圧膜スクリーン印刷
により第2の1次電極チップの表面及び絶縁基板表面
に、第1の電極取り出し導体を形成する低温乾燥用導電
ペーストを塗布し、加熱乾燥する工程、 前記第1の電極取り出し導体に低温乾燥用ガラスペース
トをスクリーン印刷により塗布し、加熱乾燥する工程、 前記第1の1次電極チップ側の孔に埋め込むと同時に、
絶縁基板表面に第2の電極取り出し導体を形成する低温
乾燥用導電ペーストを塗布し、加熱乾燥する工程、 前記第2の電極取り出し導体に低温乾燥用ガラスペース
トをスクリーン印刷により塗布し、加熱乾燥する工程、 前記絶縁基板をスリット部より短冊状に分割する工程、 前記短冊状に分割した絶縁基板の端面に、端面電極を形
成する導電ペーストを塗布し、加熱乾燥する工程、 前記短冊状絶縁基板をスリット部よりさらに分割し、チ
ップ状電子部品に形成する工程、 前記各電極取り出し導体及び前記各端面電極にそれぞれ
2次電極をメッキする工程、
1. A method for manufacturing a flat electronic component comprising the following steps. A step of preparing an insulating substrate having a slit that can be divided vertically and horizontally, on each substrate portion of the insulating substrate surrounded by the slit,
Forming a hole that penetrates the front and back to hold an electronic component; mounting a solder-plated first primary electrode chip to be one of the primary electrodes in the hole that can hold the electronic component; Holding by suction, placing an electronic component on the first primary electrode chip, and placing a solder-plated second primary electrode chip thereon as the other primary electrode; A step of heating the insulating substrate, dissolving the solder plated on the electrode chip, and soldering the electrode chip to a terminal of the electronic component; and vacuuming the electronic component to which the electrode chip is soldered to the electronic component holding portion. Holding and applying a low-temperature drying conductive paste for forming a first electrode lead-out conductor to the surface of the second primary electrode chip and the surface of the insulating substrate by pressure film screen printing, and heating and drying the paste. Electrode extraction low temperature drying glass paste was applied by screen printing a conductor, drying by heating, when embedded in the first primary electrode tip side of the hole at the same time,
A step of applying a conductive paste for low-temperature drying for forming a second electrode lead-out conductor on the surface of the insulating substrate and heating and drying; applying a glass paste for low-temperature drying to the second electrode lead-out conductor by screen printing and drying by heating; A step of dividing the insulating substrate into strips from the slit portion, a step of applying a conductive paste for forming an end face electrode to an end surface of the insulating substrate divided into strips, and a step of drying by heating; A step of further dividing the chip from the slit portion and forming the chip-shaped electronic component; a step of plating a secondary electrode on each of the electrode extraction conductors and the end electrodes;
【請求項2】電子部品を保持できる保持部を、段差部を
有する形状としたことを特徴とする請求項(1)記載の
平型電子部品の製造方法。
2. The method according to claim 1, wherein the holding portion capable of holding the electronic component has a shape having a step portion.
JP33573990A 1990-11-30 1990-11-30 Manufacturing method of flat electronic components Expired - Fee Related JP2844259B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP33573990A JP2844259B2 (en) 1990-11-30 1990-11-30 Manufacturing method of flat electronic components

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP33573990A JP2844259B2 (en) 1990-11-30 1990-11-30 Manufacturing method of flat electronic components

Publications (2)

Publication Number Publication Date
JPH04206762A JPH04206762A (en) 1992-07-28
JP2844259B2 true JP2844259B2 (en) 1999-01-06

Family

ID=18291934

Family Applications (1)

Application Number Title Priority Date Filing Date
JP33573990A Expired - Fee Related JP2844259B2 (en) 1990-11-30 1990-11-30 Manufacturing method of flat electronic components

Country Status (1)

Country Link
JP (1) JP2844259B2 (en)

Also Published As

Publication number Publication date
JPH04206762A (en) 1992-07-28

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