JP2844654B2 - Method for manufacturing semiconductor memory device - Google Patents

Description

Description: TECHNICAL FIELD The present invention relates to a method for manufacturing a semiconductor memory device,
The present invention relates to a method for manufacturing an ultraviolet erasing semiconductor memory device having a gate having a two-layer structure.

[Prior Art] As shown in FIG. 4, a conventional semiconductor memory device of this type is formed in a P ⁺ diffusion tank 3 provided on a P-type semiconductor substrate 1 so as to be surrounded by a silicon oxide film 6. The N ⁺ diffusion tank 14 is used as a source / drain region, the polysilicon film 8 formed via the silicon oxide film 7 as a gate oxide film is used as a first gate electrode, and a silicon oxide film as an interlayer insulating film is formed thereon. A transistor using the polysilicon film 10 formed through the second gate electrode 9 as a second gate electrode is used as a memory cell. The first and second gate electrodes are covered with a silicon oxide film 13, and the surface of the semiconductor substrate is covered with a BPSG film 20.

In this transistor, the polysilicon film 10 and the polysilicon film 8 are formed to have the same dimensions by anisotropic etching using the same photoresist film, and N-type impurities are ion-implanted using these polysilicon films as a mask. N ⁺ diffusion layer
Created by forming 14.

[Problems to be Solved by the Invention] As shown in FIG.
Since the gate lengths of the first gate electrode (polysilicon film 8) and the second gate electrode (polysilicon film 10) have the same dimensions, the charge injected into the first gate electrode is irradiated with ultraviolet light. UV light emitted vertically when emitted
A2 does not enter the polysilicon film 8, and only the obliquely incident ultraviolet light B2 enters the polysilicon film 8 while being reflected between the semiconductor substrate 1 and the polysilicon film 8. Therefore, in the conventional device, ultraviolet light incident on the polysilicon film 8 is only a small part of the irradiation light, and it takes a long time to erase the memory.

The etching of the lower polysilicon film 8 is performed using the photoresist film and the polysilicon film 10 as a mask, but this etching is slightly over-etched in order to completely etch the polysilicon film 8. Alternatively, the gate oxide film may be removed by etching after etching the polysilicon film 8. At the time of etching such a silicon oxide film, oxygen gas is released, and this etches the polysilicon immediately above. Therefore, a phenomenon occurs in which the length of the lower gate electrode is shorter than that of the upper gate electrode. If the gate length of the upper layer gate electrode is medium, when the source / drain region is formed by ion implantation using the two-layer gate electrode by a self-alignment method, the distance between the source and drain is increased by the upper gate. Since it is determined by the electrode length, a so-called offset structure in which the lower gate electrode is isolated from the source and the drain, respectively. Since the semiconductor memory device having such a structure causes an operation failure, a high yield cannot be expected according to the conventional manufacturing method.

Further, in the transistor having such an offset structure, ultraviolet rays are more unlikely to be incident on the first gate electrode, and a longer time is required for memory erasing.

[Means for Solving the Problems] According to the method of manufacturing a semiconductor memory device of the present invention, a step of forming a gate insulating film on a semiconductor substrate and a step of continuously depositing a first gate electrode forming material film and forming a Forming an interlayer insulating film, then depositing a second gate electrode forming material film, forming a second gate electrode using an isotropic ion etching method, and forming a second gate electrode on the side wall of the second gate transmission. A step of forming a sidewall protective film, a step of forming a first gate electrode by using an anisotropic ion etching method, and a step of forming a diffusion layer of a reverse conductivity type with a semiconductor substrate by using ion implantation. Have.

[Example] Next, an example of the present invention will be described with reference to the drawings.

1A to 1F are cross-sectional views of a semiconductor device showing process steps according to one embodiment of the present invention.

First, as shown in FIG.
A silicon oxide film 2 is formed thereon at a film pressure of about 5000 ° by a thermal oxidation method, and the silicon oxide film is selectively wet-etched by a photolithography technique. Thereafter, a silicon oxide film is formed again, and subsequently, boron is ion-implanted and heat treatment is performed to form a P ⁺ diffusion layer 3.

Next, the silicon oxide film 2 is removed, a silicon oxide film 4 is formed again at about 500 °, and a silicon nitride film 5 is
The silicon nitride film 5 is deposited by a VD method, and the silicon nitride film 5 is selectively removed by etching using a photolithography technique. Thereafter, a silicon oxide film 6 is formed to a thickness of about 6000 ° by a thermal oxidation method (FIG. 1B).

Subsequently, the silicon nitride film 5 and the silicon oxide film 4 are sequentially removed, a silicon oxide film 7 is formed again to a thickness of about 600 ° by using a thermal oxidation method, and then a polysilicon film 8 is formed by using a CVD method. Deposit about 4000 °, and then apply phosphorus to the polysilicon film 8 by using a thermal diffusion method at 1 × 10 ¹⁸ to 1 × 10 ²⁰ atm / cm.
Introduce about ^three . Thereafter, a silicon oxide film 9 is formed to a thickness of about 400 ° on the polysilicon film 8 by a thermal oxidation method, and then a polysilicon film 10 is deposited to a thickness of about 5000 °, and phosphorus is again applied to the polysilicon film 10 by a thermal diffusion method. 1 × 10 ¹⁸ 〜
About 1 × 10 ²⁰ atm / cm ^{3 is} introduced. Thereafter, a photoresist film 11 is selectively provided, and using the photoresist film 11 as a mask, the polysilicon film is formed using an isotropic reactive ion etching method.
Etch 10 In this etching, when Nidec Anelva ILD-4002 is used, the degree of vacuum is 25 Pa, the ion etching power (RF output) is 500 W, and the gas flow rate is CCl ₂ F ₂ ; 3.
This is performed for about 6 minutes under the conditions of 0 cc / min, N ₂ ; 10 cc / min. At this time, the polysilicon film 10 has a thickness of 0.3 μm with respect to the photoresist size.
m side etching is included. Thereafter, in the above-described apparatus, the degree of vacuum was maintained at about 7 Pa, the etching power was about 800 W, and CHF ₃ , CF ₄ , and H ₂ gas were each supplied at 30 cc / mi.
Flow for about 10 minutes at a mixing ratio of n, 20 c / min, 20 cc / min,
As shown in FIG. 1 (c), a sidewall protective film 12 made of a carbon-based compound is
It is formed to a thickness of about μm.

Next, the silicon oxide film 9 is etched using the ion etching method for about 2 minutes, and then the polysilicon film 8 is etched using the strongly anisotropic ion etching method (FIG. 1D). In this etching, the degree of vacuum is 12 Pa,
Etching power 800W, gas flow rate, CCl ₂ F ₂ ; 15cc / mi
Perform for about 2 minutes under the conditions of n and N ₂ ; 15 cc / min. In this etching, the polysilicon film 10 on which the sidewall protection film 12 is adhered together with the photoresist film 11 is used as a mask, so that the dimension of the polysilicon film 8 is longer than the polysilicon film 10 by at least the sidewall protection film 12.

Thereafter, the photoresist film 11 and the sidewall protection film 12 are removed, and the silicon oxide film 13 is formed to a thickness of 200 to 3 using a thermal oxidation method.
It is formed to about 00 °. Subsequently, arsenic is ion-implanted to form an N ⁺ diffusion layer 14 serving as a source / drain region. Next, a BPSG film 20 is deposited to a thickness of about 10,000 ° using a CVD method, and a heat treatment at about 900 ° C. is performed to reflow the BPSG (FIG. 1E).

After that, a contact hole was opened by photolithography technology, and aluminum was
Aluminum is deposited by about 0 °, and aluminum is selectively removed by photolithography to form aluminum wiring 15 (FIG. 1 (f)). Then 450
Heat treatment of about ° C.

In this embodiment, the side wall protective film 12 is formed of a carbon-based compound product.
While etching the oxide film 9 by appropriately setting the etching conditions described above, a protective film may be formed from this material.

In the semiconductor memory device thus formed, as shown in FIG. 2, at the time of ultraviolet irradiation, in addition to the oblique component incident light B2 also used in the conventional example, the vertical component A1 having the highest irradiation energy is used. Directly enter the polysilicon film 8. In addition, the oblique component incident light B1 is absorbed by the polysilicon film 8 while being repeatedly reflected between the polysilicon films 8 and 10. Therefore, the amount of light incident on the polysilicon film 8 is greatly increased, and the memory erasing time can be reduced by 20 to 40%.

By the way, when the upper gate electrode is extremely short with respect to the lower gate electrode, the controllability of the upper gate electrode is deteriorated. However, according to the present embodiment, the polysilicon film 10 has the thickness of the sidewall protection film 12. Since the gate electrode is only shorter than the polysilicon film 8, the controllability of the electrode is not deteriorated by shortening the gate electrode.

Next, another embodiment of the present invention will be described with reference to FIG. FIG. 3 is a sectional view showing a process step corresponding to FIG. 1 (c). In this embodiment, after the polysilicon film 10 is formed, the polysilicon film 10 is formed before the photoresist film 11 is formed. The surface of the silicon film 10 is subjected to oxygen plasma processing. By doing so, the adhesion between the polysilicon film 10 and the photoresist film is impaired, so that a taper is formed at the end of the polysilicon film 10 after the end of the etching.
Subsequent steps are the same as in the previous embodiment.

According to this embodiment, the taper is formed at the end of the polysilicon film 10, so that the ultraviolet rays are more easily incident on the polysilicon film 8, and the memory erasing time is shortened.
However, since the size of the lower surface of the polysilicon layer 10 is not different from that of the previous embodiment, the controllability of the gate electrode is not different from that of the previous embodiment.

[Effects of the Invention] As described above, according to the present invention, the amount of ultraviolet light incident on the lower gate electrode is greatly increased, so that the memory erasing time can be shortened.

Further, according to the manufacturing method of the present invention, since the lower polysilicon film is etched using the upper gate electrode to which the side wall protective film is attached as a mask, the gate length of the upper gate electrode is reduced by the lower gate electrode. It can be shorter than that. At that time, the dimensional difference can be accurately processed. Then, since the source / drain regions are formed in a self-aligned manner using the stacked gate electrodes processed in this manner, the transistor does not have an offset structure, and stable operation of the transistor is possible, and the yield is improved. Can be improved.

[Brief description of the drawings]

1 (a) to 1 (f) are cross-sectional views of a semiconductor device showing a sequence of manufacturing steps according to one embodiment of the present invention, FIG. 2 is an explanatory view of the operation of the semiconductor device according to this embodiment, and FIG. FIG. 4 is a sectional view of a conventional semiconductor device for explaining another embodiment, and FIG. 4 is a sectional view of a conventional example. DESCRIPTION OF SYMBOLS 1 ... P type semiconductor substrate, 2, 4, 6, 7, 9, 13 ... Silicon oxide film, 3 ... P ⁺ diffusion layer, 5 ... Silicon nitride film, 8, 10 ... Polysilicon film, 11 ...... Photoresist film, 12 ... sidewall protective film, 14 ... N ⁺ diffusion layer, 15 ... Aluminum wiring, 20 ... BPSG film.

Claims (1)

(57) [Claims] A step of sequentially forming a gate insulating film, a first gate electrode forming material film, an interlayer insulating film, and a second gate electrode forming material film on a semiconductor substrate of a first conductivity type; Selectively forming a photoresist film on the gate electrode forming material film; and performing isotropic etching on the second gate electrode forming material film using the photoresist film as a mask to form a second gate electrode. Forming; forming a sidewall protection film on sidewalls of the second gate electrode;
Forming a first gate electrode by performing anisotropic etching on the first gate electrode forming material film using the second gate electrode on which the photoresist film and the sidewall protection film are formed as a mask; Forming a source / drain region by introducing a second conductivity type impurity into the semiconductor substrate using the second gate electrode as a mask.