JP2844940B2 - Method of forming alignment mark - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for forming an alignment mark.

[0002]

2. Description of the Related Art Conventionally, in an image sensor used for a facsimile or the like, a sensor unit composed of light receiving element rows is formed directly on a substrate by photolithography technology, and a control IC is mounted on the substrate on which the sensor unit is formed. The chip was mounted. In recent years, a plurality of image sensor IC chips and a control IC for controlling these sensor ICs have been developed.
A method of mounting a C chip on a wiring board has been proposed.
When a plurality of image sensor IC chips are mounted in a horizontal row, mounting errors are directly output as sensor reading errors, so that it is necessary to accurately position each sensor IC chip.

That is, as shown in FIG. 3, the positioning of each image sensor IC chip CP is performed by two IC chips CP.
Is adjusted so that the interval between adjacent outer light receiving elements in both IC chips CP corresponds to the pixel pitch.
The distance GP between the IC chips CP must be accurately determined and aligned using the alignment mark AM. Therefore, an alignment mark AM that can be accurately positioned on a wiring board is required.

[0004]

However, it has been difficult to form a pattern of an alignment mark AM indicating a gap GP corresponding to one pixel pitch at a chip mount position by photolithography. That is, since the interval (slit) between the marks AM is the gap GP, the width of the slit is very short, and it is very difficult to produce the slit in a process. Therefore, as shown in FIG. 4, when the respective alignment marks AM are formed at positions that are not adjacent to each other and are separated from the chip mounting position, the positioning of the sensor IC chip CP is performed based on the relative coordinates from the separated alignment mark AM. Will be used for positioning. As a result, it was not possible to check at a glance, and measurement was troublesome.

SUMMARY OF THE INVENTION The present invention has been made to solve the above problems, and has as its object to form a mark at a position closest to a chip mount position without being limited to a mark forming position. It is an object of the present invention to provide a method of forming an alignment mark which can improve the positioning accuracy and increase the efficiency of the positioning inspection.

[0006]

Since the present invention SUMMARY OF] is to solve the above problems, a phase opposed alignment mark pairs for arranging at least two chips at a predetermined interval, the side of the chip which faces respectively The gist is to displace the sides indicating the edges so as not to oppose each other.

[0007]

Therefore, according to the present invention, the relative intervals between the alignment mark pairs are determined on each side by displacing the sides indicating the chip edges on the opposite side of the alignment mark pairs so as not to oppose each other. At this interval, the chip interval can be set to a very short interval. Since the sides that determine the interval do not face each other, it is not necessary to form a slit-shaped alignment mark pattern with a narrow interval.

[0008]

FIG. 1 shows an embodiment of the present invention.
Explanation will be made according to 2. A wiring pattern 2 of aluminum or the like is formed on a substrate 1 by a lithography process, and a chip mount 3 is continuously formed on the wiring pattern 2.
a, 3b are formed in plurality. A sensor IC is mounted on the upper surfaces of the chip mounts 3a and 3b via an insulator.
The chips 5 are arranged at predetermined intervals.

Each of the chip mounts 3a and 3b also serves as an alignment mark, and an alignment mark pair 4 is formed on both sides facing each other. The alignment mark pair 4 has a protrusion 6 formed on one of the chip mounts 3a.
a and a protrusion 6b formed on the other chip mount 3b.
It is composed of The protrusions 6a and 6b are formed so as to be displaced so as not to face each other.

Further, as shown in FIG. 2, an edge 7a as a side of the projection 6a and an edge 7b as a side of the projection 6b
When the gaps with respect to each other are viewed relatively, a predetermined gap G
(In this embodiment, 10 μm). That is, the gap G is defined by each of the chip mounts 3a,
When sensor IC chip 5 is mounted on 3b, both ICs
The gap between adjacent light receiving elements of the chip 5 is set to be one pixel pitch.

[0011] A projection 6 serving as the alignment mark pair 4
The relative gap G between the edge 7a of a and the edge 7b of the protrusion 6b is formed as follows. For example, as shown in FIG. 2, a protrusion 6 a of 100 μm is formed below the right end of the chip mount 3 a toward the left end of the chip mount 3 b, and 100 μm from the edge 7 a of the protrusion 6 a.
The chip mount 3b is formed as the left end of the chip mount 3b facing with a gap of μm. Then, a projection 6b of 90 μm is formed from the upper part of the left end of the chip mount 3b toward the right end of the chip mount 3a.

Therefore, the edge 7a of the protrusion 6a and the protrusion 6b
Is 10 μm relative to the edge 7b. Moreover, since the distance between each of the edges 7a, 7b and the opposing chip mount 3a, 3b is 100 μm or more, a pattern can be easily formed in the process.
Furthermore, since the alignment marks are formed at positions closest to the chip mounts 3a and 3b, that is, the alignment mark pairs 4 are part of the chip mounts 3a and 3b, the formation positions of the alignment mark pairs 4 are not limited.

Now, a case where the sensor IC chip 5 is disposed on each of the chip mounts 3a and 3b will be described. In FIG. 1, a sensor IC chip 5 is mounted on a chip mount 3a.
In order to arrange the sensor IC chip 5, the right side edge of the sensor IC chip 5 is made to coincide with the edge 7a of the projection 6a of the alignment mark pair 4, and the left side edge of the sensor IC chip 5 is aligned with the projection of the alignment mark pair 4. 6b and the chip mount 3a.
The sensor IC chip 5 is arranged thereon.

Next, in order to dispose the sensor IC chip 5 on the chip mount 3b, the right side edge of the sensor IC chip 5 is made to coincide with the edge 7a of the projection 6a of the alignment mark pair 4 as described above. The left side edge of the sensor IC chip 5 is matched with the edge 7b of the projection 6b in the alignment mark pair 4,
The sensor IC chip 5 is arranged on the chip mount 3b.

Accordingly, the sensor IC chips 5 are reliably arranged on each of the chip mounts 3a and 3b with a gap G of every 10 μm. As described above, the alignment mark of the present embodiment can be formed at the chip mounting position, and an index with a very small interval G can be formed without requiring advanced technology. Therefore, the sensor IC chip 5 can be accurately arranged with a predetermined gap G on each of the chip mounts 3a and 3b only by directly aligning the side edges of the sensor IC chip 5 with the edges 7a and 7b. In addition, the positioning accuracy and the efficiency of the positioning inspection can be improved.

The present invention is not limited to the above embodiment. For example, in the above embodiment, the chip mount and the alignment mark are formed by using the wiring pattern in the wiring step. It may be formed. In the above embodiment, the image sensor I
Although the alignment mark for positioning C has been described, the present invention may be applied to other alignment marks for positioning an IC chip.

[0017]

As described above in detail, according to the present invention, the process can be easily performed, and the mark can be formed at the position closest to the chip mounting position without any limitation on the mark forming position. And an excellent effect that the efficiency of the positioning test can be increased.

[Brief description of the drawings]

FIG. 1 is an explanatory view showing a state where alignment marks are formed on a plurality of chip mounts.

FIG. 2 is a partially enlarged view showing an alignment mark formed on a chip mount.

FIG. 3 is an explanatory diagram for explaining positioning of a conventional sensor IC chip.

FIG. 4 is an explanatory diagram for explaining positioning of a conventional sensor IC chip.

[Explanation of symbols]

 4 Alignment mark pair 5 Chip 7a Edge 7b Edge

Continued on the front page (72) Inventor Noboru Endo 2274 Hongo, Ebina-shi, Kanagawa Prefecture Fuji Xerox Corporation Ebina Office (72) Inventor Mitsuyuki Tamaya 2274 Hongo, Ebina-shi, Kanagawa Prefecture Fuji Xerox Corporation Ebina Office (72) Inventor Seiji Miyauchi 2274 Hongo, Ebina-shi, Kanagawa Pref. Fuji Xerox Co., Ltd. Ebina Works (56) References Jika 64-6447 (JP, U) (58) Field surveyed (Int.Cl) . ^6, DB name) G03F 7/20 - 9/02 H01L 23/12

Claims (1)

(57) [Claims] 1. A at least two chips to a alignment mark pair faced each other for arranging at predetermined intervals so as to displace the side showing the side of the chip edge which faces respectively so as not to face each other A method for forming an alignment mark.