JP2845844B2 - Microprocessor - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a microprocessor, and more particularly, to a microprocessor that performs data processing including signal processing operations.

[0002]

2. Description of the Related Art Conventionally, this kind of microprocessor has
As a general-purpose microprocessor, it is used for equipment control that requires signal processing operation together with general-purpose data processing. For example, FIG. 3 is a block diagram showing a configuration example of a general conventional general-purpose microprocessor.

Referring to FIG. 3, when a signal processing operation is performed using this general-purpose microprocessor, data RO is obtained.
A coefficient or delay data as an operation element is stored in M7 or the data RAM 3, and an operation is executed using the contents. The data transfer operation by this means is performed once by the data ROM from the register 11 or the instruction decoder 2 via the internal bus 15.
7 or the address information of the data RAM 3
The address is specified by transferring the data to the AM address register 16 or the ROM address register 17, and then the data ROM 7 or the data RA is transferred via the internal bus 15.
The process is performed by transferring the data from M3 to a multiplier or an arithmetic operation unit and performing an operation. For this reason, a general-purpose microprocessor needs to occupy the internal bus and transfer data address information when performing frequently updated data addresses, or to perform address calculations using an arithmetic unit. Since other instructions cannot be executed, the number of executions of operations such as multiplication per unit time is greatly reduced.

A typical example of digital signal processing is a biquad type IIR which is considered to be most frequently used.
A processing procedure when the filter program is executed by the general-purpose microprocessor will be described. FIG. 4 is a flowchart showing a procedure of an instruction when processing the second-order biquad IIR filter. Steps S1 to S14 shown in FIG.
Are instruction steps required for updating the address of data. According to this, it is understood that out of the 36 instructions constituting the program, 14 instructions must be executed in order to update these data addresses.

A dedicated processor, a so-called digital signal processor (hereinafter referred to as DSP), has been developed to solve the above-mentioned problem in general-purpose microprocessors by providing a circuit configuration suitable for digital signal processing. It is used as an essential component in signal processing systems. In general, a DSP includes a hardware multiplier, and a data bus and a program bus are separately provided to make it possible to simultaneously refer to data and a program by making each address space independent, and to update a data address by another. The operation efficiency is improved by providing a data memory pointer that can be executed in parallel with the operation. Further, the data memory pointer has various functions, and realizes an address operation function frequently used for signal processing such as a two-dimensional array operation and a butterfly operation by various methods.

In many DSPs, the address update processing occupies an operation time by providing an area for storing the instruction for the data memory pointer described above in parallel with another instruction in the same word and executing the instruction at the same time. Has been eliminated.
FIG. 5 is a flowchart of a program in a case where an equivalent to the above-described IIR filter is realized using a typical DSP. The instructions described in the same frame are all executed during the same instruction cycle, and the ten instructions constitute a program of the same filter including five multiply-accumulate operations. This indicates that there is a performance difference of three times or more even in the number of instructions alone.

However, the DSP obtains an operation speed and an operation efficiency important for signal processing by narrowing down an instruction system and a circuit configuration as an execution means for the purpose of signal processing. Is scarce. Specifically, since the I / O port control function, interrupt processing function, and logical operation function are significantly inferior to general microprocessors, it is incompatible with general microprocessors for controlling external circuits. Is generally regarded as common sense.

On the other hand, adopting a parallel execution means of a data memory pointer as seen in a DSP in a general-purpose microprocessor requires an instruction area for a data memory pointer, which is extremely rarely used except for signal processing operations, by using a conventional instruction memory. In addition, the efficiency of use of the instruction memory is deteriorated by adding the instruction memory in parallel, and in particular, the applicability of software with a conventional microprocessor is significantly impaired, which has been considered irrational and difficult.

In recent years, there has been a microprocessor equipped with a hardware multiplier and capable of executing a multiply-accumulate operation frequently used in digital signal processing in one instruction cycle. However, a parallel processing function of a data memory pointer provided in a DSP is known. Has not been installed for the above-mentioned reason. For this reason, in a real-time signal processing system, even if it is a relatively small-scale system, the processing capacity is often insufficient.

As described above, in the prior art, the diversion of software of existing general-purpose microprocessors,
In addition, it has been difficult to design a general-purpose microprocessor by incorporating a data address updating function using a data memory pointer similar to that of a DSP without deteriorating the versatility of the general-purpose microprocessor. Because of this,
When constructing a real-time signal processing system, it is almost always necessary to use a DSP and a microprocessor or a DSP and a host computer together, even for a relatively small-scale system.

[0011]

As described above, when a conventional general-purpose microprocessor attempts to perform digital signal processing represented by a digital filter,
Due to frequently executed data address updates, even if
Even with a general-purpose microprocessor provided with a hardware multiplier, the number of arithmetic operations per unit time is significantly reduced, and there has been a problem that arithmetic operations required for signal processing cannot be processed within a fixed time.

On the other hand, if a DSP is used to share the functions of a general microprocessor, sufficient functions cannot be realized due to the lack of general versatility. There is a problem that even the same small-scale system needs to be used together with a microprocessor.

Further, even if a data address updating function by means similar to that of a DSP is employed in a general-purpose microprocessor, the use efficiency of an instruction memory is deteriorated and compatibility of software with a conventional general-purpose microcomputer is significantly impaired. There was a problem above.

Accordingly, it is an object of the present invention to update data addresses mainly at the time of digital signal processing by adding relatively small circuits and expanding instructions without compromising the upward compatibility of software with respect to a conventional general-purpose microprocessor. Another object of the present invention is to provide a microprocessor in which the time required for the microprocessor is greatly reduced, and to further expand the application range of the microprocessor to digital signal processing systems.

[0015]

Accordingly, the present invention provides an instruction decoder for decoding an instruction read from an instruction memory for storing a processing program, and an instruction for multiplying data previously transferred from a data memory to a register. And a multiplier that calculates or updates the address of the data and outputs it to the data memory, and only a pointer instruction that controls the address calculation or address update of the data memory pointer. A pointer instruction memory separately stored in advance.

Further, when the instruction decoder is an arithmetic routine including the data transfer instruction between the data memory and the register and the multiplication instruction, the instruction decoder indicates a data transfer instruction to the data memory. A transfer instruction state signal and a pointer instruction execution permission signal indicating permission of execution of the pointer instruction in the operation routine are decoded and output, and in synchronization with a logical product output of the transfer instruction state signal and the pointer instruction execution permission signal, The pointer instruction is read from the pointer instruction memory to the data memory pointer and is executed concurrently with the data transfer instruction.

Further, the pointer instruction memory may have an RA
M, and stores the pointer instruction from the instruction memory before the arithmetic routine.

Alternatively, the pointer instruction memory is RO
M, and the pointer instruction corresponding to the arithmetic routine is written in advance.

[0019]

Next, the present invention will be described with reference to the drawings. FIG. 1 is a block diagram showing an embodiment of the microprocessor of the present invention. Referring to FIG.
The microprocessor of the present embodiment includes an instruction memory 1, an instruction decoder 2, a data RAM 3, a data ROM 7, a multiplier 8, and an operation unit 12 including an arithmetic operation unit 10, as in the conventional microprocessor of FIG. Furthermore, DS
As data memory pointer similar to P, data RAM
3, RAM pointer 4 for data ROM 7 and RO
M pointer 6 and a new RAM pointer 4, R
A pointer instruction memory 5 for the OM pointer 6 is provided. Of these blocks, the same blocks as those in FIG. 3 will not be described repeatedly.

The pointer instruction execution permission signal 13 is a binary signal output from the instruction decoder 2, and changes the state of the signal during the period from execution of the pointer instruction execution start instruction to execution of the pointer instruction execution stop instruction. It is set to “1”, and the state is set to “0” during other periods. The transfer instruction state signal 14 is also a signal output from the instruction decoder 2, and is used during a period when the instruction decoder 2 executes a memory transfer instruction.
The state of the output is set to “1”, and the state is set to “0” during other periods. When the logical product of the pointer command execution enable signal 13 and the transfer command state signal 14 as inputs is "1", the RAM pointer 4 and the ROM pointer 6 execute the pointer command one word at a time, and during the other periods, the pointer command is executed. By stopping the execution of
The pointer instruction is executed at an appropriate timing.

Next, the functions of the RAM pointer 4 and the ROM pointer 6 will be described with reference to FIG. RAM pointer 4 has a word length of 65536 by having a word length of 16 bits.
It has a word address space, and in practice, it is possible to arbitrarily set an address space having an upper limit of the mounted data RAM capacity. In the upper 12 bits of the 16 bits, 0 clear, immediate value designation, increment and decrement from the current value, and carry addition or non-carry addition with an arbitrary 4-bit image for the 12 bits of the current value are performed. And it is possible. Furthermore, in the remaining lower 4 bits, the value can be changed by a bitwise XOR operation between the current value and an arbitrary 4-bit image.

The ROM pointer 6 has an address space of 65,536 words by having a word length of 16 bits. In practice, a space having an upper limit of the mounted data ROM capacity can be arbitrarily set. The address value can be updated by using the immediate value designation and increment and decrement from the current value. When the transfer instruction and the pointer instruction related to the data RAM 3 and the data ROM 7 are executed in the same cycle, the execution result of the pointer instruction becomes valid after the execution of the transfer.

The pointer instruction memory 5 can be constituted by either a RAM or a ROM. When the pointer instruction memory 5 is formed of a RAM, the pointer instruction stored in the instruction memory 1 is transferred to the pointer instruction memory 5 via the internal bus before executing the pointer instruction.
By transferring the required amount to the pointer instruction, the pointer instruction can be executed. When the pointer instruction memory 5 is configured by a ROM,
The procedure for transferring the pointer instruction from the instruction memory 1 to the pointer instruction memory 5 can be omitted, but it is necessary to write all the pointer instructions to be used in advance.

Next, the operation of this embodiment will be described with reference to the drawings. FIG. 2 is a flow chart showing a procedure for executing calculations and data transfer in a calculation routine of an IIR filter program as a typical example of digital signal processing. In the figure, the operation instruction and the pointer instruction executed in the same execution cycle are described in the same frame. As shown in the figure, in the second-order biquad type IIR filter, after specifying the initial value of the RAM address as an immediate value, four exclusive OR operations for the lower four bits and one increment for the upper four bits are performed. Then, the RAM address is changed. Referring to FIG. 1, with respect to the data ROM 7 in which the coefficients are stored, the initial value of the ROM address is immediately specified, and then the ROM address is updated by decrementing five times.

In both the data RAM 3 and the data ROM 7, the procedure for updating the address following the designation of an immediate value corresponds to one invocation of a secondary biquad type IIR filter of a subroutine operation. Further, by repeatedly executing the subroutine, the data RAM 3 and the data ROM
Can be updated in synchronization with the transfer operation.

[0026]

As described above, the microprocessor according to the present invention is provided with a general-purpose microprocessor in which a parallel operation function for executing a pointer instruction for operating a data address in parallel with other operations is added to a conventional microprocessor. DS
By realizing the address updating function equivalent to P, the time required for updating the data address performed in the digital signal processing operation such as the digital filter program can be greatly reduced. As a result, by improving the actual operation efficiency of the operation processing, there is an effect that the digital signal processing can be applied to more advanced or a wide range of digital signal processing without using the DSP together.

At the same time, the microprocessor of the present invention
For many conventional general-purpose microprocessors, it can be realized by changing and adding relatively small-scale circuits and instructions, and can be realized without losing upward compatibility in software. This has the effect that software can be easily diverted.

[Brief description of the drawings]

FIG. 1 is a block diagram showing an embodiment of a microprocessor of the present invention.

FIG. 2 is a flowchart showing an execution procedure of a calculation routine of a biquad type IIR filter by the microprocessor of FIG. 1;

FIG. 3 is a block diagram illustrating a configuration example of a conventional microprocessor.

4 is a flowchart showing an execution procedure of a calculation routine of a biquad type IIR filter by the microprocessor of FIG. 3;

FIG. 5 shows a biquad type I using a conventional representative DSP.
9 is a flowchart showing an execution procedure of an operation routine of an IR filter.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 Instruction memory 2 Instruction decoder 3 Data RAM 4 RAM pointer 5 Pointer instruction memory 6 ROM pointer 7 Data ROM 8 Multiplier 9 Multiplier output register 10 Arithmetic operation unit 11 Register 12 Operation unit 13 Pointer instruction execution permission signal 14 Transfer instruction state signal 15 Internal bus 16 RAM address register 17 ROM address register ram Data RAM dp Data RAM address register dph Data RAM address register, but upper 12 bits dpl Data RAM address register, but lower 4 bits rom data rom rp data rom address register r0 0 General register r1 First general register r2 Second general register r3 Third general register r4 Fourth general register r5 Fifth general register r6 Sixth general Register m multiplication result storage register → transfer or assignment operation * multiply operation + adding operations - instruction steps for the purpose of subtraction operation xor XOR operation S1~S14 address update

──────────────────────────────────────────────────続 き Continued on the front page (58) Field surveyed (Int.Cl. ⁶ , DB name) G06F 9/30-9/355 G06F 9/40-9/42 390 G06F 9/38-9/38 390 G06F 15/78 510

Claims (4)

(57) [Claims] 1. A micro-computer comprising: an instruction decoder for decoding an instruction read from an instruction memory for storing a processing program; and a multiplier for multiplying data previously transferred from a data memory to a register by a multiplication instruction. In the processor, a data memory pointer for calculating or updating the address of the data and outputting the data to the data memory, and a pointer instruction memory for separately storing only a pointer instruction for controlling the address calculation or the address update of the data memory pointer, A microprocessor, comprising: 2. The instruction decoder, when the processing program is an arithmetic routine including a data transfer instruction between the data memory and the register and the multiplication instruction, indicates a data transfer instruction to the data memory. A transfer instruction state signal and a pointer instruction execution permission signal indicating permission of execution of the pointer instruction in the operation routine are decoded and output, and in synchronization with a logical product output of the transfer instruction state signal and the pointer instruction execution permission signal, 2. The microprocessor according to claim 1, wherein said pointer instruction is read from said pointer instruction memory to said data memory pointer, and is simultaneously executed in parallel with said data transfer instruction. 3. The microprocessor according to claim 1, wherein said pointer instruction memory comprises a RAM, and stores said pointer instruction from said instruction memory before said operation routine. 4. The microprocessor according to claim 1, wherein said pointer instruction memory comprises a ROM, and said pointer instruction corresponding to said arithmetic routine is written in advance.