JP2848488B2 - Semiconductor device and manufacturing method thereof - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device and a method of manufacturing the same, and more particularly, to a structure of a semiconductor device having an analog circuit and used in a microwave band and a method of manufacturing the same.

[0002]

2. Description of the Related Art Conventionally, as a substrate of a semiconductor chip on which a microwave-band analog circuit is mounted, GaAs is used because of its advantages that a semi-insulating substrate can be obtained and a compound semiconductor device having excellent high-frequency characteristics can be easily manufactured. And other compound semiconductor substrates have been used. However, the compound semiconductor substrate has a disadvantage that the thermal conductivity is smaller than that of the Si substrate [The thermal conductivity is 150 (W / mK) for Si, for example, 54 (W / mK) for GaAs]. In order to compensate for this, chip thickness has been reduced. Also, 20G
At ultra-high frequencies of over Hz, it is necessary to make the distance from the grounding terminal in the circuit to the ground plane shorter in order to prevent deterioration of the circuit performance.A hole called a via hole is formed in the board, and the board surface and the ground plane Connection with a certain substrate back surface is being performed. Since the via hole is difficult to be formed when the substrate is thick, it is necessary to reduce the thickness to about 100 μm or less. Further, when the frequency becomes higher than about 40 GHz, the performance is deteriorated even at a length up to the ground plane having the thickness of the substrate, and it is required to further reduce the thickness.

On the other hand, the compound semiconductor substrate has a disadvantage that the mechanical strength is lower than that of Si or the like. If the compound semiconductor substrate is exposed at the edge of the chip, the chip may be chipped or chipped when handling the tweezers. Cracks are likely to occur. As means for avoiding these problems, means for protecting the chip edge with a metal film which can be formed relatively easily has been used conventionally. FIG. 10A is a plan view of a conventional semiconductor device in which this measure is taken, and FIG. 10B is a cross-sectional view taken along line HH ′. As shown in FIGS. 10A and 10B, on the surface of a semi-insulating GaAs substrate 1, an element on which a MESFET, wiring, and the like are formed and a wiring forming section 2 are provided. A signal input unit 3 and a signal output unit 4 for connecting between terminals with a bonding wire.
Are formed. An edge surface metal film 5 is formed all around the periphery of the substrate surface, and the back and side surfaces of the substrate are covered with a back metal film 7. The edge portion front surface metal film 5 and the back surface metal film 7 are usually made of gold (A
u) It is formed by a multilayer metal film including a layer.

[0004] The semiconductor device thus formed is shown in FIG.
As shown in FIG. 1, it is mounted in a package. That is, the semiconductor device is die-bonded to the island 11 formed on the package 10 via the brazing material 12, and the signal input terminal 13 and the signal output terminal 14 on the package side and the signal input unit 3 and the signal output unit 4 on the chip side are connected. Are connected by bonding wires 15.

[0005]

In the above-described conventional semiconductor device, since the chip side surface is covered with Au which is easily wetted by the brazing material, when the chip is die-bonded to the island on the package, as shown in FIG. The brazing material rises 15 to 20 μm higher than the chip surface. Therefore, in order to avoid contact with the brazing material, it is necessary to pass the bonding wire high, and the bonding wire length becomes long. As a result, the reactance component in the transmission line increases, and the high-frequency characteristics of the circuit deteriorate. Therefore, the problem to be solved by the present invention is to prevent the mounting brazing material from rising high in a region where the bonding wire passes, so that the bonding wire can pass through the shortest distance.

[0006]

According to the present invention, in order to solve the above-described problems, the back surface, the side surface, and the surface in the vicinity of the edge of the semiconductor chip, except for a portion below the bonding wire, are provided. A semiconductor device characterized by being covered with a metal film is provided.

[0007]

DESCRIPTION OF THE PREFERRED EMBODIMENTS In a semiconductor device according to the present invention, the back surface, side surfaces and surfaces near edges of a semiconductor chip are covered with metal films (5, 7) except for portions under signal bonding wires. . Then, the chip side surface of the portion to be the signal bonding wires under, for example the surface of a semi-insulating semiconductor substrate is exposed. The surface of the semi-insulating semiconductor substrate (1) is exposed at the surface portion near the edge below the signal bonding wire, the substrate surface is covered with an insulating film (8), or the substrate surface is formed of a metal layer. (9) and the insulating film (8).

Further, a method of manufacturing a semiconductor device according to the present invention includes (1) a step of forming a metal layer and a step of forming an insulating film, and forming an element and a wiring on a semi-insulating semiconductor substrate; 2) A step of covering a region to be a chip separation region and a region near a chip edge except for a portion below signal bonding wires with a surface metal film [FIGS.
(A)], (3) a step of processing the substrate from the back surface of the substrate to a desired thickness, and (4) etching of the semiconductor substrate in the region to be the chip separation region from the back surface of the substrate, Step of exposing the back surface of the front surface metal film [FIG.
(B), FIG. 3 (b)], and (5) a step of covering the side surface and the back surface of the substrate with the back surface metal film except for the side surface portion of the region below the signal bonding wire [FIG.
(C), FIG. 3 (c)] and (6) a step of separating the individual chips by etching away the surface metal film on the exposed substrate surface from the back surface of the substrate. .

[Operation] In the semiconductor device of the present invention,
The edge surface surface metal film and the back surface metal film (side surfaces) of the bonding wire passage area are removed. Therefore, when the chip is mounted on the mounting substrate, the side surface of the chip is not wetted by the mounting brazing material in a region below the bonding wires for signal input / output, and therefore, the brazing material swells on the chip surface in this region. Disappears. Therefore, it is possible to pass the bonding wire low, it is possible to minimize the bonding wire, and it is possible to prevent deterioration of high-frequency characteristics. According to the present invention, a portion of the chip edge portion that is not covered by the edge portion surface metal film and the back surface metal film occurs, but the portion is not wide and the entire peripheral portion is covered by the metal film. The mechanical strength of the uncovered portion is maintained, and the possibility that the frequency of occurrence of cracks and chips is increased by the present invention is low.

[0010]

Next, embodiments of the present invention will be described with reference to the drawings. [First Embodiment] FIG. 1 (a) is a plan view showing a first embodiment of the present invention, and FIGS.
AA 'line, BB' line, and C- line in FIG.
It is sectional drawing in the C 'line. In FIG. 1, the same parts as those of the conventional example shown in FIG. 10 are denoted by the same reference numerals, and the duplicate description will be omitted. The difference from the conventional example of the first embodiment is that the edge surface surface metal film 5 and the back surface metal film 7 (side surface portion) of the bonding wire passage area 6 are different.
Is removed, and the surface of the semi-insulating GaAs substrate 1 is exposed in that portion.

FIG. 2 is a plan view showing a manufacturing method according to a first embodiment of the present invention in the order of steps, and FIG. 3 is a sectional view taken along line DD 'of FIG.
It is sectional drawing of a process order in a line and EE 'line. Semi-insulating G
After a step of forming an element and a wiring forming portion 2 on the aAs substrate 1, a 1 μm-thick Ti / 2 μm thick film is formed near a chip edge portion and a chip separation region between chips.
An edge surface metal film 5 made of Au is formed. At this time, the portion in the range of 50 to 500 μm serving as the bonding wire passage region 6 of the signal wire is narrower than the other portion so that the edge portion surface metal film 5 can be completely etched away from the back surface in a later step. I have. After that, the semi-insulating GaAs substrate 1 is etched from the back surface to reduce the substrate thickness to about 20 to 100 μm [FIG.
(A)].

Then, if necessary, after forming a via hole for connecting the ground electrode on the front surface of the substrate and the back metal film (7), the semi-insulating GaAs substrate 1 is left so as to leave only a chip portion from the back surface. The chip separation region is selectively removed by etching so that the back surface of the previously formed edge portion surface metal film 5 is exposed (FIGS. 2B and 3B).

Thereafter, a backside metal film 7 made of Ti / Au is formed so as to cover the backside and side surfaces of the semi-insulating GaAs substrate 1 which has become only the chip portion by the etching from the backside.
To form At this time, the back surface metal film 7 is not formed on the back surface and the side surface corresponding to the narrow portion of the edge surface metal film [FIGS. 2C and 3C]. Then, the edge surface metal film 5 exposed on the back surface side is removed by etching to manufacture a semiconductor chip. Since the narrow portion of the edge surface metal film 5 is entirely removed by etching, the semi-insulating GaAs substrate 1 extends over the surface and side surfaces of the bonding wire passing region 6.
Is exposed.

[Second Embodiment] FIG. 4A is a plan view showing a second embodiment of the present invention, and FIG.
It is sectional drawing in the -F 'line. In the first embodiment,
In the bonding wire passage area 6, the edge portion surface metal film is removed to expose the surface of the semi-insulating GaAs substrate 1, but in this embodiment, the insulating film 8 covers the substrate surface (bonding passage). The semi-insulating GaAs substrate 1 is exposed on the chip side surface in the region 6).

The semiconductor device of this embodiment is manufactured as follows. In the process of forming the element and wiring forming portion 2 on the semi-insulating GaAs substrate 1, the insulating film 8 forms a bonding wire passing region at an edge portion when a protective film is formed of, for example, a silicon oxide film or a silicon nitride film. 6 are formed simultaneously. That is, the insulating film 8 is formed in a pattern that fills the concave portion of the narrowed portion of the pattern of the edge portion surface metal film 5 shown in FIG. Subsequent steps are the same as those in the manufacturing method of the first embodiment shown in FIGS. 2 and 3 to manufacture the semiconductor device of the present embodiment.

This manufacturing method can be modified as follows. The insulating film 8 is formed by extending the chip separation region between the two chips, and when the chip is finally separated into chips, the insulating film 8 exposed on the back surface side is etched prior to etching the edge surface metal film. The part is removed by etching. In the first embodiment of the present invention, when the semi-insulating GaAs substrate 1 is etched from the back surface to expose the edge surface metal film 5, the GaAs substrate other than the edge surface metal film 5 is etched due to manufacturing variations. Although there is a possibility that the front and back surfaces may penetrate, the insulating film 8 may be exposed in the second embodiment, but it is possible to prevent the front and back surfaces from penetrating. There is an advantage that it becomes easy.

[Third Embodiment] FIG. 5A is a plan view showing a third embodiment of the present invention, and FIG.
It is sectional drawing in the -G 'line. The present embodiment is different from the second embodiment shown in FIG. 4 in that a wiring metal layer 9 is provided on a semi-insulating GaAs substrate on the surface of the bonding wire passing region 6 and an insulating film 8 is formed thereon. This is the point that was formed. The wiring metal layer 9 is formed by, for example, WSi, Ti / A in a process of forming an element and a wiring on the semi-insulating GaAs substrate 1.
The electrode / wiring is formed simultaneously with the formation of a thin metal layer of about 1 μm or less made of u, Al / Ti / Au or the like. An insulating film 8 is formed on the wiring metal layer 9 in the same process as in the second embodiment. By adopting such a structure, the same advantages as those of the second embodiment can be obtained. In addition, since the edge surface metal film 5 is connected by the wiring metal layer 9 in the bonding wire passage region 6, the first and second structures can be obtained. As compared with the embodiment, there is an advantage that peeling from the edge of the metal film 5 on the edge portion surface of the bonding wire passage region 6 is less likely to occur.

The manufacturing method according to the third embodiment can be performed in the same manner as in the second embodiment. That is, a method of forming the wiring metal layer 9 and the insulating film 8 only on the surface of the chip edge portion, and these can be formed by extending the chip separation region. In the latter case, when separating into chips, the wiring metal layer 9 and the insulating film 8 are etched away from the back surface before the edge surface metal film 5 is etched away.

[Fourth Embodiment] FIG. 6 is a plan view and a cross-sectional view in one process step for explaining a manufacturing method according to a fourth embodiment of the present invention. FIG. FIG. 6 is a cross-sectional view in the order of steps in a step that follows the step of FIG. After an analog circuit is formed in the element and the wiring forming section 2 of each chip of the semi-insulating GaAs substrate 1, the scribe region is etched to form a tapered recess 16. The width of the bottom surface of the concave portion 16 is made smaller than the width of the scribe region to be etched, and the angle of the taper is made about 45 degrees to secure a process margin. Further, the depth of the concave portion is about 30% or more of the final substrate thickness and 20 to 60 μm. Next, an edge portion surface metal film 5 made of Ti / Au having a thickness of 1 to 2 μm is formed so as to cover the concave portion 16. However, the edge portion surface metal film 5 in the bonding wire passage region 6 is formed to be narrower than the other portions, and has such a width as to extend below the tapered portion of the concave portion 2. FIG. 6 is a diagram showing this state.
6A is a plan view, and FIGS. 6B and 6C are cross-sectional views taken along line JJ ′ and line KK ′ in FIG. 6A, respectively.

FIG. 7 is a sectional view taken along the line JJ 'and the line KK' in FIG. 6A for explaining the steps after the state shown in FIG.
It is sectional drawing of a process order in a line. As shown in FIG. 7A, after the back surface of the substrate is polished and etched until a desired thickness is obtained, the semi-insulating GaAs substrate 1 in a scribe region is formed.
Is etched until the edge surface metal film 5 on the bottom surface of the concave portion 16 is exposed. The etching is stopped before the end of the edge surface metal film 5 in the middle of the taper is exposed. This makes it possible to prevent the front and back surfaces of the substrate from penetrating. Then, T is applied to the back surface of the substrate and the side surface of the scribe portion of the semi-insulating GaAs substrate 1 etched from the back surface.
A backside metal film 7 made of i / Au is attached [FIG.
(B)]. At this time, the back surface metal film 7 is prevented from adhering to the side surface of the semi-insulating GaAs substrate 1 which corresponds to the bonding wire passage region. Thereafter, only the edge surface metal film 5 of the scribe portion exposed from the back surface is removed by etching to separate into chips [FIG. 7 (c)]. In the above description, the bottom surface of the concave portion 16 is narrower than the width of the scribe region to be etched. However, the width may be approximately the same or wider than the width of the scribe region.

FIG. 8 is a sectional view schematically showing a semiconductor chip according to a fourth embodiment of the present invention mounted on a package. This cross section is the same as the cross section taken along the line JJ ′ in FIG. The semiconductor chip is mounted on the island 11 on the package 10 by the brazing material 12, and the input / output pads on the chip are connected to the signal input terminals 13 and the signal output terminals 14 on the package 10 by bonding wires 15. In the bonding wire passage area, since the back metal 7 of the semiconductor chip does not exist on the side of the chip, the brazing material 12 does not crawl on the side of the chip. Even though the brazing material may flow through the back surface metal film, the amount thereof is small and the position of the front surface metal film 5 is below the substrate surface, so that the brazing material does not rise above the substrate surface, and the bonding wire 15 It is not necessary to increase the length, and the length can be minimized to connect the wires.

In the above-described first to third embodiments, the width of the surface metal film 5 in the bonding wire passage area is made the same as the width of the scribe area. When the substrate is etched in the scribe region, the front and back surfaces of the substrate may penetrate during etching of the scribe region, or etching residue may be left when etching the surface metal film 5 from the back surface of the substrate through the scribe region. Occurs. When the above occurs, the element surface is contaminated by an etchant or the like, and the element characteristics are degraded. When the above occurs, the brazing material swells through the surface metal film 5 remaining after the etching, and the possibility of contact with the bonding wire is raised. Causes an adverse effect such as an increase in However, in the fourth embodiment, the surface metal film in the region where the bonding wire passes is formed so as to cover the tapered portion, and the etching of the GaAs substrate is terminated in the middle of the tapered portion. In this case, the substrate can be stably manufactured without penetrating between the front and back surfaces of the substrate. Further, the edge portion surface metal film 5 slightly remains under the bonding wire, but is lower than the substrate surface, so that the possibility that the metal film or a material flowing into the metal film comes into contact with the bonding wire is low.

[Fifth Embodiment] FIGS. 9A and 9B are views for explaining a manufacturing method according to a fifth embodiment of the present invention at one process step. FIG. 9A is a plan view and FIG. 9 (b), FIG. 9 (c)
10A and 10B are cross-sectional views taken along line MM ′ and line NN ′ in FIG. 9A, respectively. The difference between the fifth embodiment and the fourth embodiment is that, in the present embodiment, the concave portion 16 formed in the scribe portion from the surface of the semi-insulating GaAs substrate 1 is used as a signal input / output bonding wire. This is the point where only the chip side that intersects is set. The manufacturing process after the formation of the recess 16 is the same as that of the fourth embodiment. By doing so, there is an advantage that the length of the side surface can be increased except for the chip side below the bonding wire, so that chip handling becomes easy.

[0024]

As described above, in the semiconductor device of the present invention, the surface, the back surface, and the side surface of the edge portion are covered with the metal film except for the surface and the side surface of the chip which becomes the bonding wire passage area. According to the present invention, it is possible to prevent the chip edge portion from being cracked or chipped, and to prevent the mounting brazing material from rising beyond the chip surface under the bonding wire. Therefore, according to the present invention, it is possible to provide a bonding wire in the shortest time while preventing breakage of a chip, and to prevent deterioration of high frequency characteristics.

Further, according to the embodiment in which the concave portion is formed in the scribed portion of the substrate, the front and back surfaces of the wafer do not penetrate during the process, so that unwanted contamination by an etchant or the like can be prevented. It is possible to improve the yield and manufacture stably. In addition, since the edge portion surface metal film below the bonding wire is formed at a portion lower than the substrate surface, even if a brazing material flows into the surface metal film under the bonding wire at the time of chip mounting, the bulge can be suppressed low, The contact between the brazing material and the bonding wire can be avoided.

[Brief description of the drawings]

FIG. 1 is a plan view and a cross-sectional view showing a first embodiment of the present invention.

FIG. 2 is a plan view showing a manufacturing method according to the first embodiment of the present invention in order of steps.

FIG. 3 is a sectional view illustrating a manufacturing method according to the first embodiment of the present invention in the order of steps.

FIG. 4 is a plan view and a sectional view showing a second embodiment of the present invention.

FIG. 5 is a plan view and a sectional view showing a third embodiment of the present invention.

FIG. 6 is a plan view and a cross-sectional view for explaining a manufacturing method according to a fourth embodiment of the present invention.

FIG. 7 is a step-by-step sectional view in a step following FIG. 6 for explaining the manufacturing method of the fourth embodiment of the present invention.

FIG. 8 is a sectional view showing a mounting state of a fourth embodiment of the present invention.

FIG. 9 is a plan view and a cross-sectional view for explaining a manufacturing method according to a fifth embodiment of the present invention.

FIG. 10 is a plan view and a cross-sectional view of a conventional example.

FIG. 11 is a sectional view showing a mounting state of a conventional example.

DESCRIPTION OF SYMBOLS 1 Semi-insulating GaAs substrate 2 Element and wiring forming part 3 Signal input part 4 Signal output part 5 Edge part surface metal film 6 Bonding wire passage area 7 Backside metal film 8 Insulating film 9 Wiring metal layer 10 Package 11 Island 12 brazing material 13 signal input terminal 14 signal output terminal 15 bonding wire 16 recess

──────────────────────────────────────────────────続 き Continued on the front page (58) Field surveyed (Int.Cl. ⁶ , DB name) H01L 21/60 301 H01L 21/60 321 H01L 21/88 H01L 21/68

Claims (11)

(57) [Claims] 1. A back surface of the semiconductor chip, the front surface side and the edge vicinity, except where <br/> that Do and signal bonding wires under, characterized in that it is covered by a gold Shokumaku semiconductor apparatus. 2. The semiconductor device according to claim 1, wherein the surface of the substrate is exposed at a surface portion near a side surface and an edge of the semiconductor chip in a region below the signal bonding wire. 3. The substrate surface is exposed on a side surface of the semiconductor chip in a region below the signal bonding wire, and an insulating film covers the substrate surface on a surface portion near an edge below the signal bonding wire. The semiconductor device according to claim 1, wherein: 4. A substrate surface is exposed on a side surface of the semiconductor chip in a region below a signal bonding wire, and a metal layer covers the substrate surface on a surface portion near an edge below the signal bonding wire. 2. The semiconductor device according to claim 1, wherein a surface of the metal layer is covered with an insulating film at a center portion and an end portion with the metal film. 5. The semiconductor device according to claim 1, wherein at least a surface-side edge of a side of the semiconductor chip that intersects with the signal bonding wire is chamfered. 6. A step of forming an element and a wiring on a semi-insulating semiconductor substrate, including: (1) a step of forming a metal layer and a step of forming an insulating film; and (2) a region to be a chip separation region; Covering the area near the chip edge with the surface metal film except for the portion under the signal bonding wire; (3) processing the substrate from the back surface to a desired thickness; and (4) back surface of the substrate. Etching the semiconductor substrate in the region to be the chip separation region to expose the back surface of the front surface metal film on the substrate surface; and (5) the side surface of the substrate except for the side portion under the signal bonding wire. And a step of covering the back surface of the substrate with a back surface metal film; and (6) a step of separating the individual chip by etching away the front surface metal film on the exposed substrate surface from the substrate back surface. The method of manufacturing a semiconductor device characterized by having a. 7. The method according to claim 6, wherein in the step of forming the insulating film in the step (1), a region below a signal bonding wire near a chip edge is covered with an insulating film. A method for manufacturing a semiconductor device. 8. A chip sandwiched between a region under a signal bonding wire near a chip edge and a region under two signal bonding wires in a process of forming the insulating film in the first step. A step of covering the portion on the isolation region with an insulating film and etching the insulating film exposed from the back surface of the substrate after the step (5) and prior to the step (6) is added. 7. The method for manufacturing a semiconductor device according to claim 6, wherein 9. In the step (1) of forming the metal layer and the step of forming the insulating film, a region below a signal bonding wire near a chip edge is insulated from the metal layer by a narrower insulating layer. 7. The method according to claim 6, wherein a portion of the metal layer protruding from the insulating film is coated with a surface metal film formed in the step (2).
The manufacturing method of the semiconductor device described in the above. 10. The method according to claim 1, wherein in the forming the metal layer and the insulating film in the first step, a region below a signal bonding wire near a chip edge and a region below two signal bonding wires. And a portion on the chip isolation region sandwiched between the regions is covered with a metal layer and an insulating film narrower than the metal layer, and a portion of the metal layer protruding from the insulating film is formed in the step (2). A step of covering the surface with the formed surface metal film and etching the metal layer and the insulating film exposed from the back surface of the substrate after the step (5) and prior to the step (6). 7. The method for manufacturing a semiconductor device according to claim 6, wherein 11. A step of forming an element and a wiring on a semi-insulating semiconductor substrate, including: (1) a step of forming a metal layer and a step of forming an insulating film; and (2) intersecting at least a future signal bonding wire. Forming a concave portion wider than a chip isolation region having a tapered portion and a bottom portion on the surface of the semi-insulating semiconductor substrate which is to be a chip isolation region on a side to be separated; and (3) chip separation on the surface of the semi-insulating semiconductor substrate. Forming a surface metal film which covers the region to be the region and the vicinity of the chip edge, and which is narrower than the other portion in the portion below the signal bonding wire and slightly wider in that portion than the chip isolation region; A) processing the substrate from the back surface of the substrate to a desired thickness; and (5) etching the semiconductor substrate in a region to be the chip separation region from the back surface of the substrate, A step of exposing the back surface of the surface metal film; (6) a step of covering the side surface and the back surface of the substrate with a back surface metal film except for a side surface portion of a region under the signal bonding wire; Separating the individual chips by etching away the surface metal film on the exposed substrate surface.