JP2849286B2 - Method for manufacturing semiconductor device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a multi-layer wiring structure.
The present invention relates to a method for manufacturing a semiconductor device.

[0002]

2. Description of the Related Art FIG. 5 is a sectional view showing a step of forming a multi-layer wiring structure in a conventional semiconductor device, wherein 1 is a silicon semiconductor substrate, 2 is a silicon oxide formed on a semiconductor substrate 1. 3, a lower wiring, 4 a plasma oxide film (silicon oxide film), 5 a positive resist film,
5a is an opening formed in the positive resist film 5, 6 is a through hole, and 7 is an upper wiring connected to the lower wiring 3 through the through hole 6 .

[0003] A forming process will be described below with reference to FIG. First, as shown in FIG. 5A, a lower wiring 3 is selectively formed in a predetermined region on the upper surface of a silicon oxide film 2 covering the surface of a silicon semiconductor substrate 1. Next, FIG.
As shown in FIG. 1, a plasma oxide film (silicon oxide film) 4 is formed over the entire surface of the silicon semiconductor substrate 1 so as to cover the lower wiring 3. Next, as shown in FIG. 5 (c), a positive resist film 5 is applied on the plasma oxide film (silicon oxide film) 4 and the photolithographic technique shown in FIG.
As shown in (d), an opening 5a is formed in a predetermined region of the positive resist film 5. Next, using the positive resist film 5 in which the openings 5a are formed as a mask, the plasma oxide film (silicon oxide film) 4 is selectively etched, and as shown in FIG. A through hole 6 is formed in a predetermined region of the silicon oxide film 4. Next, after the positive resist film 5 is completely removed, as shown in FIG. 5F, the upper surface of the plasma oxide film (silicon oxide film) 4 and the surface of the lower wiring 3 exposed from the through hole 6 are formed. The wiring metal is deposited to form the upper wiring 7.

As shown in the above steps, in a semiconductor device, usually, in accordance with integration and miniaturization, an upper layer and a lower layer wiring (upper layer wiring 7) are interposed via an interlayer insulating film (plasma oxide film 4). The lower wiring 3 is connected through a through hole 6 formed in the interlayer insulating film to form a multilayer wiring structure.

[0005]

The multi-layer wiring structure of the conventional semiconductor device is formed by the above-described steps, and the through-hole 6 formed in the interlayer insulating film (plasma oxide film 4) on the lower wiring 3 and the through hole 6 are formed. In the peripheral part, as shown in the figure, the thickness of the interlayer insulating film (plasma oxide film 4) appears as a step as it is, so that the interlayer insulating film (plasma oxide film 4)
The upper layer wiring 7 formed along the inner peripheral surface of the upper surface of the through hole 6 and the through hole 6 is disconnected due to this step, and even if not disconnected, the coverage is reduced, and the reliability of the obtained semiconductor device is reduced. There was a problem of doing.

SUMMARY OF THE INVENTION The present invention has been made to solve the above-mentioned problems, and has been made in consideration of the above-described problems, and is directed to a lower wiring surface exposed from a contact hole of an interlayer insulating film and an upper wiring formed on the surface of the interlayer insulating film around the lower wiring. Of a semiconductor device having a multi-layer wiring structure that is well coated without disconnection .
It is intended to provide a fabrication method.

[0007]

A semiconductor according to the present invention.
The method of manufacturing the device is such that a lower wiring and an upper wiring are formed on a semiconductor substrate.
Line is connected through through hole in interlayer insulating film
In a method of manufacturing a semiconductor device having a multilayer wiring film formed thereon,
Forming a first wiring layer in a predetermined region on the semiconductor substrate
And the semiconductor layer so as to cover the first wiring layer.
A first shell containing no carbon component is applied to the entire surface of the body substrate.
A step of forming a silicon oxide film;
The repeating unit is represented by the following general formula (1)
A resin solution containing the silicone ladder polymer
Spin coating, baking the obtained coating film, carbon component
Forming a second silicon oxide film containing
Position of the second silicon oxide film above the first wiring layer
Forming an opening in a predetermined portion to be formed;
Etching rate by etching gas to be etched
Is, compared to the first silicon oxide film, the second silicon oxide film.
By making use of the fact that the oxide film is smaller,
In this state, the first and second seals are formed by the etching gas.
Etching the silicon oxide film to form the second silicon oxide film;
With the film remaining on the first silicon oxide film,
Exposing an upper surface of the first wiring layer;
A wiring metal is deposited on the entire surface of the substrate, and the first wiring
The second wiring layer, part of which is connected to the
Forming on a silicon oxide film of
It is assumed that.

(Equation 2) [Wherein, R1 is a phenyl group or a lower alkyl group;
2 is a hydrogen atom or a lower alkyl group;
May be the same or different groups, and different R2s are the same groups
May also be different groups. N is a positive number of 20 to 1000
Indicates an integer. ]

[0008]

In the method of manufacturing a semiconductor device according to the present invention ,
Of the fired film of silicon ladder polymer having organic groups
With a hole formed in a predetermined part located at the top of the wiring,
Fired film of silicon ladder polymer having the organic group and
Silicon dioxide film containing no carbon component
Dry etching using gas to etch i
When applied, firing of silicon ladder polymer with organic groups
The etching rate of the film is
The opening is smaller than that of the oxide film.
Firing of formed silicon ladder polymer with organic groups
Using the film as a mask, the silicon containing no carbon component
When an opening reaching the upper surface of the lower wiring is formed in the oxide film,
Both films are etched back and the carbon
Formed around the lower wiring of silicon oxide film containing no component
Silicon ladder poly in which the formed concave portion has the above organic group
Buried and planarized interlayer insulation
An edge membrane can be formed.

[0009]

[0010]

(Embodiment 1) FIG. 1 is a sectional view showing the steps of forming a multilayer wiring structure of a semiconductor device according to a first embodiment of the present invention. Denotes the same or corresponding portions, 8 denotes an organic SOG film,
8a is an opening formed in the organic SOG film 8, and 9 is an interlayer insulating film. The organic SOG film 8 is formed of an organic SOG film obtained by dissolving a silicon compound represented by a composition formula of the following formula (2) in an organic solvent.
OG is obtained by baking a spin-coated coating film and contains a carbon component, so that its etching rate is lower than that of a silicon oxide film containing no carbon component.

RnSi (OH) 4-n (2)

In the formula, R is a phenyl group or a lower alkyl group, and n is an integer of 1-3.

A process for forming a multilayer wiring structure will be described below with reference to FIG. As shown in FIGS. 1 (a) and 1 (b), a lower wiring 3 is selectively formed in a predetermined region on the upper surface of a silicon oxide film 2 covering the surface of a silicon semiconductor substrate 1, as in the prior art. In order to cover this lower wiring 3,
A plasma oxide film (silicon oxide film) 4 is formed over the entire surface of the silicon semiconductor substrate 1. Next, a silicon compound having an organic group represented by the above formula (2) is dissolved in an organic solvent together with a suitable organic binder and a vitreous forming agent.
When this solution is spin-coated on the plasma oxide film (silicon oxide film) 4 and then subjected to a heat treatment, the evaporation and dehydration / polymerization reaction of the solvent proceed, as shown in FIG. An organic SOG film 8 made of a silicon oxide film containing a carbon component is formed. Since the organic SOG film 8 is formed by spin coating, as shown in the figure, the organic SOG film 8 is formed thick in the step concave portions of the plasma oxide film (silicon oxide film) 4 and thinly formed in the step convex portions. It becomes a film excellent in. Next, as shown in FIG. 1 (d), a resist film 5 is applied and formed, and the photolithographic technique shown in FIG.
An opening 5a is formed in a predetermined portion of the resist film 5 as shown in FIG.
To form Next, as shown in FIG.
a using the resist film 5 on which the a
The G film 8 is subjected to dry etching with a mixed gas of CF4, CHF3, and Ar to form an opening 8a reaching the upper portion of the plasma oxide film 4. Next, as shown in FIG. 1 (g), after removing the resist film 5, the organic SOG film 8 and the plasma oxide film (silicon oxide film) 4 are coated with CF4, CHF3, and Ar in the same manner as described above. Using a mixed gas,
Dry etching is performed under the etching conditions shown in FIG.
At this time, as described above, since the etching rate of the organic SOG film 8 is lower than that of the plasma oxide film 4, the organic SOG film 8 in which the openings 8a are formed is used as a mask, as shown in FIG. A through hole 6 reaching the lower wiring 3 is formed in the plasma oxide film (silicon oxide film) 4, and
By the etch back, a planarizing insulating film 9 composed of the organic SOG film 8 and the plasma oxide film (silicon oxide film) 4 is formed. After that, when the wiring metal constituting the upper wiring is deposited on the entire surface of the silicon substrate, the contact hole 4a and the upper surface of the plasma oxide film (silicon oxide film) 4 are formed as shown in FIG. , And is covered with the upper wiring 7 having a uniform thickness.

FIG. 4 shows the relationship between the reaction temperature (° C.) and the etching rate (angstrom / min) of an organic SOG film (containing a methyl group as an organic group), and the relationship between other inorganic insulating films (silicon oxide films). In the figure, a is an etching rate of an inorganic SOG film (an SOG film obtained from a silicon compound having no organic group), and b is an etching rate of TEOS (tetra-ethyl orthosilicate). , C and d indicate etching rates of an organic SOG film containing a methyl group as an organic group, and e indicates an etching rate of a fired film of PPSQ (polyphenylsilsesquioxane) of a second embodiment described later. Here, for d and e, the etching rate of the organic SOG film having a large amount of carbon in the film corresponds to d, and the etching rate of the organic SOG film having a small amount of carbon in the film corresponds to c.

From this figure, it can be seen that in the present invention, the organic SOG
The etching temperature (reaction temperature) when etching the film 8 together with another silicon oxide film containing no carbon component is as follows:
It is understood that the etching rate is preferably set to 500 ° C. or less, which is sufficiently smaller than that of a silicon oxide film containing no other carbon component.

In the process of forming the multi-layer wiring structure according to the present embodiment, the plasma oxide film (silicon oxide film) 4
An organic SOG film 8 having excellent flatness is formed, and thereafter, a plasma oxide film (silicon oxide film) 4 is formed in a state where an opening 8a is formed in a predetermined portion of the organic SOG film 8 corresponding to the upper part of the lower wiring 3. and the organic SOG film 8, the mixed system gas CF4, CHF3, Ar etching silicon dioxide, for dry etching, slow organic SOG film 8 of etching rate <br/> over preparative becomes the mask At the same time, a through hole 6 following the lower wiring 3 is formed in the plasma oxide film (silicon oxide film) 4, and at the same time, the plasma oxide film (silicon oxide film) 4 and the organic SOG film 8 are etched back.
As a result, the step portion of the through hole 6 becomes gentle because the upper surface portion of the plasma oxide film (silicon oxide film) 4 is etched, and furthermore, the concave portion of the plasma oxide film (silicon oxide film) 4 becomes an organic SOG film 8. To form an interlayer insulating film 9 having excellent flatness. Therefore, the upper wiring 7 obtained by depositing a wiring metal on the interlayer insulating film 9 has a uniform layer thickness and does not cause disconnection or the like.

(Embodiment 2) FIG. 2 is a sectional view showing a multilayer wiring structure of a semiconductor device according to a second embodiment of the present invention. In the drawing, the same reference numerals as those in FIG. 1 denote the same or corresponding parts. Reference numeral 10 denotes a fired film of a silicon ladder polymer. Here, the fired film 10 of the silicon ladder polymer is prepared by dissolving a solution of a silicon ladder polymer having a repeating unit represented by the following general formula (1) in an organic solvent on a plasma oxide film (silicon oxide film) 4. It is obtained by spin coating and baking the obtained coating film.

[0018]

(Equation 3)

Wherein R 1 is a phenyl group or a lower alkyl group, R 2 is a hydrogen atom or a lower alkyl group,
The different R1 may be the same or different, and different R2
May be the same or different groups. N is 20 to 10
It is a positive integer of 00.

The process of forming the multilayer wiring structure in this embodiment is the same as that of the first embodiment except that the fired film 10 of silicon ladder polymer is formed on the plasma oxide film (silicon oxide film) 4 as described above. The description is omitted here.

As described above, FIG. 4E shows PPS which is a silicon ladder polymer represented by the above general formula.
The figure shows the etching rate of the fired film of Q (polyphenylsilsesquioxane). From this figure, the etching rate of the fired film of the silicon ladder polymer is sufficiently higher than that of the silicon oxide film containing no other carbon component. It turns out that it is small. Therefore, similarly to the first embodiment,
Spaced openings in baked film 10 of the silicon ladder polymer, plasma when subjected to dry etching and fired film 10 of a plasma oxide film (silicon oxide film) 4 and the silicon ladder polymer, a fired film 10 of the silicon ladder polymer as a mask At the same time as the contact hole 6 is formed in a predetermined portion of the oxide film (silicon oxide film) 4, an interlayer insulating film 9 planarized by etch back is formed.

In the semiconductor device of this embodiment, the etching rate of the fired film 10 of the silicon ladder polymer is sufficiently smaller than that of the plasma oxide film (silicon oxide film) 4, and an opening is formed in a predetermined portion. When the baked film 10 of the silicon ladder polymer and the plasma oxide film (silicon oxide film) 4 are simultaneously etched by the etching gas for etching silicon dioxide, the lower wiring 3 is formed in the same manner as in the first embodiment. Simultaneously with the formation of the through hole 6 following the upper surface, the concave portion of the plasma oxide film 4 is filled with the fired film 10 of the silicon ladder polymer, so that the interlayer insulating film 9 having excellent flatness can be formed. Therefore, the upper wiring 7 obtained by depositing a wiring metal on the interlayer insulating film 9 has a uniform layer thickness and is free from disconnection or the like.

In the above embodiment, a mixed gas of CF4, CHF3, and Ar is used as an etching gas for etching the plasma oxide film (silicon oxide film) 4 and the organic SOG film 8. However, CF4, CHF3, The same effect can be obtained by using another gas that can etch silicon dioxide, such as a mixed gas of He.

[0024]

As described above, the semiconductor according to the present invention is
The method of manufacturing the device is such that a lower wiring and an upper wiring are formed on a semiconductor substrate.
Line is connected through through hole in interlayer insulating film
In a method of manufacturing a semiconductor device having a multilayer wiring film formed thereon,
Forming a first wiring layer in a predetermined region on the semiconductor substrate
And the semiconductor layer so as to cover the first wiring layer.
A first shell containing no carbon component is applied to the entire surface of the body substrate.
A step of forming a silicon oxide film;
Resin with silicon ladder polymer dissolved on the upper surface of the passivation film
The solution is spin-coated and the resulting coating is baked to remove carbon
For forming a second silicon oxide film containing components
And above the first wiring layer of the second silicon oxide film
Forming an opening in a predetermined portion located in the portion;
Etching with etching gas to etch silicon
Greater than the first silicon oxide film in the second silicon oxide film.
By making use of the fact that the silicon oxide film is smaller,
In the state where
The second silicon oxide film is etched to form the second silicon oxide film.
A state in which a silicon oxide film is left on the first silicon oxide film
Exposing the upper surface of the first wiring layer in a state,
A wiring metal is deposited on the entire surface of the semiconductor substrate,
The second wiring layer, a part of which is connected to the first wiring layer, is
1, forming on the second silicon oxide film.
With this, the first arrangement is
The through-hole with the upper surface of the wire layer exposed and the step of the insulating oxide film is small.
Is formed and the first carbon-free
Ladder Poly with Silicon Oxide Film and Organic Group
Second Silico Containing Carbon Component Consisting of Fired Film of Mer
The oxide film is etched back to provide an interlayer with excellent flatness.
An insulating film can be formed, and as a result,
And the second wiring layer formed on the interlayer insulating oxide film
Layer thickness is uniform, and a highly reliable semiconductor device is obtained.
Has the effect.

[Brief description of the drawings]

FIGS. 1A to 1C are cross-sectional views showing steps of forming a multilayer wiring structure of a semiconductor device according to a first embodiment of the present invention.

FIG. 2 is a sectional view showing a multilayer wiring structure of a semiconductor device according to a second embodiment of the present invention.

FIG. 3 is a graph showing etching conditions when etching a plasma oxide film (silicon oxide film) and an organic SOG film in a step of forming the multilayer wiring structure shown in FIG.

FIG. 4 is a diagram showing a change in an etching rate with respect to a reaction temperature of an organic SOG film, a fired film of a silicon ladder polymer, and a silicon oxide film containing no other carbon component.

FIG. 5 is a cross-sectional view showing a step of forming a multilayer wiring structure of a conventional semiconductor device.

[Explanation of symbols]

 Reference Signs List 1 silicon semiconductor substrate 2 silicon oxide film 3 lower layer wiring 4 plasma oxide film (silicon oxide film) film 5 resist film 5a opening 6 through hole 7 upper layer wiring 8 organic SOG film 8a opening 9 interlayer insulating film 10 firing of silicon ladder polymer Film a, b, c, d, e Etching rate

──────────────────────────────────────────────────続 き Continued on the front page (58) Field surveyed (Int.Cl. ⁶ , DB name) H01L 21/3205 H01L 21/3213 H01L 21/768

Claims (1)

(57) [Claims] 1. A semiconductor device comprising : a lower wiring and an upper wiring formed on a semiconductor substrate;
Are connected through through holes in the interlayer insulating film
In a method of manufacturing a semiconductor device in which a wiring film is formed, a first wiring layer is formed in a predetermined region on the semiconductor substrate.
A process and an entire surface of the semiconductor substrate so as to cover the first wiring layer.
First silicon oxide film containing no carbon component
And forming a repeating unit on the upper surface of the first silicon oxide film.
Is a silicon ladder polymer represented by the following general formula (1)
Is spin-coated with a resin solution in which
Baking to form a second silicon oxide film containing a carbon component.
Forming a second silicon oxide film on the first wiring layer;
Forming an opening in a predetermined position, and etching with an etching gas for etching silicon dioxide.
The switching rate is higher than that of the first silicon oxide film.
Utilizing that the second silicon oxide film is smaller,
With the apertures formed, the etching gas
The first and second silicon oxide films are etched to form the second silicon oxide film.
Remaining on the first silicon oxide film.
Exposing the upper surface of the first wiring layer in the state in which
And depositing a wiring metal on the entire surface of the semiconductor substrate,
The second wiring layer, a part of which is connected to the first wiring layer, is
Forming on the first and second silicon oxide films
A method for manufacturing a semiconductor device, comprising: (Equation 1) [Wherein, R1 is a phenyl group or a lower alkyl group;
2 is a hydrogen atom or a lower alkyl group;
May be the same or different groups, and different R2s are the same groups
May also be different groups. N is a positive number of 20 to 1000
Indicates an integer. ]